CI_ROLE_END,
};
+enum ci_revision {
+ CI_REVISION_1X = 10, /* Revision 1.x */
+ CI_REVISION_20 = 20, /* Revision 2.0 */
+ CI_REVISION_21, /* Revision 2.1 */
+ CI_REVISION_22, /* Revision 2.2 */
+ CI_REVISION_23, /* Revision 2.3 */
+ CI_REVISION_24, /* Revision 2.4 */
+ CI_REVISION_25, /* Revision 2.5 */
+ CI_REVISION_25_PLUS, /* Revision above than 2.5 */
+ CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
+};
+
/**
* struct ci_role_driver - host/gadget role driver
* @start: start this role
* @role: current role
* @is_otg: if the device is otg-capable
* @fsm: otg finite state machine
- * @fsm_timer: pointer to timer list of otg fsm
+ * @otg_fsm_hrtimer: hrtimer for otg fsm timers
+ * @hr_timeouts: time out list for active otg fsm timers
+ * @enabled_otg_timer_bits: bits of enabled otg timers
+ * @next_otg_timer: next nearest enabled timer to be expired
* @work: work for role changing
* @wq: workqueue thread
* @qh_pool: allocation pool for queue heads
* @supports_runtime_pm: if runtime pm is supported
* @in_lpm: if the core in low power mode
* @wakeup_int: if wakeup interrupt occur
+ * @rev: The revision number for controller
*/
struct ci_hdrc {
struct device *dev;
bool is_otg;
struct usb_otg otg;
struct otg_fsm fsm;
- struct ci_otg_fsm_timer_list *fsm_timer;
+ struct hrtimer otg_fsm_hrtimer;
+ ktime_t hr_timeouts[NUM_OTG_FSM_TIMERS];
+ unsigned enabled_otg_timer_bits;
+ enum otg_fsm_timer next_otg_timer;
struct work_struct work;
struct workqueue_struct *wq;
bool supports_runtime_pm;
bool in_lpm;
bool wakeup_int;
+ enum ci_revision rev;
};
static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)