Intel xhci: Limit number of active endpoints to 64.

[deliverable/linux.git] / drivers / usb / host / xhci.h

diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index af8b66f2fd0050d9dc4a08fdd1ecf6fffba72b85..ac0196e7fcf11dba0c1df87ffb24ea57cd6c379f 100644 (file)
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -881,7 +881,9 @@ struct xhci_transfer_event {
 #define COMP_STOP_INVAL        27
 /* Control Abort Error - Debug Capability - control pipe aborted */
 #define COMP_DBG_ABORT 28
-/* TRB type 29 and 30 reserved */
+/* Max Exit Latency Too Large Error */
+#define COMP_MEL_ERR   29
+/* TRB type 30 reserved */
 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
 #define COMP_BUFF_OVER 31
 /* Event Lost Error - xHC has an "internal event overrun condition" */
@@ -964,6 +966,8 @@ struct xhci_event_cmd {
 /* The buffer pointer contains immediate data */
 #define TRB_IDT                        (1<<6)
 
+/* Block Event Interrupt */
+#define        TRB_BEI                 (1<<9)
 
 /* Control transfer TRB specific fields */
 #define TRB_DIR_IN             (1<<16)
@@ -1119,6 +1123,7 @@ struct xhci_ring {
         */
        u32                     cycle_state;
        unsigned int            stream_id;
+       bool                    last_td_was_short;
 };
 
 struct xhci_erst_entry {
@@ -1286,6 +1291,19 @@ struct xhci_hcd {
 #define XHCI_RESET_EP_QUIRK    (1 << 1)
 #define XHCI_NEC_HOST          (1 << 2)
 #define XHCI_AMD_PLL_FIX       (1 << 3)
+#define XHCI_SPURIOUS_SUCCESS  (1 << 4)
+/*
+ * Certain Intel host controllers have a limit to the number of endpoint
+ * contexts they can handle.  Ideally, they would signal that they can't handle
+ * anymore endpoint contexts by returning a Resource Error for the Configure
+ * Endpoint command, but they don't.  Instead they expect software to keep track
+ * of the number of active endpoints for them, across configure endpoint
+ * commands, reset device commands, disable slot commands, and address device
+ * commands.
+ */
+#define XHCI_EP_LIMIT_QUIRK    (1 << 5)
+       unsigned int            num_active_eps;
+       unsigned int            limit_active_eps;
        /* There are two roothubs to keep track of bus suspend info for */
        struct xhci_bus_state   bus_state[2];
        /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
@@ -1334,9 +1352,6 @@ static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
 static inline void xhci_writel(struct xhci_hcd *xhci,
                const unsigned int val, __le32 __iomem *regs)
 {
-       xhci_dbg(xhci,
-                       "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n",
-                       regs, val);
        writel(val, regs);
 }
 
@@ -1364,9 +1379,6 @@ static inline void xhci_write_64(struct xhci_hcd *xhci,
        u32 val_lo = lower_32_bits(val);
        u32 val_hi = upper_32_bits(val);
 
-       xhci_dbg(xhci,
-                       "`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n",
-                       regs, (long unsigned int) val);
        writel(val_lo, ptr);
        writel(val_hi, ptr + 1);
 }
@@ -1435,6 +1447,8 @@ void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
                struct xhci_ep_ctx *ep_ctx,
                struct xhci_virt_ep *ep);
+void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
+       struct xhci_virt_device *virt_dev, bool drop_control_ep);
 struct xhci_ring *xhci_dma_to_transfer_ring(
                struct xhci_virt_ep *ep,
                u64 address);