+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (validate_mips_insn): Move further up file.
+ Add insn_bits and decode_operand arguments. Use the mips_operand
+ fields to work out which bits an operand occupies. Detect double
+ definitions.
+ (validate_micromips_insn): Move further up file. Call into
+ validate_mips_insn.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips16_macro_build): Remove 'Y' case.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (macro_build): Take an int for "C", "k", "\\"
+ and "~".
+ (macro): Update accordingly.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (imm_expr, imm2_expr, offset_expr): Tweak commentary.
+ (imm_reloc): Delete.
+ (md_assemble): Remove imm_reloc handling.
+ (mips_ip): Update commentary. Use offset_expr and offset_reloc
+ rather than imm_expr and imm_reloc for 'i', 'j' and 'u'.
+ Use a temporary array rather than imm_reloc when parsing
+ constant expressions. Remove imm_reloc initialization.
+ (mips16_ip): Update commentary. Use offset_expr and offset_reloc
+ for the relaxable field. Use a relax_char variable to track the
+ type of this field. Remove imm_reloc initialization.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips16_ip): Handle "I".
+
+2013-07-12 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (mips_flag_nan2008): New variable.
+ (options): Add OPTION_NAN enum value.
+ (md_longopts): Handle it.
+ (md_parse_option): Likewise.
+ (s_nan): New function.
+ (mips_elf_final_processing): Handle EF_MIPS_NAN2008.
+ (md_show_usage): Add -mnan.
+
+ * doc/as.texinfo (Overview): Add -mnan.
+ * doc/c-mips.texi (MIPS Opts): Document -mnan.
+ (MIPS NaN Encodings): New node. Document .nan directive.
+ (MIPS-Dependent): List the new node.
+
+2013-07-09 Tristan Gingold <gingold@adacore.com>
+
+ * configure.com: Define HAVE_SYS_TYPES_H and HAVE_UNISTD_H
+
+2013-07-08 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_ip): Unconditionally parse an expression
+ for 'A' and assume that the constant has been elided if the result
+ is an O_register.
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (gprel16_reloc_p): New function.
+ (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
+ BFD_RELOC_UNUSED.
+ (offset_high_part, small_offset_p): New functions.
+ (nacro): Use them. Remove *_OB and *_DOB cases. For single-
+ register load and store macros, handle the 16-bit offset case first.
+ If a 16-bit offset is not suitable for the instruction we're
+ generating, load it into the temporary register using
+ ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the
+ M_L_DAB code once the address has been constructed. For double load
+ and store macros, again handle the 16-bit offset case first.
+ If the second register cannot be accessed from the same high
+ part as the first, load it into AT using ADDRESS_ADDI_INSN.
+ Fix the handling of LD in cases where the first register is the
+ same as the base. Also handle the case where the offset is
+ not 16 bits and the second register cannot be accessed from the
+ same high part as the first. For unaligned loads and stores,
+ fuse the offbits == 12 and old "ab" handling. Apply this handling
+ whenever the second offset needs a different high part from the first.
+ Construct the offset using ADDRESS_ADDI_INSN where possible,
+ for offbits == 16 as well as offbits == 12. Use offset_reloc
+ when constructing the individual loads and stores.
+ (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
+ and offset_reloc before matching against a particular opcode.
+ Handle elided 'A' constants. Allow 'A' constants to use
+ relocation operators.
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
+ (mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions.
+ Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_ip): Preserve the real bit number for "+p".
+ Require the msb to be <= 31 for "+s". Check that the size is <= 31
+ for both "+s" and "+S".
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn):
+ (mips_ip, mips16_ip): Handle "+i".
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete.
+ (micromips_to_32_reg_h_map): Rename to...
+ (micromips_to_32_reg_h_map1): ...this.
+ (micromips_to_32_reg_i_map): Rename to...
+ (micromips_to_32_reg_h_map2): ...this.
+ (mips_lookup_reg_pair): New function.
+ (gpr_write_mask, macro): Adjust after above renaming.
+ (validate_micromips_insn): Remove "mi" handling.
+ (mips_ip): Likewise. Parse both registers in a pair for "mh".
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
+ (mips_ip): Remove "+D" and "+T" handling.
+
+2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * config/tc-s390.c (md_gather_operands, md_apply_fix): Support new
+ relocs.
+
+2013-07-03 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): Merge got_prel19 into got.
+
+2013-07-02 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * config/tc-aarch64.c (md_apply_fix): Reorder case values.
+ (aarch64_force_relocation): Likewise.
+
+2013-07-02 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (ppc_elf_adjust_symtab): Don't make .TOC. weak.
+
+2013-06-26 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * doc/as.texinfo (Overview): Remove @samp from MIPS ISA names.
+ * doc/c-mips.texi (MIPS Options): Remove @sc from MIPS ISA names.
+ Replace @sc{mips16} with literal `MIPS16'.
+ (MIPS ISA): Replace @sc{mips3} with literal `MIPS III'.
+
+2013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): Replace
+ BFD_RELOC_AARCH64_LD64_GOT_LO12_NC with
+ BFD_RELOC_AARCH64_LD_GOT_LO12_NC; likewise to
+ BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC and
+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC.
+ (md_apply_fix): Handle BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
+ BFD_RELOC_AARCH64_LD32_GOT_LO12_NC,
+ BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
+ BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC,
+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC and
+ BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC.
+ (aarch64_force_relocation): Likewise.
+
+2013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * config/tc-aarch64.c (ilp32_p): New static variable.
+ (elf64_aarch64_target_format): Return the target according to the
+ value of 'ilp32_p'.
+ (md_begin): Determine 'mach' according to the value of 'ilp32_p'.
+ (aarch64_opts): Add support for options '-milp32' and '-mlp64'.
+ (aarch64_dwarf2_addr_size): New function.
+ * config/tc-aarch64.h (aarch64_dwarf2_addr_size): New declaration.
+ (DWARF2_ADDR_SIZE): New define.
+
+2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/c-mips.texi: Use ISA instead of @sc{isa}.
+
+2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
+
+2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (mips_set_options): Add insn32 member.
+ (mips_opts): Initialize it.
+ (NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode.
+ (options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values.
+ (md_longopts): Add "minsn32" and "mno-insn32" options.
+ (is_size_valid): Handle insn32 mode.
+ (md_assemble): Pass instruction string down to macro.
+ (brk_fmt): Add second dimension and insn32 mode initializers.
+ (mfhl_fmt): Likewise.
+ (BRK_FMT, MFHL_FMT): Handle insn32 mode.
+ (macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding.
+ (macro_build_jalr, move_register): Handle insn32 mode.
+ (macro_build_branch_rs): Likewise.
+ (macro): Handle insn32 mode.
+ <M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases.
+ (mips_ip): Handle insn32 mode.
+ (md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32.
+ (s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops.
+ (mips_handle_align): Handle insn32 mode.
+ (md_show_usage): Add -minsn32 and -mno-insn32.
+
+ * doc/as.texinfo (Target MIPS options): Add -minsn32 and
+ -mno-insn32 options.
+ (-minsn32, -mno-insn32): New options.
+ * doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32
+ options.
+ (MIPS assembly options): New node. Document .set insn32 and
+ .set noinsn32.
+ (MIPS-Dependent): List the new node.
+
+2013-06-25 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-msp430.c (msp430_srcoperand): Do not allow the use of
+ the PC in indirect addressing on 430xv2 parts.
+ (msp430_operands): Add version test to hardware bug encoding
+ restrictions.
+
+2013-06-24 Roland McGrath <mcgrathr@google.com>
+
+ * config/tc-arm.c (parse_reg_list): Use skip_past_char for '}',
+ so it skips whitespace before it.
+ (s_arm_unwind_save_mmxwr, s_arm_unwind_save_mmxwcg): Likewise.
+
+ * config/tc-arm.c (arm_symbol_chars): Include '{' and '}'.
+ (arm_reg_parse_multi): Skip whitespace first.
+ (parse_reg_list): Likewise.
+ (parse_vfp_reg_list): Likewise.
+ (s_arm_unwind_save_mmxwcg): Likewise.
+
+2013-06-24 Nick Clifton <nickc@redhat.com>
+
+ PR gas/15623
+ * config/tc-arm.c (do_t_smc): Mark as ending an IT block.
+
+2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments.
+
+2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c: Assert that offsetT and valueT are at least
+ 8 bytes in size.
+ (GPR_SMIN, GPR_SMAX): New macros.
+ (macro, mips_ip): Remove code for 4-byte valueT and offsetT.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c: Remove OBJ_ELF, OBJ_MAYBE_ELF and IS_ELF
+ conditions. Remove any code deselected by them.
+ (s_mips_frame, s_mips_mask): Handle ECOFF_DEBUGGING case first.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * NEWS: Note removal of ECOFF support.
+ * doc/as.texinfo (--emulation): Update for the removal of MIPS ECOFF.
+ * Makefile.am (TARG_ENV_HFILES): Remove config/te-lnews.h.
+ (MULTI_CFILES): Remove config/e-mipsecoff.c.
+ * Makefile.in: Regenerate.
+ * configure.in: Remove MIPS ECOFF references.
+ (mips-sony-bsd*, mips-*-bsd*, mips-*-lnews*-ecoff, mips-*-*-ecoff):
+ Delete cases.
+ (mips-*-irix5*-*, mips*-*-linux*-*, mips*-*-freebsd*)
+ (mips*-*-kfreebsd*-gnu, mips-*-*-elf): Fold into...
+ (mips-*-*): ...this single case.
+ (mipsbecoff, mipslecoff, mipsecoff): Remove emulations. Expect
+ MIPS emulations to be e-mipself*.
+ * configure: Regenerate.
+ * configure.tgt (mips-sony-bsd*, mips-*-ultrix*, mips-*-osf*)
+ (mips-*-ecoff*, mips-*-pe*, mips-*-irix*, ips-*-lnews*, mips-*-riscos*)
+ (mips-*-sysv*): Remove coff and ecoff cases.
+ * as.c (mipsbecoff, mipslecoff, mipsecoff): Remove.
+ * ecoff.c: Remove reference to MIPS ECOFF.
+ * config/e-mipsecoff.c, config/te-lnews.h: Delete files.
+ * config/tc-mips.c (ECOFF_LITTLE_FORMAT): Delete.
+ (RDATA_SECTION_NAME, mips_target_form): Remove COFF and ECOFF cases.
+ (mips_hi_fixup): Tweak comment.
+ (append_insn): Require a howto.
+ (mips_after_parse_args): Remove OBJ_MAYBE_ECOFF code.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/as.texinfo: Use MIPS rather than @sc{mips} throughout.
+ Use "CPU" instead of "cpu".
+ * doc/c-mips.texi: Likewise.
+ (MIPS Opts): Rename to MIPS Options.
+ (MIPS option stack): Rename to MIPS Option Stack.
+ (MIPS ASE instruction generation overrides): Rename to
+ MIPS ASE Instruction Generation Overrides (for now).
+ (MIPS floating-point): Rename to MIPS Floating-Point.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/c-mips.texi (MIPS Macros): New section.
+ (MIPS Object): Replace with...
+ (MIPS Small Data): ...this new section.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/c-mips.texi (MIPS symbol sizes): Move section further up file.
+ Capitalize name. Use @kindex instead of @cindex for .set entries.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/c-mips.texi (MIPS Stabs): Remove section.
+
+2013-06-20 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS, ISA_SUPPORTS_DSP_ASE)
+ (ISA_SUPPORTS_DSP64_ASE, ISA_SUPPORTS_DSPR2_ASE, ISA_SUPPORTS_EVA_ASE)
+ (ISA_SUPPORTS_MT_ASE, ISA_SUPPORTS_MCU_ASE, ISA_SUPPORTS_VIRT_ASE)
+ (ISA_SUPPORTS_VIRT64_ASE): Delete.
+ (mips_ase): New structure.
+ (mips_ases): New table.
+ (FP64_ASES): New macro.
+ (mips_ase_groups): New array.
+ (mips_isa_rev, mips_ase_mask, mips_check_isa_supports_ase)
+ (mips_check_isa_supports_ases, mips_set_ase, mips_lookup_ase): New
+ functions.
+ (is_opcode_valid): Use mips_ases to get the 64-bit ASE flags.
+ (md_parse_option): Use mips_ases and mips_set_ase instead of
+ separate case statements for each ASE option.
+ (mips_after_parse_args): Use FP64_ASES. Use
+ mips_check_isa_supports_ases to check the ASEs against
+ other options.
+ (s_mipsset): Use mips_ases and mips_set_ase instead of
+ separate if statements for each ASE option. Use
+ mips_check_isa_supports_ases, even when a non-ASE option
+ is specified.
+
+2013-06-19 Greta Yorsh <Greta.Yorsh@arm.com>
+
+ * config/tc-arm.c (arm_cpus): Add support for Cortex-A12.
+
+2013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (md_shortopts, options, md_longopts)
+ (md_longopts_size): Move earlier in file.
+
+2013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_set_options): Replace separate "ase_*" fields
+ with a single "ase" bitmask.
+ (mips_opts): Update accordingly.
+ (file_ase, file_ase_explicit): New variables.
+ (file_ase_mips3d, file_ase_mdmx, file_ase_smartmips, file_ase_dsp)
+ (file_ase_dspr2, file_ase_eva, file_ase_mt, file_ase_virt): Delete.
+ (ISA_HAS_ROR): Adjust for mips_set_options change.
+ (is_opcode_valid): Take the base ase mask directly from mips_opts.
+ (mips_ip): Adjust for mips_set_options change.
+ (md_parse_option): Likewise. Update file_ase_explicit.
+ (mips_after_parse_args): Adjust for mips_set_options change.
+ Use bitmask operations to select the default ASEs. Set file_ase
+ rather than individual per-ASE variables.
+ (s_mipsset): Adjust for mips_set_options change.
+ (mips_elf_final_processing): Test file_ase rather than
+ file_ase_mdmx. Remove commented-out code.
+
+2013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_cpu_info): Add an "ase" field.
+ (MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT)
+ (MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX, MIPS_CPU_ASE_DSPR2)
+ (MIPS_CPU_ASE_MCU, MIPS_CPU_ASE_VIRT, MIPS_CPU_ASE_EVA): Delete.
+ (mips_after_parse_args): Use the new "ase" field to choose
+ the default ASEs.
+ (mips_cpu_info_table): Move ASEs from the "flags" field to the
+ "ase" field.
+
+2013-06-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/tc-arm.c (symbol_preemptible): New function.
+ (relax_branch): Use it.
+
+2013-06-17 Catherine Moore <clm@codesourcery.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+ Chao-Ying Fu <fu@mips.com>
+
+ * config/tc-mips.c (mips_set_options): Add ase_eva.
+ (mips_set_options mips_opts): Add ase_eva.
+ (file_ase_eva): Declare.
+ (ISA_SUPPORTS_EVA_ASE): Define.
+ (IS_SEXT_9BIT_NUM): Define.
+ (MIPS_CPU_ASE_EVA): Define.
+ (is_opcode_valid): Add support for ase_eva.
+ (macro_build): Likewise.
+ (macro): Likewise.
+ (validate_mips_insn): Likewise.
+ (validate_micromips_insn): Likewise.
+ (mips_ip): Likewise.
+ (options): Add OPTION_EVA and OPTION_NO_EVA.
+ (md_longopts): Add -meva and -mno-eva.
+ (md_parse_option): Process new options.
+ (mips_after_parse_args): Check for valid EVA combinations.
+ (s_mipsset): Likewise.
+
+2013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
+
+ * dwarf2dbg.h (dwarf2_move_insn): Declare.
+ * dwarf2dbg.c (line_subseg): Add pmove_tail.
+ (get_line_subseg): Add create_p argument. Initialize pmove_tail.
+ (dwarf2_gen_line_info_1): Update call accordingly.
+ (dwarf2_move_insn): New function.
+ * config/tc-mips.c (append_insn): Use dwarf2_move_insn.
+
+2013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
+
+ Revert:
+
+ 2011-09-05 Richard Sandiford <rdsandiford@googlemail.com>
+
+ PR gas/13024
+ * dwarf2dbg.c (pending_lines, pending_lines_tail): New variables.
+ (dwarf2_gen_line_info_1): Delete.
+ (dwarf2_push_line, dwarf2_flush_pending_lines): New functions.
+ (dwarf2_gen_line_info, dwarf2_emit_label): Use them.
+ (dwarf2_consume_line_info): Call dwarf2_flush_pending_lines.
+ (dwarf2_directive_loc): Push previous .locs instead of generating
+ them immediately.
+
+2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
+
+ * config/tc-mips.c (ISA_SUPPORTS_VIRT_ASE): Support micromips.
+ (ISA_SUPPORTS_VIRT64_ASE): Support 64-bit micromips.
+
+2013-06-13 Nick Clifton <nickc@redhat.com>
+
+ PR gas/15602
+ * config/tc-m68k.h (TC_CHECK_ADJUSTED_BROKEN_DOT_WORD): Define.
+ * config/tc-m68k.c (tc_m68k_check_adjusted_broken_word): New
+ function. Generates an error if the adjusted offset is out of a
+ 16-bit range.
+
+2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
+
+ * config/tc-nios2.c (md_apply_fix): Mask constant
+ BFD_RELOC_NIOS2_HIADJ16 value to 16 bits.
+
+2013-06-10 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (append_insn): Don't do branch relaxation for
+ MIPS-3D instructions either.
+ (md_convert_frag): Update the COPx branch mask accordingly.
+
+ * config/tc-mips.c (md_show_usage): Document --[no-]relax-branch
+ option.
+ * doc/as.texinfo (Overview): Add --relax-branch and
+ --no-relax-branch.
+ * doc/c-mips.texi (MIPS Opts): Document --relax-branch and
+ --no-relax-branch.
+
+2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
+
+ * config/tc-nios2.c (nios2_parse_args): Allow trap argument to
+ omitted.
+
+2013-06-08 Catherine Moore <clm@codesourcery.com>
+
+ * config/tc-mips.c (is_opcode_valid): Build ASE mask.
+ (is_opcode_valid_16): Pass ase value to opcode_is_member.
+ (append_insn): Change INSN_xxxx to ASE_xxxx.
+
+2013-06-01 George Thomas <george.thomas@atmel.com>
+
+ * gas/config/tc-avr.c: Change ISA for devices with USB support to
+ AVR_ISA_XMEGAU
+
+2013-05-31 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (md_begin): Don't align text/data/bss sections
+ for ELF.
+
+2013-05-31 Paul Brook <paul@codesourcery.com>
+
+ gas/
+ * config/tc-mips.c (s_ehword): New.
+
+2013-05-30 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-mips.c (md_apply_fix): Support BFD_RELOC_MIPS_EH.
+
+2013-05-29 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * write.c (resolve_reloc_expr_symbols): On REL targets don't
+ convert relocs who have no relocatable field either. Rephrase
+ the conditional so that the PC-relative check is only applied
+ for REL targets.
+
+2013-05-28 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
+
+ * config/tc-mips.c (macro) <ld>: Don't use $zero for address
+ calculation.
+
+2013-05-28 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): Update to use
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 instead of
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE.
+ (md_apply_fix): Likewise.
+ (aarch64_force_relocation): Likewise.
+
+2013-05-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/tc-arm.c (it_fsm_post_encode): Improve
+ warning messages about deprecated IT block formats.
+
+2013-05-28 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * config/tc-aarch64.c (md_apply_fix): Move value range checking
+ inside fx_done condition.
+
+2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
+
+ * config/tc-mips.c (macro): Handle M_LQC2_AB and M_SQC2_AB.
+
+2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
+
+ * config/tc-ppc.c (ppc_setup_opcodes): Use new_seg to fix error
+ and clean up warning when using PRINT_OPCODE_TABLE.
+
+2013-05-20 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_apply_fix): Hoist code common to insn
+ and data fixups performing shift/high adjust/sign extension on
+ fieldval. Sink fx_pcrel handling and checks. Use fixP->fx_size
+ when writing data fixups rather than recalculating size.
+
+2013-05-16 Jan-Benedict Glaw <jbglaw@lug-owl.de>
+
+ * doc/c-msp430.texi: Fix typo.
+
+2013-05-16 Tristan Gingold <gingold@adacore.com>
+
+ * config/tc-ppc.c (ppc_is_toc_sym): Symbols of class XMC_TC
+ are also TOC symbols.
+
+2013-05-16 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-msp430.c: Make -mmcu recognise more part numbers.
+ Add -mcpu command to specify core type.
+ * doc/c-msp430.texi: Update documentation.
+
+2013-05-09 Andrew Pinski <apinski@cavium.com>
+
+ * config/tc-mips.c (struct mips_set_options): New ase_virt field.
+ (mips_opts): Update for the new field.
+ (file_ase_virt): New variable.
+ (ISA_SUPPORTS_VIRT_ASE): New macro.
+ (ISA_SUPPORTS_VIRT64_ASE): New macro.
+ (MIPS_CPU_ASE_VIRT): New define.
+ (is_opcode_valid): Handle ase_virt.
+ (macro_build): Handle "+J".
+ (validate_mips_insn): Likewise.
+ (mips_ip): Likewise.
+ (enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
+ (md_longopts): Add mvirt and mnovirt
+ (md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
+ (mips_after_parse_args): Handle ase_virt field.
+ (s_mipsset): Handle "virt" and "novirt".
+ (mips_elf_final_processing): Add a comment about virt ASE might need
+ a new flag.
+ (md_show_usage): Print out the usage of -mvirt and mno-virt options.
+ * doc/c-mips.texi: Document -mvirt and -mno-virt.
+ Document ".set virt" and ".set novirt".
+
+2013-05-09 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_apply_fix): Sign extend fieldval under
+ control of operand flag bits.
+
+2013-05-07 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (PPC_VLE_SPLIT16A): Delete unused macro.
+ (PPC_VLE_SPLIT16D, PPC_VLE_LO16A, PPC_VLE_LO16D): Likewise.
+ (PPC_VLE_HI16A, PPC_VLE_HI16D): Likewise.
+ (PPC_VLE_HA16A, PPC_VLE_HA16D): Likewise.
+ (md_apply_fix): Set fx_no_overflow for assorted relocations.
+ Shift and sign-extend fieldval for use by some VLE reloc
+ operand->insert functions.
+
+2013-05-06 Paul Brook <paul@codesourcery.com>
+ Catherine Moore <clm@codesourcery.com>
+
+ * config/tc-mips.c (md_pcrel_from): Handle BFD_RELOC_32_PCREL.
+ (limited_pcrel_reloc_p): Likewise.
+ (md_apply_fix): Likewise.
+ (tc_gen_reloc): Likewise.
+
+2013-05-06 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (limited_pcrel_reloc_p): New function.
+ (mips_fix_adjustable): Adjust pc-relative check to use
+ limited_pc_reloc_p.
+
+2013-05-02 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_pseudo_table): Add stabd and stabs entries.
+ (s_mips_stab): Do not restrict to stabn only.
+
+2013-05-02 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-msp430.c: Add support for the MSP430X architecture.
+ Add code to insert a NOP instruction after any instruction that
+ might change the interrupt state.
+ Add support for the LARGE memory model.
+ Add code to initialise the .MSP430.attributes section.
+ * config/tc-msp430.h: Add support for the MSP430X architecture.
+ * doc/c-msp430.texi: Document the new -mL and -mN command line
+ options.
+ * NEWS: Mention support for the MSP430X architecture.
+
+2013-05-01 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * configure.tgt: Replace alpha*-*-linuxecoff* pattern with
+ alpha*-*-linux*ecoff*.
+
+2013-04-30 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
+
+ * config/tc-mips.c (mips_ip): Add sizelo.
+ For "+C", "+G", and "+H", set sizelo and compare against it.
+
+2013-04-29 Nick Clifton <nickc@redhat.com>
+
+ * as.c (Options): Add -gdwarf-sections.
+ (parse_args): Likewise.
+ * as.h (flag_dwarf_sections): Declare.
+ * dwarf2dbg.c (emit_fixed_inc_line_addr): Skip section changes.
+ (process_entries): When -gdwarf-sections is enabled generate
+ fragmentary .debug_line sections.
+ (out_debug_line): Set the section for the .debug_line section end
+ symbol.
+ * doc/as.texinfo: Document -gdwarf-sections.
+ * NEWS: Mention -gdwarf-sections.
+
+2013-04-26 Christian Groessler <chris@groessler.org>
+
+ * config/tc-z8k.c (md_parse_option): Set z8k_target_from_cmdline
+ according to the target parameter. Don't call s_segm since s_segm
+ calls bfd_set_arch_mach using stdoutput, but stdoutput isn't
+ initialized yet.
+ (md_begin): Call s_segm according to target parameter from command
+ line.
+
+2013-04-25 Alan Modra <amodra@gmail.com>
+
+ * configure.in: Allow little-endian linux.
+ * configure: Regenerate.
+
+2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
+
+ * config/tc-nios2.c (nios2_control_register_arg_p): Rename
+ "fstatus" control register to "eccinj".
+
+2013-04-19 Kai Tietz <ktietz@redhat.com>
+
+ * configure.tgt (i386-*-cygwin): Handle x86_64 cygwin.
+
+2013-04-15 Julian Brown <julian@codesourcery.com>
+
+ * expr.c (add_to_result, subtract_from_result): Make global.
+ * expr.h (add_to_result, subtract_from_result): Add prototypes.
+ * config/tc-sh.c (sh_optimize_expr): Use add_to_result,
+ subtract_from_result to handle extra bit of precision for .sleb128
+ directive operands.
+
+2013-04-10 Julian Brown <julian@codesourcery.com>
+
+ * read.c (convert_to_bignum): Add sign parameter. Use it
+ instead of X_unsigned to determine sign of resulting bignum.
+ (emit_expr): Pass extra argument to convert_to_bignum.
+ (emit_leb128_expr): Use X_extrabit instead of X_unsigned. Pass
+ X_extrabit to convert_to_bignum.
+ (parse_bitfield_cons): Set X_extrabit.
+ * expr.c (make_expr_symbol, expr_build_uconstant, operand):
+ Initialise X_extrabit field as appropriate.
+ (add_to_result): New.
+ (subtract_from_result): New.
+ (expr): Use above.
+ * expr.h (expressionS): Add X_extrabit field.
+
+2013-04-10 Jan Beulich <jbeulich@suse.com>
+
+ * gas/config/tc-arm.c (encode_arm_addr_mode_3): Only reject base
+ register being PC when is_t or writeback, and use distinct
+ diagnostic for the latter case.
+
+2013-04-10 Jan Beulich <jbeulich@suse.com>
+
+ * gas/config/tc-arm.c (parse_operands): Re-write
+ po_barrier_or_imm().
+ (do_barrier): Remove bogus constraint().
+ (do_t_barrier): Remove.
+
+2013-04-09 Joerg Wunsch <joerg.wunsch@atmel.com>
+
+ * gas/config/tc-avr.c (mcu_types): Add ATmega64RFR2,
+ ATmega644RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega256RFR2,
+ ATmega2564RFR2
+ * gas/doc/c-avr.texi (-mmcu documentation): Likewise.
+
+2013-04-09 Jan Beulich <jbeulich@suse.com>
+
+ * gas/config/tc-arm.c (do_vmrs): Accept all control registers.
+ Use local variable Rt in more places.
+ (do_vmsr): Accept all control registers.
+
+2013-04-09 Jan Beulich <jbeulich@suse.com>
+
+ * gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix
+ if there was none specified for moves between scalar and core
+ register.
+
+2013-04-09 Jan Beulich <jbeulich@suse.com>
+
+ * gas/config/tc-arm.c (do_neon_ldx_stx): Reject VSTn in the
+ NEON_ALL_LANES case.
+
+2013-04-08 Jan Beulich <jbeulich@suse.com>
+
+ * gas/config/tc-arm.c (do_neon_ldr_str): Correct disgnostics for
+ PC-relative VSTR.
+
+2013-04-08 Jan Beulich <jbeulich@suse.com>
+
+ * gas/config/tc-arm.c (reg_names): Convert duplicate SP_fiq
+ entry to sp_fiq.
+
+2013-04-03 Alan Modra <amodra@gmail.com>
+
+ * doc/as.texinfo: Add support to generate man options for h8300.
+ * doc/c-h8300.texi: Likewise.
+
+2013-03-28 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ * config/tc-arm.c (arm_cpus): Add support for Cortex-A53 and
+ Cortex-A57.
+
+2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
+
+ PR binutils/15068
+ * config/tc-tic6x.c (tic6x_try_encode): Add use of bitfields array.
+
+2013-03-26 Nick Clifton <nickc@redhat.com>
+
+ PR gas/15295
+ * listing.c (rebuffer_line): Rewrite to avoid seeking back to the
+ start of the file each time.
+
+ PR gas/15178
+ * config/tc-sparc.h (ELF_TARGET_FORMAT): Set to elf32-sparc for
+ FreeBSD targets.
+
+2013-03-26 Douglas B Rupp <rupp@gnat.com>
+
+ * config/tc-ia64.c (emit_one_bundle): Move last_slot adjustment
+ after fixup.
+
2013-03-21 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (encode_thumb32_addr_mode): Emit an error for all