+2007-04-20 Nathan Sidwell <nathan@codesourcery.com>
+
+ * config/m68k-parse.h (RAMBAR_ALT): New.
+ * config/tc-m68k.c (mcf5206_ctrl, mcf5307_ctrl): New.
+ (mcf_ctrl, mcf5208_ctrl, mcf5210a_ctrl, mcf5213_ctrl, mcf52235_ctrl,
+ mcf5225_ctrl, mcf5235_ctrl, mcf5271_ctrl, mcf5275_ctrl,
+ mcf5282_ctrl, mcf5329_ctrl, mcf5373_ctrl, mcfv4e_ctrl,
+ mcf5475_ctrl, mcf5485_ctrl): Add RAMBAR synonym for
+ RAMBAR1.
+ (mcf5272_ctrl): Add RAMBAR0, replace add RAMBAR with RAMBAR_ALT.
+ (m68k_cpus): Adjust 5206, 5206e & 5307 entries.
+ (m68k_ip) <Case J>: Detect when RAMBAR_ALT should be used. Add it
+ to control register mapping.
+
+2007-04-20 Alan Modra <amodra@bigpond.net.au>
+
+ * messages.c (as_internal_value_out_of_range): Fix typo in
+ error message. Return after printing domain error.
+ * config/tc-ppc.c (ppc_insert_operand): Preserve low zero bits
+ in max when shifting right.
+
+2007-04-20 Alan Modra <amodra@bigpond.net.au>
+
+ * messages.c (as_internal_value_out_of_range): Extend to report
+ errors for values with invalid low bits set.
+ * config/tc-ppc.c (ppc_setup_opcodes): Check powerpc_operands bitm
+ fields. Check that operands and opcode fields are disjoint.
+ (ppc_insert_operand): Check operands using mask rather than bit
+ count. Check low bits too. Handle PPC_OPERAND_PLUS1. Adjust
+ insertion code.
+ (md_apply_fix): Adjust for struct powerpc_operand change.
+
+2007-04-19 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (md_assemble): Only allow 16-bit instructions on
+ Thumb-1. Add sanity check for bogus relaxations.
+
+2007-04-19 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (insns): Allow rsb and rsbs on Thumb-1.
+
+2007-04-19 Alan Modra <amodra@bigpond.net.au>
+
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+
+2007-04-19 Nathan Froyd <froydnj@codesourcery.com>
+
+ * doc/c-ppc.texi (PowerPC-Opts): Document -me500, -me500x2, -mspe.
+
+2007-04-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * doc/c-i386.texi; Document .ssse3, .sse4.1, .sse4.2 and .sse4.
+
+2007-04-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (cpu_arch): Add .sse4.2 and .sse4.
+ (match_template): Handle operand size for crc32 in SSE4.2.
+ (process_suffix): Handle operand type for crc32 in SSE4.2.
+ (output_insn): Support SSE4.2.
+
+2007-04-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (cpu_arch): Add .sse4.1.
+ (process_operands): Adjust implicit operand for blendvpd,
+ blendvps and pblendvb in SSE4.1.
+ (output_insn): Support SSE4.1.
+
+2007-04-18 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (do_t_rsb): Use 16-bit encoding when possible.
+
+2007-04-16 Kaz Kojima <kkojima@rr.iij4u.or.jp>
+
+ * config/tc-sh.c (sh_handle_align): Call as_bad_where instead
+ of as_warn_where for misaligned data.
+
+2007-04-15 Kaz Kojima <kkojima@rr.iij4u.or.jp>
+
+ * config/tc-sh.c (align_test_frag_offset_fixed_p): Handle
+ rs_fill frags.
+
+2007-04-14 Steve Ellcey <sje@cup.hp.com>
+
+ * Makefile.am: Add ACLOCAL_AMFLAGS.
+ * Makefile.in: Regenerate.
+
+2007-04-14 Kaz Kojima <kkojima@rr.iij4u.or.jp>
+
+ * config/tc-sh.c (align_test_frag_offset_fixed_p): New.
+ (sh_optimize_expr): Likewise.
+ * config/tc-sh.h (md_optimize_expr): Define.
+ (sh_optimize_expr): Prototype.
+
+2007-04-06 Matt Thomas <matt@netbsd.org>
+
+ * config/tc-vax.c (vax_cons): Added to support %pcrel{8,16,32}(exp)
+ to emit pcrel relocations by DWARF2 in non-code sections. Borrowed
+ heavily from tc-sparc.c. (vax_cons_fix_new): Likewise.
+
+2007-04-04 Kazu Hirata <kazu@codesourcery.com>
+
+ * config/tc-m68k.c (HAVE_LONG_BRANCH): Add fido_a.
+
+2007-04-04 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (do_neon_ext): Enforce immediate range.
+ (insns): Use I15 for vext.
+
+2007-04-04 Paul Brook <paul@codesourcery.com>
+
+ * configure.tgt: Loosen checks for arm uclinux eabi targets.
+
+2007-04-02 Sterling Augustine <sterling@tensilica.com>
+
+ * config/tc-xtensa.c (xtensa_flush_pending_output): Check
+ outputting_stabs_line_debug.
+
2007-03-26 Anatoly Sokolov <aesok@post.ru>
* config/tc-avr.c (mcu_types): Add support for at90pwm1, at90usb82,