+2017-10-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/22352
+ * config/tc-i386.c (check_VecOperands): Also check XMM register
+ for invalid register in AVX512 gathers.
+ * testsuite/gas/i386/vgather-check.s: Add tests for AVX512
+ gathers with XMM register.
+ * testsuite/gas/i386/x86-64-vgather-check.s: Likewise.
+ * testsuite/gas/i386/vgather-check-error.l: Updated.
+ * testsuite/gas/i386/vgather-check-none.d: Likewise.
+ * testsuite/gas/i386/vgather-check-warn.d: Likewise.
+ * testsuite/gas/i386/vgather-check-warn.e: Likewise.
+ * testsuite/gas/i386/vgather-check.d: Likewise.
+ * testsuite/gas/i386/x86-64-vgather-check-error.l: Likewise.
+ * testsuite/gas/i386/x86-64-vgather-check-none.d: Likewise.
+ * testsuite/gas/i386/x86-64-vgather-check-warn.d: Likewise.
+ * testsuite/gas/i386/x86-64-vgather-check-warn.e: Likewise.
+ * testsuite/gas/i386/x86-64-vgather-check.d: Likewise.
+
+2017-10-26 Hans-Peter Nilsson <hp@bitrange.com>
+
+ * testsuite/gas/all/fill-1.s: Use L2 rather than .L2.
+
+2017-10-25 Alan Modra <amodra@gmail.com>
+
+ PR 22348
+ * config/tc-crx.c (instruction, output_opcode): Make static.
+ (relocatable, ins_parse, cur_arg_num): Likewise.
+ (parse_insn): Adjust for renamed opcodes globals.
+ (check_range): Likewise
+
+2017-10-25 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/all/fill-1.d: Exclude tic4x and tic54x.
+ * testsuite/gas/all/fill-1.s: Use L1 rather than .L1.
+
+2017-10-24 Andrew Waterman <andrew@sifive.com>
+
+ * testsuite/gas/riscv/c-addi16sp-fail.d: New test.
+ * testsuite/gas/riscv/c-addi16sp-fail.l: Likewise.
+ * testsuite/gas/riscv/c-addi16sp-fail.s: Likewise.
+ * testsuite/gas/riscv/c-addi4spn-fail.d: Likewise.
+ * testsuite/gas/riscv/c-addi4spn-fail.l: Likewise.
+ * testsuite/gas/riscv/c-addi4spn-fail.s: Likewise.
+ * testsuite/gas/riscv/riscv.exp: Add new tests.
+
+2017-10-24 Andrew Waterman <andrew@sifive.com>
+
+ * testsuite/gas/riscv/c-lui-fail.d: New testcase.
+ * gas/testsuite/gas/riscv/c-lui-fail.l: Likewise.
+ * gas/testsuite/gas/riscv/c-lui-fail.s: Likewise.
+ * gas/testsuite/gas/riscv/riscv.exp: Likewise.
+
+2017-10-24 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (md_pseudo_table): Add .code64 directive
+ only if BFD64 is defined.
+ * testsuite/gas/i386/code64-inval.l: New file.
+ * gas/testsuite/gas/i386/code64-inval.s: Likewise.
+ * gas/testsuite/gas/i386/code64.d: Likewise.
+ * gas/testsuite/gas/i386/code64.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Run mixed-mode-reloc32,
+ att-regs, intel-regs, intel-expr and string-ok tests only if
+ assembler supports x86-64. Run code64 and code64-inval.
+
2017-10-23 Palmer Dabbelt <palmer@dabbelt.com>
- * config/tc-riscv.c (riscv_frag_align_code): Align code by 4
- bytes on non-RVC systems.
+ * config/tc-riscv.c (riscv_frag_align_code): Align code by 4
+ bytes on non-RVC systems.
2017-10-23 Maciej W. Rozycki <macro@imgtec.com>