+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (insns): Add DCPS instruction.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (T16_32_TAB): Add _sevl.
+ (insns): Add SEVL.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (asm_barrier_opt): Add arch field.
+ (mark_feature_used): New function.
+ (parse_barrier): Check specified option is valid for the
+ specified architecture.
+ (UL_BARRIER): New macro.
+ (barrier_opt_names): Update for new barrier options.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (do_setend): Warn on deprecated SETEND.
+ (do_t_setend): Likewise.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (do_t_it): Fully initialise now_it.
+ (new_automatic_it_block): Likewise.
+ (handle_it_block): Record whether current instruction is
+ conditionally executed.
+ * config/tc-arm.c (depr_insn_mask): New structure.
+ (depr_it_insns): New variable.
+ (it_fsm_post_encode): Warn on deprecated uses.
+ * config/tc-arm.h (current_it): Add new fields.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (deprecated_coproc_regs_s): New structure.
+ (deprecated_coproc_regs): New variable.
+ (deprecated_coproc_reg_count): Likewise.
+ (do_co_reg): Error on obsolete & warn on deprecated registers.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (check_obsolete): New function.
+ (do_rd_rm_rn): Check swp{b} for obsoletion.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.h (arm_ext_v8): New variable.
+ (fpu_vfp_ext_armv8): Likewise.
+ (fpu_neon_ext_armv8): Likewise.
+ (fpu_crypto_ext_armv8): Likewise.
+ (arm_archs): Add armv8-a.
+ (arm_extensions): Add crypto, fp, and simd.
+ (arm_fpus): Add fp-armv8, neon-fp-armv8, crypto-neon-fp-armv8.
+ (cpu_arch_ver): Add support for ARMv8.
+ (aeabi_set_public_sttributes): Likewise.
+ * doc/c-arm.texi (ARM Options): Document new architecture and
+ extension options for ARMv8.
+
+2012-08-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ * doc/as.texinfo: Replace --n32 with --x32.
+
+2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
+
+ * config/tc-i386.c (cpu_arch): Add CPU_BTVER1_FLAGS and
+ CPU_BTVER2_FLAGS.
+ (i386_align_code): Add case for PROCESSOR_BT.
+
+ * config/tc-i386.h (enum processor_type): Add PROCESSOR_BT.
+
+ * doc/c-i386.texi: Add -march={btver1, btver2} options.
+
+2012-08-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/14457
+ * config/tc-i386.c (i386_att_operand): Terminate register name
+ when reporting bad register.
+
+2012-08-14 Hans-Peter Nilsson <hp@bitrange.com>
+
+ * config/tc-mmix.c (loc_asserts): New variable.
+ (mmix_greg_internal): Handle expressions not determinable at first
+ pass.
+ (s_loc): Ditto. Record expressions where the section isn't
+ determinable at the first pass, and assume they don't refer to
+ other sections.
+ (mmix_md_end): Verify that recorded LOC expressions weren't
+ to other sections, else emit error messages.
+
+2012-08-13 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * Makefile.am: Add AArch64.
+ * Makefile.in: Regenerate.
+ * config/tc-aarch64.c: New file.
+ * config/tc-aarch64.h: New file.
+ * configure.tgt: Add AArch64.
+ * doc/Makefile.am: Add AArch64.
+ * doc/Makefile.in: Regenerate.
+ * doc/all.texi: Add AArch64.
+ * doc/as.texinfo: Add AArch64.
+ * doc/c-aarch64.texi: New file.
+ * po/POTFILES.in: Regenerate.
+ * NEWS: Mention the new support.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (NO_ISA_COP, COP_INSN): Remove macros.
+ (is_opcode_valid): Remove coprocessor instruction exclusions.
+ Replace OPCODE_IS_MEMBER with opcode_is_member.
+ (is_opcode_valid_16): Replace OPCODE_IS_MEMBER with
+ opcode_is_member.
+ (macro): Remove coprocessor instruction exclusions.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (s_cpload, s_cpsetup): Fail if MIPS16 mode.
+ (s_cplocal, s_cprestore, s_cpreturn): Likewise.
+
+2012-08-07 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386-intel.c (build_modrm_byte): Split determining
+ default segment from figuring out encoding. Honor RegRex for
+ the former.
+
+2012-08-07 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (set_check): Renamed from set_sse_check.
+ Generalize to also handle operand checking option.
+ (enum i386_error): New enumerator 'invalid_vector_register_set'.
+ (match_template): Handle it.
+ (enum check_kind): Give it a tag. Drop sse_ prefixes from
+ enumerators.
+ (operand_check): New.
+ (md_pseudo_table): Add "operand_check".
+ (check_VecOperands): Don't special case RIP addressing. Check
+ that vSIB operands use distinct vector registers unless no
+ checking was requested.
+ (OPTION_MOPERAND_CHECK): New.
+ (md_parse_option): Handle it.
+ (OPTION_MAVXSCALAR, OPTION_X32): Adjust.
+ (md_longopts): Add "moperand-check".
+ (md_show_usage): Add help text for it.
+
+2012-08-07 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (register_number): New function.
+ (build_vex_prefix, process_immext, process_operands,
+ build_modrm_byte, i386_index_check): Use it.
+
2012-08-07 Daniel Green <venix1@gmail.com>
* config/tc-i386.c (lex_got): Provide implementation for PE