+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (insns): Add DCPS instruction.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (T16_32_TAB): Add _sevl.
+ (insns): Add SEVL.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (asm_barrier_opt): Add arch field.
+ (mark_feature_used): New function.
+ (parse_barrier): Check specified option is valid for the
+ specified architecture.
+ (UL_BARRIER): New macro.
+ (barrier_opt_names): Update for new barrier options.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (do_setend): Warn on deprecated SETEND.
+ (do_t_setend): Likewise.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (do_t_it): Fully initialise now_it.
+ (new_automatic_it_block): Likewise.
+ (handle_it_block): Record whether current instruction is
+ conditionally executed.
+ * config/tc-arm.c (depr_insn_mask): New structure.
+ (depr_it_insns): New variable.
+ (it_fsm_post_encode): Warn on deprecated uses.
+ * config/tc-arm.h (current_it): Add new fields.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (deprecated_coproc_regs_s): New structure.
+ (deprecated_coproc_regs): New variable.
+ (deprecated_coproc_reg_count): Likewise.
+ (do_co_reg): Error on obsolete & warn on deprecated registers.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (check_obsolete): New function.
+ (do_rd_rm_rn): Check swp{b} for obsoletion.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.h (arm_ext_v8): New variable.
+ (fpu_vfp_ext_armv8): Likewise.
+ (fpu_neon_ext_armv8): Likewise.
+ (fpu_crypto_ext_armv8): Likewise.
+ (arm_archs): Add armv8-a.
+ (arm_extensions): Add crypto, fp, and simd.
+ (arm_fpus): Add fp-armv8, neon-fp-armv8, crypto-neon-fp-armv8.
+ (cpu_arch_ver): Add support for ARMv8.
+ (aeabi_set_public_sttributes): Likewise.
+ * doc/c-arm.texi (ARM Options): Document new architecture and
+ extension options for ARMv8.
+
+2012-08-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ * doc/as.texinfo: Replace --n32 with --x32.
+
+2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
+
+ * config/tc-i386.c (cpu_arch): Add CPU_BTVER1_FLAGS and
+ CPU_BTVER2_FLAGS.
+ (i386_align_code): Add case for PROCESSOR_BT.
+
+ * config/tc-i386.h (enum processor_type): Add PROCESSOR_BT.
+
+ * doc/c-i386.texi: Add -march={btver1, btver2} options.
+
+2012-08-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/14457
+ * config/tc-i386.c (i386_att_operand): Terminate register name
+ when reporting bad register.
+
+2012-08-14 Hans-Peter Nilsson <hp@bitrange.com>
+
+ * config/tc-mmix.c (loc_asserts): New variable.
+ (mmix_greg_internal): Handle expressions not determinable at first
+ pass.
+ (s_loc): Ditto. Record expressions where the section isn't
+ determinable at the first pass, and assume they don't refer to
+ other sections.
+ (mmix_md_end): Verify that recorded LOC expressions weren't
+ to other sections, else emit error messages.
+
+2012-08-13 Ian Bolton <ian.bolton@arm.com>
+ Laurent Desnogues <laurent.desnogues@arm.com>
+ Jim MacArthur <jim.macarthur@arm.com>
+ Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Nigel Stephens <nigel.stephens@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ Richard Earnshaw <rearnsha@arm.com>
+ Sofiane Naci <sofiane.naci@arm.com>
+ Tejas Belagod <tejas.belagod@arm.com>
+ Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * Makefile.am: Add AArch64.
+ * Makefile.in: Regenerate.
+ * config/tc-aarch64.c: New file.
+ * config/tc-aarch64.h: New file.
+ * configure.tgt: Add AArch64.
+ * doc/Makefile.am: Add AArch64.
+ * doc/Makefile.in: Regenerate.
+ * doc/all.texi: Add AArch64.
+ * doc/as.texinfo: Add AArch64.
+ * doc/c-aarch64.texi: New file.
+ * po/POTFILES.in: Regenerate.
+ * NEWS: Mention the new support.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (NO_ISA_COP, COP_INSN): Remove macros.
+ (is_opcode_valid): Remove coprocessor instruction exclusions.
+ Replace OPCODE_IS_MEMBER with opcode_is_member.
+ (is_opcode_valid_16): Replace OPCODE_IS_MEMBER with
+ opcode_is_member.
+ (macro): Remove coprocessor instruction exclusions.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (s_cpload, s_cpsetup): Fail if MIPS16 mode.
+ (s_cplocal, s_cprestore, s_cpreturn): Likewise.
+
+2012-08-07 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386-intel.c (build_modrm_byte): Split determining
+ default segment from figuring out encoding. Honor RegRex for
+ the former.
+
+2012-08-07 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (set_check): Renamed from set_sse_check.
+ Generalize to also handle operand checking option.
+ (enum i386_error): New enumerator 'invalid_vector_register_set'.
+ (match_template): Handle it.
+ (enum check_kind): Give it a tag. Drop sse_ prefixes from
+ enumerators.
+ (operand_check): New.
+ (md_pseudo_table): Add "operand_check".
+ (check_VecOperands): Don't special case RIP addressing. Check
+ that vSIB operands use distinct vector registers unless no
+ checking was requested.
+ (OPTION_MOPERAND_CHECK): New.
+ (md_parse_option): Handle it.
+ (OPTION_MAVXSCALAR, OPTION_X32): Adjust.
+ (md_longopts): Add "moperand-check".
+ (md_show_usage): Add help text for it.
+
+2012-08-07 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (register_number): New function.
+ (build_vex_prefix, process_immext, process_operands,
+ build_modrm_byte, i386_index_check): Use it.
+
+2012-08-07 Daniel Green <venix1@gmail.com>
+
+ * config/tc-i386.c (lex_got): Provide implementation for PE
+ format.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (append_insn): Also handle moving delay-slot
+ instruction across frags for fixed branches.
+
+2012-08-03 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * frags.c (frag_grow): Never shrink the obstack size requested
+ below the default.
+
+2012-08-02 Sean Keys <skeys@ipdatasys.com>
+
+ * config/tc-m68hc11.c (s_m68hc11_parse_pseudo_instruction):
+ New function to parse pseudo ops that are unreleated to
+ existing pseudo ops.
+
+2012-08-01 Catherine Moore <clm@codesourcery.com>
+ Sandra Loosemore <sandra@codesourcery.com>
+
+ * config/mips/tc-mips.c (mips_cpu_info): Add the 34kn.
+ * doc/c-mips.texi (MIPS Opts): Document it.
+
+2012-08-01 James Lemke <jwlemke@codesourcery.com>
+
+ * dwarf2dbg.c (out_set_addr): Allow for non-constant value of
+ DWARF2_LINE_MIN_INSN_LENGTH
+ * config/tc-ppc.c (ppc_dwarf2_line_min_insn_length): Declare
+ and initialize.
+ (md_apply_fix): Branch addr can be a multiple of 2 or 4.
+ * config/tc-ppc.h (DWARF2_LINE_MIN_INSN_LENGTH): Now a
+ variable reference.
+
+2012-07-31 Maciej W. Rozycki <macro@codesourcery.com>
+ Chao-Ying Fu <fu@mips.com>
+ Catherine Moore <clm@codesourcery.com>
+
+ * config/tc-mips.c (ISA_SUPPORTS_DSP_ASE): Also set if microMIPS
+ mode.
+ (ISA_SUPPORTS_DSPR2_ASE): Likewise.
+ (macro_build) <'2'>: Handle microMIPS.
+ (macro) <M_BALIGN>: Update error handling.
+ (validate_micromips_insn) <'2', '3', '4', '5', '6'>: New cases.
+ <'7', '8', '0', '@', '^'>: Likewise.
+ (mips_ip) <'2', '3', '4', '5', '6', '7', '8'>: Handle microMIPS.
+ <'9'>: Fix formatting.
+ <'0', '@'>: Handle microMIPS.
+ <'^'>: New case.
+
+2012-07-31 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (match_template): Adjust error message
+ for 'bad_imm4' case.
+
+2012-07-31 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (check_byte_reg): Check for I/O port
+ register earlier, and just once. Drop diagnostic that got
+ issued only for some registers.
+
+2012-07-31 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (match_template): New local variable
+ 'specific_error'. Set it from i.error after failed
+ check_VecOperands or VEX_check_operands. Use it if set in
+ preference to i.error when actually issuing disagnostic.
+
+2012-07-30 Nick Clifton <nickc@redhat.com>
+
+ * po/gas.pot: Updated template.
+ * po/es.po: Updated Spanish translation.
+ * po/fi.po: Updated Finnish translation.
+ * po/fr.po: Updated French translation.
+
+2012-07-27 Mike Frysinger <vapier@gentoo.org>
+
+ * configure.in (BFD_VERSION): Run bfd/configure --version and
+ parse the output of that.
+ * configure: Regenerate.
+
+2012-07-27 Tristan Gingold <gingold@adacore.com>
+
+ * NEWS: Add marker for 2.23.
+
+2012-07-27 James Murray <jsm@jsm-net.demon.co.uk>
+
+ * config/tc-m68hc11.c: Replace binary with hex for cygwin.
+
2012-07-26 Segher Boessenkool <segher@kernel.crashing.org>
* listing.c (struct list_message): New.
* config/tc-i386.c: Add ADX, RDSEED and PRFCHW asm directives.
* doc/c-i386.texi: Document the new directives.
+2012-07-05 Sean Keys <skeys@ipdatasys.com>
+
+ * config/tc-xgate.c: Revised assembler so that operands
+ are collected before the addressing mode is determined.
+
2012-07-02 Nick Clifton <nickc@redhat.com>
* write.c (fixup_segment): Only perform the subtraction of an
by pre-biasing add_number.
* config/tc-h8300.h (DWARF2_USE_FIXED_ADVANCE_PC): Define to 0.
+2012-06-28 Sean Keys <skeys@ipdatasys.com>
+
+ * config/tc-xgate.h: Defined tc_frob_symbol.
+ * config/tc-xgate.c (xgate_frob_symbol): Wrote new function to mark
+ symbols as being XGATE by setting st_target_internal value.
+
2012-06-22 Roland McGrath <mcgrathr@google.com>
* NEWS: Mention 'rep ret' too.
* input-file.c (input_file_get): Use ferror.
(input_file_give_next_buffer): Use input_file_get.
+2012-05-31 Sean Keys <skeys@ipdatasys.com>
+
+ * config/tc-xgate.c (md_begin): Refactored code.
+
2012-05-29 Roland McGrath <mcgrathr@google.com>
* read.c [HANDLE_BUNDLE] (bundle_lock_depth): New variable.
Use nacl format variants.
2012-04-12 Jie Zhang <jie@codesourcery.com>
- Meador Inge <meadori@codesourcery.com>
+ Meador Inge <meadori@codesourcery.com>
* config/tc-arm.c (only_one_reg_in_list): New function.
(encode_ldmstm): Ditto.
projects / deliverable / binutils-gdb.git / blobdiff