[AArch64][SVE 20/32] Add support for tied operands

[deliverable/binutils-gdb.git] / gas / ChangeLog

diff --git a/gas/ChangeLog b/gas/ChangeLog
index c9e30a1584ddafa2fea062373148be913dd8517a..425c37a7dde8905f69f299d2e4314a26181a4c5a 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,103 @@
+2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/tc-aarch64.c (output_operand_error_record): Handle
+       AARCH64_OPDE_UNTIED_OPERAND.
+
+2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/tc-aarch64.c (find_best_match): Simplify, allowing an
+       instruction with all-NIL qualifiers to fail to match.
+
+2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/tc-aarch64.c (parse_address_main): Remove reloc and
+       accept_reg_post_index parameters.  Parse relocations and register
+       post indexes unconditionally.
+       (parse_address): Remove accept_reg_post_index parameter.
+       Update call to parse_address_main.
+       (parse_address_reloc): Delete.
+       (parse_operands): Call parse_address instead of parse_address_main.
+       Update existing callers of parse_address and make them check
+       inst.reloc.type where appropriate.
+       * testsuite/gas/aarch64/diagnostic.s: Add tests for relocations
+       in ADDR_SIMPLE, SIMD_ADDR_SIMPLE, ADDR_SIMM7 and ADDR_SIMM9 addresses.
+       Also test for invalid uses of post-index register addressing.
+       * testsuite/gas/aarch64/diagnostic.l: Update accordingly.
+
+2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/tc-aarch64.c (REG_TYPE_R_Z, REG_TYPE_R_SP): New register
+       types.
+       (get_reg_expected_msg): Handle them and REG_TYPE_R64_SP.
+       (aarch64_check_reg_type): Simplify.
+       (aarch64_reg_parse_32_64): Return the reg_entry instead of the
+       register number.  Return the type as a qualifier rather than an
+       "isreg32" boolean.  Remove reject_sp, reject_rz and isregzero
+       parameters.
+       (parse_shifter_operand): Update call to aarch64_parse_32_64_reg.
+       Use get_reg_expected_msg.
+       (parse_address_main): Likewise.  Use aarch64_check_reg_type.
+       (po_int_reg_or_fail): Replace reject_sp and reject_rz parameters
+       with a reg_type parameter.  Update call to aarch64_parse_32_64_reg.
+       Use aarch64_check_reg_type to test the result.
+       (parse_operands): Update after the above changes.  Parse ADDR_SIMPLE
+       addresses normally before enforcing the syntax restrictions.
+       * testsuite/gas/aarch64/diagnostic.s: Add tests for a post-index
+       zero register and for a stack pointer index.
+       * testsuite/gas/aarch64/diagnostic.l: Update accordingly.
+       Also update existing diagnostic messages after the above changes.
+       * testsuite/gas/aarch64/illegal-lse.l: Update the error message
+       for 32-bit register bases.
+
+2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/tc-aarch64.c (parse_aarch64_imm_float): Remove range check.
+       (parse_operands): Check the range of 8-bit FP immediates here instead.
+
+2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/tc-aarch64.c (parse_aarch64_imm_float): Report a specific
+       low-severity error for registers.
+       (parse_operands): Report an invalid floating point constant for
+       if parsing an FPIMM8 fails, and if no better error has been
+       recorded.
+       * testsuite/gas/aarch64/diagnostic.s,
+       testsuite/gas/aarch64/diagnostic.l: Add tests for integer operands
+       to FMOV.
+
+2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/tc-aarch64.c (aarch64_double_precision_fmovable): Rename
+       to...
+       (can_convert_double_to_float): ...this.  Accept any double-precision
+       value that converts to single precision without loss of precision.
+       (parse_aarch64_imm_float): Update accordingly.
+
+2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/tc-aarch64.c (parse_immediate_expression): Add a
+       reg_type parameter.
+       (parse_constant_immediate): Likewise, and update calls.
+       (parse_aarch64_imm_float): Likewise.
+       (parse_big_immediate): Likewise.
+       (po_imm_nc_or_fail): Update accordingly, passing down a new
+       imm_reg_type variable.
+       (po_imm_of_fail): Likewise.
+       (parse_operands): Likewise.
+
+2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/tc-aarch64.c (parse_neon_reg_list): Rename to...
+       (parse_vector_reg_list): ...this and take a register type
+       as input.
+       (parse_operands): Update accordingly.
+
+2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/tc-aarch64.c (parse_neon_type_for_operand): Rename to...
+       (parse_vector_type_for_operand): ...this.
+       (parse_typed_reg): Update accordingly.
+
 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 
        * config/tc-aarch64.c (neon_type_el): Rename to...