[binutils][arm] BFloat16 enablement [4/X]
[deliverable/binutils-gdb.git] / gas / ChangeLog
index ac2e3d75aa211023119687eb5421b5f26ed26c2a..57ee5cd1795316c1beda2c03e166b966feeb4649 100644 (file)
@@ -1,3 +1,178 @@
+2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
+2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * config/tc-arm.c (arm_archs): Add armv8.6-a option.
+       (cpu_arch_ver): Add TAG_CPU_ARCH_V8 tag for Armv8.6-a.
+       * doc/c-arm.texi (-march): New armv8.6-a arch.
+       * config/tc-arm.c (arm_ext_bf16): New feature set.
+       (enum neon_el_type): Add NT_bfloat value.
+       (B_MNEM_vfmat, B_MNEM_vfmab): New bfloat16 encoder
+       helpers.
+       (BAD_BF16): New message.
+       (parse_neon_type): Add bf16 type specifier.
+       (enum neon_type_mask): Add N_BF16 type.
+       (type_chk_of_el_type): Account for NT_bfloat.
+       (el_type_of_type_chk): Account for N_BF16.
+       (neon_three_args): Split out from neon_three_same.
+       (neon_three_same): Part split out into neon_three_args.
+       (CVT_FLAVOUR_VAR): Add bf16_f32 cvt flavour.
+       (do_neon_cvt_1): Account for vcvt.bf16.f32.
+       (do_bfloat_vmla): New.
+       (do_mve_vfma): New function to deal with the mnemonic clash between the BF16
+       vfmat and the MVE vfma in a VPT block with a 't'rue condition.
+       (do_neon_cvttb_1): Account for vcvt{t,b}.bf16.f32.
+       (do_vdot): New
+       (do_vmmla): New
+       (insns): Add vdot and vmmla mnemonics.
+       (arm_extensions): Add "bf16" extension.
+       * doc/c-arm.texi: Document "bf16" extension.
+       * testsuite/gas/arm/attr-march-armv8_6-a.d: New test.
+       * testsuite/gas/arm/bfloat16-bad.d: New test.
+       * testsuite/gas/arm/bfloat16-bad.l: New test.
+       * testsuite/gas/arm/bfloat16-bad.s: New test.
+       * testsuite/gas/arm/bfloat16-cmdline-bad-2.d: New test.
+       * testsuite/gas/arm/bfloat16-cmdline-bad-3.d: New test.
+       * testsuite/gas/arm/bfloat16-cmdline-bad.d: New test.
+       * testsuite/gas/arm/bfloat16-neon.s: New test.
+       * testsuite/gas/arm/bfloat16-non-neon.s: New test.
+       * testsuite/gas/arm/bfloat16-thumb-bad.d: New test.
+       * testsuite/gas/arm/bfloat16-thumb-bad.l: New test.
+       * testsuite/gas/arm/bfloat16-thumb.d: New test.
+       * testsuite/gas/arm/bfloat16-vfp.d: New test.
+       * testsuite/gas/arm/bfloat16.d: New test.
+       * testsuite/gas/arm/bfloat16.s: New test.
+
+2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
+2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * config/tc-aarch64.c (vectype_to_qualifier): Special case the
+       S_2H operand qualifier.
+       * doc/c-aarch64.texi: Document bf16 extension.
+       * testsuite/gas/aarch64/bfloat16.d: New test.
+       * testsuite/gas/aarch64/bfloat16.s: New test.
+       * testsuite/gas/aarch64/illegal-bfloat16.d: New test.
+       * testsuite/gas/aarch64/illegal-bfloat16.l: New test.
+       * testsuite/gas/aarch64/illegal-bfloat16.s: New test.
+       * testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test.
+       * testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test.
+
+2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
+2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * config/tc-aarch64.c (armv8.6-a): New arch.
+       * doc/c-aarch64.texi (armv8.6-a): Document new arch.
+
+2019-11-07  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (cpu_arch): Add .rdpru and .mcommit entries.
+       * doc/c-i386.texi: Mention rdpru and mcommit.
+       * testsuite/gas/i386/arch-13.s,
+       testsuite/gas/i386/x86-64-arch-3.s: Add mcommit and rdpru cases.
+       * testsuite/gas/i386/arch-13.d,
+       testsuite/gas/i386/x86-64-arch-3.d: Extend -march=. Adjust
+       expectations.
+       * testsuite/gas/i386/arch-13-znver1.d: Extend -march=. Redirect
+       expectations to arch-13.d.
+       * testsuite/gas/i386/arch-13-znver2.d: Redirect expectations to
+       arch-13.d.
+       testsuite/gas/i386/x86-64-arch-3-znver1.d: Extend -march=.
+
+2019-11-07  Jan Beulich  <jbeulich@suse.com>
+
+       * testsuite/gas/i386/x86-64-arch-3.s: Add monitorx/mwaitx cases
+       with canonical operand sizes.
+       * testsuite/gas/i386/x86-64-sse3.s: Add monitor/mwait cases with
+       canonical operand sizes.
+       * testsuite/gas/i386/x86-64-arch-3-znver1.d,
+       testsuite/gas/i386/x86-64-arch-3-znver2.d: Redirect expectations
+       to x86-64-arch-3.d.
+       * testsuite/gas/i386/ilp32/x86-64-sse-noavx.d: Redirect
+       expectations to parent dir's x86-64-sse-noavx.d.
+       * testsuite/gas/i386/ilp32/x86-64-sse3.d: Redirect expectations
+       to to parent dir's x86-64-sse3.d.
+       * testsuite/gas/i386/x86-64-arch-3.d,
+       testsuite/gas/i386/x86-64-mwaitx-bdver4.d,
+       testsuite/gas/i386/x86-64-sse-noavx.d,
+       testsuite/gas/i386/x86-64-sse3.d,
+       testsuite/gas/i386/x86-64-suffix.d: Adjust expectations.
+
+2019-11-04  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (process_operands): Handle ShortForm insns
+       later, splitting out their segment register sub-form.
+
+2019-10-31  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * testsuite/gas/i386/general.s: Add .code16gcc fldenv tests.
+       * testsuite/gas/i386/general.l: Updated.
+
+2019-10-31  Mihail Ionescu  <mihail.ionescu@arm.com>
+
+       * config/tc-arm.c (selected_ctx_ext_table) New static variable.
+       (arm_parse_arch): Set context sensitive extension table based on the
+       chosen base architecture.
+       (s_arm_arch_extension): Change to lookup extensions in the new context
+       sensitive tables.
+       * gas/testsuite/gas/arm/mve-ext.s: New.
+       * gas/testsuite/gas/arm/mve-ext.d: New.
+       * gas/testsuite/gas/arm/mvefp-ext.s: New.
+       * gas/testsuite/gas/arm/mvefp-ext.d: New.
+
+2019-10-30  Delia Burduv  <Delia.Burduv@arm.com>
+
+       * config/tc-aarch64.c (parse_address_main): Accept the omission of
+       the immediate argument for ldraa and ldrab as a shorthand for the
+       immediate being 0.
+       * testsuite/gas/aarch64/ldraa-ldrab-no-offset.d: New test.
+       * testsuite/gas/aarch64/ldraa-ldrab-no-offset.s: New test.
+       * testsuite/gas/aarch64/illegal-ldraa.s: Modified to accept the
+       writeback form with no offset.
+       * testsuite/gas/aarch64/illegal-ldraa.s: Removed missing offset
+       error.
+
+2019-10-30  Jan Beulich  <jbeulich@suse.com>
+
+       * testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg16.s,
+       testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg32.s,
+       testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.s: New.
+       * testsuite/gas/i386/i386.exp: Run new tests.
+
+2019-10-30  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (optimize_encoding): Adjust opcodes compared
+       against. Adjust replacement opcode and clear .w.
+
+2019-10-29  Alan Modra  <amodra@gmail.com>
+
+       PR 25125
+       * dw2gencfi.c (output_cfi_insn): Don't allow DW_CFA_advance_loc4
+       to be placed in a different frag to the rs_cfa.
+
+2019-10-26  John David Anglin  <danglin@gcc.gnu.org>
+
+       PR gas/25121
+       * config/tc-hppa.c (tc_gen_reloc): Cast some enums to int.
+       (md_assemble): Likewise.
+
+2019-10-26  Alan Modra  <amodra@gmail.com>
+
+       PR 25125
+       * dw2gencfi.c (output_cfi_insn): Don't output DW_CFA_advance_loc+0.
+       * ehopt.c (eh_frame_estimate_size_before_relax): Return -1 for
+       an advance_loc of zero.
+       (eh_frame_relax_frag): Translate fr_subtype of 7 to size -1.
+       (eh_frame_convert_frag): Handle fr_subtype of 7.  Abort on
+       unexpected fr_subtype.
+
+2019-10-25  Alan Modra  <amodra@gmail.com>
+
+       PR gas/25125
+       PR gas/12049
+       * write.c (relax_frag): Correct calculation of delta for
+       positive branches where "stretch" would make the branch
+       negative.  Return zero immediately in that case.  Correct
+       TC_PCREL_ADJUST comment.
+
 2019-10-16  Alan Modra  <amodra@gmail.com>
 
        * config/tc-xtensa.c (xg_order_trampoline_chain_entry): Don't
This page took 0.038935 seconds and 4 git commands to generate.