x86: replace Reg8, Reg16, Reg32, and Reg64

[deliverable/binutils-gdb.git] / gas / ChangeLog

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 19e13d6019587e53bb7deab14fb485d263da5cf2..5953cd0c96006dff56e6be3279538b06b273b1e1 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,116 @@
+2017-12-18  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (operand_type_check, pi): Switch .reg<N> to
+       just .reg.
+       (operand_size_match): Qualify .anysize check with .reg one.
+       Extend .acc check to also cover .reg.
+       (operand_type_register_match): Drop m0 and m1 parameters. Switch
+       .reg<N> to .byte/.word/.dword/.qword. Drop .acc special
+       handling. 
+       (md_assemble): Expand .reg8 checks to .reg plus .bytes ones.
+       (optimize_imm, process_suffix, check_byte_reg, check_long_reg,
+       check_qword_reg, check_word_reg): Expand .reg<N> checks to .reg
+       plus size ones.
+       (match_template): Drop arguments from calls to
+       operand_type_register_match().
+       (build_modrm_byte, i386_addressing_mode, i386_index_check,
+       parse_real_register): Replace .reg<N> checks.
+       * config/tc-i386-intel.c (i386_intel_simplify,
+       i386_intel_operand): Switch .reg16 to .word.
+
+2017-12-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/22623
+       * gas/config/tc-i386.c (output_insn): Check pseudo prefix
+       without instruction.
+       * testsuite/gas/i386/i386.exp: Run inval-pseudo.
+       * testsuite/gas/i386/inval-pseudo.l: New file.
+       * testsuite/gas/i386/inval-pseudo.s: Likewise.
+
+2017-12-15  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (match_template): Add missing ! to
+       reg{x,y,z}mm checks in q- and l-suffix handling.
+
+2017-12-15  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (build_modrm_byte): Add missing ! to reg64
+       check leading to abort().
+
+2017-12-14  Nick Clifton  <nickc@redhat.com>
+
+       * config/tc-m32c.c: Update address of FSF in copyright notice.
+       * config/tc-m32c.h: Likewise.
+       * config/tc-mt.c: Likewise.
+       * config/tc-mt.h: Likewise.
+       * config/tc-visium.c: Likewise.
+       * config/tc-visium.h: Likewise.
+       * testsuite/gas/rx/explode: Likewise.
+
+2017-12-13  Jim Wilson  <jimw@sifive.com>
+
+       PR 22599
+       * testsuite/gas/riscv/fsxxi.d, testsuite/gas/riscv/fsxxi.s: New.
+
+2017-12-13  Dimitar Dimitrov  <dimitar@dinux.eu>
+
+       * testsuite/gas/pru/extern.s: New test for print of U16_PMEMM
+       relocation.
+       * testsuite/gas/pru/extern.d: New test driver.
+
+2017-12-12  Alan Modra  <amodra@gmail.com>
+
+       PR 21118
+       * config/tc-ppc.c (md_assemble): Don't mask register number.
+
+2017-12-07  Max Filippov  <jcmvbkbc@gmail.com>
+
+       * config/tc-xtensa.c (xg_order_trampoline_chain): Replace
+       xg_order_trampoline_chain_entry call with check for
+       canonicalized symbol equality and offset equality.
+
+2017-12-04  Alan Modra  <amodra@gmail.com>
+
+       PR 22544
+       * doc/as.texinfo (8byte): Correct.
+
+2017-12-04  Alan Modra  <amodra@gmail.com>
+
+       * testsuite/gas/ppc/ppc.exp: Don't exclude VLE tests when little-endian.
+       * testsuite/gas/ppc/efs.d: Add -mbig to assembler options.
+       * testsuite/gas/ppc/efs2.d: Likewise.
+       * testsuite/gas/ppc/lsp-checks.d: Likewise.
+       * testsuite/gas/ppc/lsp.d: Likewise.
+       * testsuite/gas/ppc/spe.d: Likewise.
+       * testsuite/gas/ppc/spe2-checks.d: Likewise.
+       * testsuite/gas/ppc/spe2.d: Likewise.
+       * testsuite/gas/ppc/spe_ambiguous.d: Likewise.
+       * testsuite/gas/ppc/vle-mult-ld-st-insns.d: Likewise.
+       * testsuite/gas/ppc/vle-reloc.d: Likewise.
+       * testsuite/gas/ppc/vle-simple-1.d: Likewise.
+       * testsuite/gas/ppc/vle-simple-2.d: Likewise.
+       * testsuite/gas/ppc/vle-simple-3.d: Likewise.
+       * testsuite/gas/ppc/vle-simple-4.d: Likewise.
+       * testsuite/gas/ppc/vle-simple-5.d: Likewise.
+       * testsuite/gas/ppc/vle-simple-6.d: Likewise.
+       * testsuite/gas/ppc/vle.d: Likewise.
+
+2017-12-03  Jim Wilson  <jimw@sifive.com>
+
+       * doc/c-riscv.texi (RISC-V-Directives): Move @section immediately after
+       @node.
+
+2017-12-01  Palmer Dabbelt  <palmer@sifive.com>
+           Jim Wilson  <jimw@sifive.com>
+
+       * doc/as.texinfo (RISC-V): Alphabetize RISC-V entries.  Change
+       RISC-V-Opts to RISC-V-Options.  Delete redundant space.  Add -fpic
+       and related options to option list.
+       * doc/c-riscv.texi: (RISC-V-Options): Renamed from RISC-V-Opts.
+       (RISC-V Options): Renamed from Options.  Add missing period.
+       (-fpic): Also mention -fPIC.
+       (RISC-V Directives): New node.
+
 2017-12-01  Peter Bergner <bergner@vnet.ibm.com>
 
        * config/tc-ppc.c (last_insn): Update type.