+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
+ (mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions.
+ Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_ip): Preserve the real bit number for "+p".
+ Require the msb to be <= 31 for "+s". Check that the size is <= 31
+ for both "+s" and "+S".
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn):
+ (mips_ip, mips16_ip): Handle "+i".
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete.
+ (micromips_to_32_reg_h_map): Rename to...
+ (micromips_to_32_reg_h_map1): ...this.
+ (micromips_to_32_reg_i_map): Rename to...
+ (micromips_to_32_reg_h_map2): ...this.
+ (mips_lookup_reg_pair): New function.
+ (gpr_write_mask, macro): Adjust after above renaming.
+ (validate_micromips_insn): Remove "mi" handling.
+ (mips_ip): Likewise. Parse both registers in a pair for "mh".
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
+ (mips_ip): Remove "+D" and "+T" handling.
+
+2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * config/tc-s390.c (md_gather_operands, md_apply_fix): Support new
+ relocs.
+
+2013-07-03 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): Merge got_prel19 into got.
+
+2013-07-02 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * config/tc-aarch64.c (md_apply_fix): Reorder case values.
+ (aarch64_force_relocation): Likewise.
+
+2013-07-02 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (ppc_elf_adjust_symtab): Don't make .TOC. weak.
+
+2013-06-26 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * doc/as.texinfo (Overview): Remove @samp from MIPS ISA names.
+ * doc/c-mips.texi (MIPS Options): Remove @sc from MIPS ISA names.
+ Replace @sc{mips16} with literal `MIPS16'.
+ (MIPS ISA): Replace @sc{mips3} with literal `MIPS III'.
+
+2013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): Replace
+ BFD_RELOC_AARCH64_LD64_GOT_LO12_NC with
+ BFD_RELOC_AARCH64_LD_GOT_LO12_NC; likewise to
+ BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC and
+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC.
+ (md_apply_fix): Handle BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
+ BFD_RELOC_AARCH64_LD32_GOT_LO12_NC,
+ BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
+ BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC,
+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC and
+ BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC.
+ (aarch64_force_relocation): Likewise.
+
+2013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * config/tc-aarch64.c (ilp32_p): New static variable.
+ (elf64_aarch64_target_format): Return the target according to the
+ value of 'ilp32_p'.
+ (md_begin): Determine 'mach' according to the value of 'ilp32_p'.
+ (aarch64_opts): Add support for options '-milp32' and '-mlp64'.
+ (aarch64_dwarf2_addr_size): New function.
+ * config/tc-aarch64.h (aarch64_dwarf2_addr_size): New declaration.
+ (DWARF2_ADDR_SIZE): New define.
+
+2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/c-mips.texi: Use ISA instead of @sc{isa}.
+
+2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
+
+2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (mips_set_options): Add insn32 member.
+ (mips_opts): Initialize it.
+ (NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode.
+ (options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values.
+ (md_longopts): Add "minsn32" and "mno-insn32" options.
+ (is_size_valid): Handle insn32 mode.
+ (md_assemble): Pass instruction string down to macro.
+ (brk_fmt): Add second dimension and insn32 mode initializers.
+ (mfhl_fmt): Likewise.
+ (BRK_FMT, MFHL_FMT): Handle insn32 mode.
+ (macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding.
+ (macro_build_jalr, move_register): Handle insn32 mode.
+ (macro_build_branch_rs): Likewise.
+ (macro): Handle insn32 mode.
+ <M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases.
+ (mips_ip): Handle insn32 mode.
+ (md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32.
+ (s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops.
+ (mips_handle_align): Handle insn32 mode.
+ (md_show_usage): Add -minsn32 and -mno-insn32.
+
+ * doc/as.texinfo (Target MIPS options): Add -minsn32 and
+ -mno-insn32 options.
+ (-minsn32, -mno-insn32): New options.
+ * doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32
+ options.
+ (MIPS assembly options): New node. Document .set insn32 and
+ .set noinsn32.
+ (MIPS-Dependent): List the new node.
+
+2013-06-25 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-msp430.c (msp430_srcoperand): Do not allow the use of
+ the PC in indirect addressing on 430xv2 parts.
+ (msp430_operands): Add version test to hardware bug encoding
+ restrictions.
+
+2013-06-24 Roland McGrath <mcgrathr@google.com>
+
+ * config/tc-arm.c (parse_reg_list): Use skip_past_char for '}',
+ so it skips whitespace before it.
+ (s_arm_unwind_save_mmxwr, s_arm_unwind_save_mmxwcg): Likewise.
+
+ * config/tc-arm.c (arm_symbol_chars): Include '{' and '}'.
+ (arm_reg_parse_multi): Skip whitespace first.
+ (parse_reg_list): Likewise.
+ (parse_vfp_reg_list): Likewise.
+ (s_arm_unwind_save_mmxwcg): Likewise.
+
+2013-06-24 Nick Clifton <nickc@redhat.com>
+
+ PR gas/15623
+ * config/tc-arm.c (do_t_smc): Mark as ending an IT block.
+
+2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments.
+
+2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c: Assert that offsetT and valueT are at least
+ 8 bytes in size.
+ (GPR_SMIN, GPR_SMAX): New macros.
+ (macro, mips_ip): Remove code for 4-byte valueT and offsetT.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c: Remove OBJ_ELF, OBJ_MAYBE_ELF and IS_ELF
+ conditions. Remove any code deselected by them.
+ (s_mips_frame, s_mips_mask): Handle ECOFF_DEBUGGING case first.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * NEWS: Note removal of ECOFF support.
+ * doc/as.texinfo (--emulation): Update for the removal of MIPS ECOFF.
+ * Makefile.am (TARG_ENV_HFILES): Remove config/te-lnews.h.
+ (MULTI_CFILES): Remove config/e-mipsecoff.c.
+ * Makefile.in: Regenerate.
+ * configure.in: Remove MIPS ECOFF references.
+ (mips-sony-bsd*, mips-*-bsd*, mips-*-lnews*-ecoff, mips-*-*-ecoff):
+ Delete cases.
+ (mips-*-irix5*-*, mips*-*-linux*-*, mips*-*-freebsd*)
+ (mips*-*-kfreebsd*-gnu, mips-*-*-elf): Fold into...
+ (mips-*-*): ...this single case.
+ (mipsbecoff, mipslecoff, mipsecoff): Remove emulations. Expect
+ MIPS emulations to be e-mipself*.
+ * configure: Regenerate.
+ * configure.tgt (mips-sony-bsd*, mips-*-ultrix*, mips-*-osf*)
+ (mips-*-ecoff*, mips-*-pe*, mips-*-irix*, ips-*-lnews*, mips-*-riscos*)
+ (mips-*-sysv*): Remove coff and ecoff cases.
+ * as.c (mipsbecoff, mipslecoff, mipsecoff): Remove.
+ * ecoff.c: Remove reference to MIPS ECOFF.
+ * config/e-mipsecoff.c, config/te-lnews.h: Delete files.
+ * config/tc-mips.c (ECOFF_LITTLE_FORMAT): Delete.
+ (RDATA_SECTION_NAME, mips_target_form): Remove COFF and ECOFF cases.
+ (mips_hi_fixup): Tweak comment.
+ (append_insn): Require a howto.
+ (mips_after_parse_args): Remove OBJ_MAYBE_ECOFF code.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/as.texinfo: Use MIPS rather than @sc{mips} throughout.
+ Use "CPU" instead of "cpu".
+ * doc/c-mips.texi: Likewise.
+ (MIPS Opts): Rename to MIPS Options.
+ (MIPS option stack): Rename to MIPS Option Stack.
+ (MIPS ASE instruction generation overrides): Rename to
+ MIPS ASE Instruction Generation Overrides (for now).
+ (MIPS floating-point): Rename to MIPS Floating-Point.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/c-mips.texi (MIPS Macros): New section.
+ (MIPS Object): Replace with...
+ (MIPS Small Data): ...this new section.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/c-mips.texi (MIPS symbol sizes): Move section further up file.
+ Capitalize name. Use @kindex instead of @cindex for .set entries.
+
2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
* doc/c-mips.texi (MIPS Stabs): Remove section.
2013-05-28 Yufeng Zhang <yufeng.zhang@arm.com>
* config/tc-aarch64.c (reloc_table): Update to use
- BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 instead of
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 instead of
BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE.
(md_apply_fix): Likewise.
(aarch64_force_relocation): Likewise.
projects / deliverable / binutils-gdb.git / blobdiff