+Thu Oct 22 10:03:15 1998 Ron Unrau <runrau@cygnus.com>
+
+ * config/tc-mips.c : support frame and regmask/fregmask when
+ MIPS_STABS_ELF is specified.
+
+Wed Oct 21 11;34:51 1998 Catherine Moore <clm@cygnus.com>
+
+ * config/tc-sh.c (sh_fix_adjustable): Only include if OBJ_ELF.
+ (md_apply_fix): Don't return 1 for VTABLE relocs.
+ * config/tc-sh.h (obj_fix_adjustable): Define only if OBJ_ELF.
+
+Tue Oct 20 11:18:28 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * doc/c-i386.texi: Replace occurences of "opcode" with
+ "instruction mnemonic", "instruction", or "mnemonic" when
+ referring to the name of an instruction. Use "opcode" when
+ referring to the sequence of machine bytes.
+
+ * config/tc-i386.c (opcode_chars): Rename to mnemonic_chars.
+ (is_opcode_char): Rename to is_mnemonic_char.
+ (md_assemble and i386_operand): Correct error messages from
+ "opcode" to "instruction mnemonic"
+ Rename throughout opcode[] -> mnemonic[], opp -> mnem_p,
+ MAX_OPCODE_SIZE -> MAX_MNEM_SIZE,
+ DWORD_OPCODE_SUFFIX -> DWORD_MNEM_SUFFIX,
+ WORD_OPCODE_SUFFIX -> WORD_MNEM_SUFFIX,
+ BYTE_OPCODE_SUFFIX -> BYTE_MNEM_SUFFIX,
+ SHORT_OPCODE_SUFFIX -> SHORT_MNEM_SUFFIX
+ LONG_OPCODE_SUFFIX -> LONG_MNEM_SUFFIX
+
+ * config/tc-i386.h (*_MNEM_SUFFIX): Rename from *_OPCODE_SUFFIX.
+
+ * config/tc-i386.c (i386_operand): Check for garbage after
+ register name.
+
+Tue Oct 20 10:49:42 1998 Ian Lance Taylor <ian@cygnus.com>
+
+ * config/tc-i386.c (md_apply_fix3): Change handling of PCREL reloc
+ for BFD_ASSEMBLER to only change value when COFF if TE_PE.
+
+Mon Oct 19 20:20:42 1998 Catherine Moore <clm@cygnus.com>
+
+ * config/tc-sh.h (obj_fix_adjustable): Define.
+ * config/tc-sh.c (sh_force_relocation): Handle VT relocs.
+ (md_apply_fix): Likewise.
+ (tc_gen_reloc): Likewise.
+ (sh_fix_adjustable): New.
+
+Mon Oct 19 12:35:43 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * cgen.c (gas_cgen_finish_insn): Update handling of CGEN_INT_INSN_P.
+ * cgen.h (gas_cgen_finish_insn): Update prototype.
+ * config/tc-m32r.c (m32r_insn): CGEN_INT_INSN -> CGEN_INT_INSN_P.
+ cgen_insn_t -> CGEN_INSN_INT.
+ (make_parallel): Update handling of CGEN_INT_INSN_P.
+ (assemble_parallel_insn): Ditto.
+ (target_make_parallel): New function.
+ (md_assemble): Use it.
+
+Mon Oct 19 13:16:12 1998 Catherine Moore <clm@cygnus.com>
+
+ * config/tc-m32r.c (m32r_force_relocation): Fix typo.
+
+Sun Oct 18 18:48:57 1998 Jeffrey A Law (law@cygnus.com)
+
+ * config/tc-sh.c (md_assemble): Make sure the entire opcode is
+ converted into lower case.
+
+Fri Oct 16 13:36:34 CDT Catherine Moore <clm@cygnus.com>
+
+ * cgen.c (gas_cgen_md_apply_fix3): Handle VTABLE relocs.
+ (gas_cgen_tc_gen_reloc): Likewise.
+ * config/tc-m32r.h (obj_fix_adjustable): Define.
+ * config/tc-m32r.c (m32r_fix_adjustable): New.
+ (m32r_force_relocation): Handle VTABLE relocs.
+
+Wed Oct 14 11:33:38 1998 Nick Clifton <nickc@cygnus.com>
+
+ * doc/c-arm.texi (ARM Directives): Document .ltorn directive.
+
+Mon Oct 12 11:07:21 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-m32r.c (assemble_parallel_insn): Convert second opcode
+ to lower case before parsing.
+
+ * config/tc-d30v.c (parallel_ok): Ignore conflicts when explicitly
+ parallel insns modift buts in the PSW as a side effect.
+
+Thu Oct 8 10:18:33 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-d30v.c (find_format): Test for missing flag and
+ control registers.
+
+ (md_apply_fix3): Fix error messages to avoid
+ assumption about presence of a symbol.
+
+ (parallel_ok): Disallow parallel instructions that both modify the
+ same flag register.
+
+ (find_format): Generate a warning if an odd numbered register is
+ used as the first register in a mutli-register instruction.
+
+Wed Oct 7 14:09:14 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-d30v.c (md_apply_fix3): Do not assume that bad
+ relocations are always associated with a symbol.
+
+Tue Oct 6 09:31:15 1998 Catherine Moore <clm@cygnus.com>
+
+ * tc-sparc.h (TC_FORCE_RELOCATION): Define.
+ (elf32_sparc_force_relocation): Declare.
+ * tc-sparc.c (md_apply_fix3): Handle vtable relocs.
+ (tc_gen_reloc): Handle vtable relocs.
+ (elf32_sparc_force_relocation): New.
+
+Mon Oct 5 09:25:32 1998 Catherine Moore <clm@cygnsu.com>
+
+ * symbols.c (S_IS_FUNCTION): New.
+ * config/tc-v850.h (obj_fix_adjustable): Define.
+ (TC_FORCE_RELOCATION): Define.
+ (v850_force_relocation): Declare.
+ * config/tc-v850.c (tc_gen_reloc): Use offset instead
+ of fx_addnumber for VTABLE reloc addends.
+ (md_apply_fix3): Handle VTABLE relocs.
+ (v850_fix_adjustable): New.
+ (v850_force_relocation): New.
+
+Mon Oct 5 00:48:52 1998 Jeffrey A Law (law@cygnus.com)
+
+ * tc-hppa.c (fp_operand_format): Add some additional formats.
+ (pa_ip): Do not automatically promote into pa2.0 mode.
+ (pa_level): Handle ".level 2.0".
+start-sanitize-cygnus
+ (struct pa_it): New field "trunc".
+ (pa_parse_fp_cnv_format): New function.
+ (pa_parse_ftest_gfx_completer): New function.
+ (pa_ip): Handle various new letters for PA2.0 support.
+end-sanitize-cygnus
+
+Sun Oct 4 20:57:43 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * config/tc-i386.c (md_assemble): Handle AMD_3DNOW_OPCODE.
+ * config/tc-i386.h (template.extension_opcode): Change to
+ unsigned int to allow full range of 8-bit opcode suffixes.
+ (None): Redefine as 0xffff.
+
+ From Jeff B Epler <jepler@usgs.gov>
+ * doc/c-i386.texi (i386-SIMD): New section.
+
+Thu Oct 1 15:37:54 1998 Richard Henderson <rth@cygnus.com>
+
+ * read.c (discard_rest_of_line): New function.
+ * read.h: Declare it.
+ * config/tc-alpha.c (s_alpha_mask, s_alpha_frame): Use it.
+
+Thu Oct 1 10:33:53 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-d10v.c (find_symbol_matching_register): New function.
+ (find_opcode): Cope with the case where a register name matches
+ a symbol name.
+
+Wed Sep 30 10:52:32 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-v850.c (md_pcrel_from): Rename to
+ v850_pcrel_from_section.
+ (v850_pcrel_from_section): Do not resolves symbols in other
+ sections.
+
+ * config/tc-v850.h (MD_PCREL_FROM_SECTION): Define.
+
+Mon Sep 28 11:01:20 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-d10v.c (find_opcode): Generate an error if a register
+ is supplied for an operand that should not be a register.
+
+Fri Sep 25 10:04:21 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-d30v.c (write_2_short): But do allow delayed branch
+ instructions to have another instruction in the right bin.
+
+Thu Sep 24 09:28:34 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-d30v.c (write_2_short): Do not allow instructions in
+ the right container if the left container holds a branch
+ instruction.
+
+Wed Sep 23 10:54:29 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-d30v.c (reg_name_search): Only warn if a name matches
+ both a register name and symbol name.
+ (find_format): Allow correct parsing of MVTSYS and MVFSYS insns.
+
+Tue Sep 22 17:49:16 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-d30v.c (write_2_short): Implement EITHER_BUT_PREFER_MU
+ execution unit class.
+
+ (reg_name_search): If a name matches a register and a symbol,
+ prefer the register.
+ (find_format): Disallow flag registers when a general purpose
+ register is required.
+ If a number is required, but a register has been given, check to
+ see if a symbol with the same name as the register exists, and if
+ so, use that symbol.
+
+Tue Sep 22 16:40:52 1998 Jim Wilson <wilson@cygnus.com>
+
+ * config/obj-elf.h (ECOFF_DEBUGGING): Add missing parens.
+
+Tue Sep 22 15:44:21 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-d30v.c (find_format): Do not accept flag registers as
+ general purpose registers.
+ (find_format): If an immediate value is expected at a given place
+ in a format, but a register name has been provided instead, check
+ to see if that register name matches the name of a predefined
+ symbol and if it does, then use the symbol instead.
+ (reg_name_search): If a register name matches a symbol name,
+ prefer the register name to the symbol name.
+
+start-sanitize-sky
+Mon Sep 21 13:08:01 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * config/tc-dvp.c (md_begin): Set st_other field of mpgloc_sym.
+ (assemble_vif,create_vuoverlay_section,s_endmpg,s_vu): Ditto.
+
+end-sanitize-sky
+Mon Sep 21 10:42:57 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-m32r.c (m32r_do_align): After inserting NOPs, reset
+ the previous insn to empty.
+
+1998-09-20 Michael Meissner <meissner@cygnus.com>
+
+ * config/tc-ppc.c (md_apply_fix3): Do not break string into two
+ pieces, forcing the use of an ANSI compiler.
+
+Sun Sep 20 00:58:12 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * config/tc-m68k.h (TC_FORCE_RELOCATION): New macro. Force vtable
+ relocs.
+ * config/tc-m68k.c (md_apply_fix_2): Do nothing for vtable relocs.
+
+start-sanitize-sky
+Tue Sep 15 17:04:43 EDT 1998 Jim Lemke <jlemke@cygnus.com>
+
+ * config/tc-dvp.c (parse_float): Strtol() will not convert
+ 0xFfffFfff properly, it returns 0x7fffFfff.
+ Changed to use strtoul() which does work properly.
+
+end-sanitize-sky
+Tue Sep 15 08:51:07 1998 Catherine Moore <clm@cygnus.com>
+
+ * config/obj-elf.c (obj_elf_vtable_inherit): Handle arm
+ assembler syntax.
+ (obj_elf_vtable_entry): Likewise.
+ * config/tc-arm.h: Define TC_FORCE_RELOCATION for OBJ_ELF.
+ * config/tc-arm.c (md_apply_fix3): Handle VTABLE relocations.
+ (tc_gen_reloc): Likewise.
+ (arm_fix_adjustable): Likewise.
+ (elf32_arm_force_relocation): New.
+ (armelf_frob_symbol): Remove coff-style symbol support.
+
+start-sanitize-sky
+Mon Sep 14 22:28:24 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * config/tc-dvp.c (parse_float): Support 0fNNN.
+ (tc_gen_reloc): Don't crash if given a pc-relative reloc for .word,
+ just signal an error.
+
+end-sanitize-sky
Wed Sep 9 11:27:16 1998 Richard Henderson <rth@cygnus.com>
* config/tc-i386.c (i386_operand): Fix typo in last patch.