* config/tc-mips.c : support frame and regmask/fregmask when

[deliverable/binutils-gdb.git] / gas / ChangeLog

diff --git a/gas/ChangeLog b/gas/ChangeLog
index e81d8d137b9c4e8e73bfd2f2d8dfcae9aa86c4c7..9091febf636a96c4b3236eb7ba0705af5210f61a 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,66 @@
+Thu Oct 22 10:03:15 1998  Ron Unrau  <runrau@cygnus.com>
+
+       * config/tc-mips.c : support frame and regmask/fregmask when
+         MIPS_STABS_ELF is specified.
+
+Wed Oct 21 11;34:51 1998  Catherine Moore  <clm@cygnus.com>
+
+        * config/tc-sh.c (sh_fix_adjustable):  Only include if OBJ_ELF.
+        (md_apply_fix):  Don't return 1 for VTABLE relocs.
+        * config/tc-sh.h (obj_fix_adjustable):  Define only if OBJ_ELF.
+
+Tue Oct 20 11:18:28 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+       * doc/c-i386.texi: Replace occurences of "opcode" with
+       "instruction mnemonic", "instruction", or "mnemonic" when
+       referring to the name of an instruction.  Use "opcode" when
+       referring to the sequence of machine bytes.
+
+       * config/tc-i386.c (opcode_chars): Rename to mnemonic_chars.
+       (is_opcode_char): Rename to is_mnemonic_char.
+       (md_assemble and i386_operand): Correct error messages from
+        "opcode" to "instruction mnemonic"
+       Rename throughout opcode[] -> mnemonic[], opp -> mnem_p,
+       MAX_OPCODE_SIZE -> MAX_MNEM_SIZE,
+       DWORD_OPCODE_SUFFIX -> DWORD_MNEM_SUFFIX,
+       WORD_OPCODE_SUFFIX -> WORD_MNEM_SUFFIX,
+       BYTE_OPCODE_SUFFIX -> BYTE_MNEM_SUFFIX,
+       SHORT_OPCODE_SUFFIX -> SHORT_MNEM_SUFFIX
+       LONG_OPCODE_SUFFIX -> LONG_MNEM_SUFFIX
+
+       * config/tc-i386.h (*_MNEM_SUFFIX): Rename from *_OPCODE_SUFFIX.
+
+       * config/tc-i386.c (i386_operand): Check for garbage after
+       register name.
+
+Tue Oct 20 10:49:42 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+       * config/tc-i386.c (md_apply_fix3): Change handling of PCREL reloc
+       for BFD_ASSEMBLER to only change value when COFF if TE_PE.
+
+Mon Oct 19 20:20:42 1998  Catherine Moore  <clm@cygnus.com>
+
+        * config/tc-sh.h (obj_fix_adjustable):  Define.
+        * config/tc-sh.c (sh_force_relocation):  Handle VT relocs.
+        (md_apply_fix):  Likewise.
+        (tc_gen_reloc):  Likewise.
+        (sh_fix_adjustable):  New.
+
+Mon Oct 19 12:35:43 1998  Doug Evans  <devans@seba.cygnus.com>
+
+       * cgen.c (gas_cgen_finish_insn): Update handling of CGEN_INT_INSN_P.
+       * cgen.h (gas_cgen_finish_insn): Update prototype.
+       * config/tc-m32r.c (m32r_insn): CGEN_INT_INSN -> CGEN_INT_INSN_P.
+       cgen_insn_t -> CGEN_INSN_INT.
+       (make_parallel): Update handling of CGEN_INT_INSN_P.
+       (assemble_parallel_insn): Ditto.
+       (target_make_parallel): New function.
+       (md_assemble): Use it.
+
+Mon Oct 19 13:16:12 1998  Catherine Moore  <clm@cygnus.com>
+
+        * config/tc-m32r.c (m32r_force_relocation):  Fix typo.
+
 Sun Oct 18 18:48:57 1998  Jeffrey A Law  (law@cygnus.com)
 
        * config/tc-sh.c (md_assemble): Make sure the entire opcode is