+2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (arm_ext_v6m): New variable.
+ (arm_ext_m): Add support for OS extension.
+ (arm_ext_os): New variable.
+ (do_t_swi): In v6-M ensure we have the OS extension.
+ (arm_cpus): The cortex-m1 and cortex-m0 options have the OS
+ extension by default.
+ (arm_archs): Add armv6s-m.
+ (arm_extensions): Add 'os' extension.
+ (cpu_arch_ver): Add support for v6S-M.
+ * doc/c-arm.texi: Document the OS Extension, and v6-m and v6s-m
+ architecture options.
+
+2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (arm_ext_v6z): Remove.
+ (arm_ext_sec): New variable.
+ (do_t_smc): In Thumb state SMC requires v7-A.
+ (insns): Make SMC depend on Security Extensions.
+ (arm_cpus): All -mcpu=cortex-a* options have the Security Extensions.
+ (arm_extensions): Add 'sec' extension.
+ (cpu_arch_ver): Reorder.
+ (aeabi_set_public_attributes): Emit Tag_Virtualization_use as
+ appropriate.
+ * doc/c-arm.texi: Document Security Extensions.
+
+2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (arm_ext_mp): Add.
+ (do_pld): Update comment.
+ (insns): Add support for pldw.
+ (arm_cpus): Update cortex-a5, cortex-a9, and cortex-a15 to support
+ MP extension.
+ (arm_extensions): Add 'mp' extension.
+ (aeabi_set_public_attributes): Emit correct build attribute when
+ MP extension is enabled.
+ * doc/c-arm.texi: Update for MP extensions.
+
+2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (md_pseduo_table): Add .arch_extension directive.
+ (arm_option_extension_value_table): Add.
+ (arm_extensions): Change type.
+ (arm_option_cpu_table): Rename...
+ (arm_option_fpu_table): ...to this.
+ (arm_fpus): Change type.
+ (arm_parse_extension): Enforce alphabetical order. Allow
+ extensions to be removed.
+ (arm_parse_arch): Allow extensions to be specified with -march.
+ (s_arm_arch_extension): Add.
+ (s_arm_fpu): Update for type changes.
+ * doc/c-arm.texi: Document changes to infrastructure.
+
+2010-09-23 Alan Modra <amodra@gmail.com>
+
+ * config/tc-mn10300.c (tc_gen_reloc): Replace absolute symbols
+ with the absolute section symbol.
+
+2010-09-22 Mike Frysinger <vapier@gentoo.org>
+
+ * config/bfin-parse.y: Fix typo in BYTEOP16P comment.
+
+2010-09-22 Robin Getz <robin.getz@analog.com>
+
+ * config/bfin-parse.y (is_store): New function.
+ (gen_multi_instr_1): Check parallel slots for store insns.
+
+2010-09-22 Robin Getz <robin.getz@analog.com>
+
+ * config/bfin-defs.h (IS_EMUDAT): New define.
+ * config/bfin-parse.y: Accept EMUDAT for any register move.
+
+2010-09-22 Robin Getz <robin.getz@analog.com>
+
+ * config/bfin-parse.y: Improve error messages.
+
+2010-09-22 Robin Getz <robin.getz@analog.com>
+
+ * config/bfin-parse.y (DBG): Fix regno encoding.
+ (DBGCMPLX): Likewise.
+
+2010-09-22 Robin Getz <robin.getz@analog.com>
+
+ * config/bfin-lex.l: Accept multibyte chars in symbol names.
+
+2010-09-22 Robin Getz <robin.getz@analog.com>
+
+ * config/bfin-defs.h (statusflags): Add AC0_COPY, V_COPY, and RND_MOD.
+ * config/bfin-lex.l: Tokenize AC0_COPY, V_COPY, and RND_MOD.
+
+2010-09-22 Mike Frysinger <vapier@gentoo.org>
+
+ * config/bfin-aux.h (bfin_gen_pseudochr): New prototype.
+ * config/tc-bfin.c (bfin_gen_pseudochr): New function.
+ * config/bfin-parse.y: Call bfin_gen_pseudochr for OUTC tokens.
+
+2010-09-22 Mike Frysinger <vapier@gentoo.org>
+
+ * config/bfin-lex.l (abort): Accept case-insensitive abort insn.
+ * config/bfin-parse.y (ABORT): Handle the ABORT token.
+
+2010-09-22 Mike Frysinger <vapier@gentoo.org>
+
+ * config/tc-bfin.c (bfin_cpus[]): Add 0.2 for bf512/bf514/bf516/bf518.
+
+2010-09-22 Mike Frysinger <vapier@gentoo.org>
+
+ * doc/c-bfin.texi (-mcpu): Add bf592.
+ * config/tc-bfin.c (bfin_cpu_type): Add BFIN_CPU_BF592.
+ (bfin_cpus[]): Add 0.0/0.1 for bf592.
+
+2010-09-22 Mike Frysinger <vapier@gentoo.org>
+
+ * config/tc-bfin.c (comment_chars): Add #.
+
+2010-09-20 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (arm_cpus): Correct canonical names for Cortex CPUs.
+
+2010-09-20 Richard Henderson <rth@redhat.com>
+
+ * config/tc-alpha.c (tc_gen_reloc): Remove hack around
+ bfd_perform_reloc for OBJ_ELF.
+
+2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
+
+ * config/tc-arm.c (do_t_ldmstm): Add logic to handle single-register
+ list for ldm/stm.
+
+2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
+
+ * config/tc-arm.c (parse_psr): Add condition for matching "APSR" on
+ non-M-arch cpus.
+ (psrs): Add entry for PSR flags, g, nzcvq, nzcvqg.
+
+2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
+
+ * config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead
+ of just RR.
+
+2010-09-17 Andrew Burgess <aburgess@broadcom.com>
+
+ PR gas/12011
+ * config/obj-elf.c (obj_elf_parse_section_letters): Correct test
+ for error return from md_elf_section_letter.
+ * config/tc-alpha.c (alpha_elf_section_letter): Correct error message.
+ * config/tc-i386.c (x86_64_section_letter): Likewise.
+ * config/tc-ia64.c (ia64_elf_section_letter): Likewise.
+ * config/tc-mep.c (mep_elf_section_letter): Likewise.
+
2010-09-15 Kai Tietz <kai.tietz@onevision.com>
- * config/obj-coff-seh.h (seh_context): New member code_seg.
- * config/obj-coff-seh.c: Implementing xdata/pdata section cloning
- for link-once code-segment.
+ * config/obj-coff-seh.c (seh_validate_seg): New funtion.
+ (obj_coff_seh_endproc): Add check for segment.
+ (obj_coff_seh_endprologue): Likewise.
+ (obj_coff_seh_pushreg): Likewise.
+ (obj_coff_seh_pushframe): Likewise.
+ (obj_coff_seh_save): Likewise.
+ (obj_coff_seh_setframe): Likewise.
+
+ * config/obj-coff-seh.h (seh_context): New member code_seg.
+ * config/obj-coff-seh.c: Implementing xdata/pdata section cloning
+ for link-once code-segment.
2010-09-14 Jie Zhang <jie@codesourcery.com>
projects / deliverable / binutils-gdb.git / blobdiff