+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/as.texinfo: Use MIPS rather than @sc{mips} throughout.
+ Use "CPU" instead of "cpu".
+ * doc/c-mips.texi: Likewise.
+ (MIPS Opts): Rename to MIPS Options.
+ (MIPS option stack): Rename to MIPS Option Stack.
+ (MIPS ASE instruction generation overrides): Rename to
+ MIPS ASE Instruction Generation Overrides (for now).
+ (MIPS floating-point): Rename to MIPS Floating-Point.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/c-mips.texi (MIPS Macros): New section.
+ (MIPS Object): Replace with...
+ (MIPS Small Data): ...this new section.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/c-mips.texi (MIPS symbol sizes): Move section further up file.
+ Capitalize name. Use @kindex instead of @cindex for .set entries.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/c-mips.texi (MIPS Stabs): Remove section.
+
+2013-06-20 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS, ISA_SUPPORTS_DSP_ASE)
+ (ISA_SUPPORTS_DSP64_ASE, ISA_SUPPORTS_DSPR2_ASE, ISA_SUPPORTS_EVA_ASE)
+ (ISA_SUPPORTS_MT_ASE, ISA_SUPPORTS_MCU_ASE, ISA_SUPPORTS_VIRT_ASE)
+ (ISA_SUPPORTS_VIRT64_ASE): Delete.
+ (mips_ase): New structure.
+ (mips_ases): New table.
+ (FP64_ASES): New macro.
+ (mips_ase_groups): New array.
+ (mips_isa_rev, mips_ase_mask, mips_check_isa_supports_ase)
+ (mips_check_isa_supports_ases, mips_set_ase, mips_lookup_ase): New
+ functions.
+ (is_opcode_valid): Use mips_ases to get the 64-bit ASE flags.
+ (md_parse_option): Use mips_ases and mips_set_ase instead of
+ separate case statements for each ASE option.
+ (mips_after_parse_args): Use FP64_ASES. Use
+ mips_check_isa_supports_ases to check the ASEs against
+ other options.
+ (s_mipsset): Use mips_ases and mips_set_ase instead of
+ separate if statements for each ASE option. Use
+ mips_check_isa_supports_ases, even when a non-ASE option
+ is specified.
+
+2013-06-19 Greta Yorsh <Greta.Yorsh@arm.com>
+
+ * config/tc-arm.c (arm_cpus): Add support for Cortex-A12.
+
+2013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (md_shortopts, options, md_longopts)
+ (md_longopts_size): Move earlier in file.
+
+2013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_set_options): Replace separate "ase_*" fields
+ with a single "ase" bitmask.
+ (mips_opts): Update accordingly.
+ (file_ase, file_ase_explicit): New variables.
+ (file_ase_mips3d, file_ase_mdmx, file_ase_smartmips, file_ase_dsp)
+ (file_ase_dspr2, file_ase_eva, file_ase_mt, file_ase_virt): Delete.
+ (ISA_HAS_ROR): Adjust for mips_set_options change.
+ (is_opcode_valid): Take the base ase mask directly from mips_opts.
+ (mips_ip): Adjust for mips_set_options change.
+ (md_parse_option): Likewise. Update file_ase_explicit.
+ (mips_after_parse_args): Adjust for mips_set_options change.
+ Use bitmask operations to select the default ASEs. Set file_ase
+ rather than individual per-ASE variables.
+ (s_mipsset): Adjust for mips_set_options change.
+ (mips_elf_final_processing): Test file_ase rather than
+ file_ase_mdmx. Remove commented-out code.
+
+2013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_cpu_info): Add an "ase" field.
+ (MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT)
+ (MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX, MIPS_CPU_ASE_DSPR2)
+ (MIPS_CPU_ASE_MCU, MIPS_CPU_ASE_VIRT, MIPS_CPU_ASE_EVA): Delete.
+ (mips_after_parse_args): Use the new "ase" field to choose
+ the default ASEs.
+ (mips_cpu_info_table): Move ASEs from the "flags" field to the
+ "ase" field.
+
+2013-06-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/tc-arm.c (symbol_preemptible): New function.
+ (relax_branch): Use it.
+
+2013-06-17 Catherine Moore <clm@codesourcery.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+ Chao-Ying Fu <fu@mips.com>
+
+ * config/tc-mips.c (mips_set_options): Add ase_eva.
+ (mips_set_options mips_opts): Add ase_eva.
+ (file_ase_eva): Declare.
+ (ISA_SUPPORTS_EVA_ASE): Define.
+ (IS_SEXT_9BIT_NUM): Define.
+ (MIPS_CPU_ASE_EVA): Define.
+ (is_opcode_valid): Add support for ase_eva.
+ (macro_build): Likewise.
+ (macro): Likewise.
+ (validate_mips_insn): Likewise.
+ (validate_micromips_insn): Likewise.
+ (mips_ip): Likewise.
+ (options): Add OPTION_EVA and OPTION_NO_EVA.
+ (md_longopts): Add -meva and -mno-eva.
+ (md_parse_option): Process new options.
+ (mips_after_parse_args): Check for valid EVA combinations.
+ (s_mipsset): Likewise.
+
+2013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
+
+ * dwarf2dbg.h (dwarf2_move_insn): Declare.
+ * dwarf2dbg.c (line_subseg): Add pmove_tail.
+ (get_line_subseg): Add create_p argument. Initialize pmove_tail.
+ (dwarf2_gen_line_info_1): Update call accordingly.
+ (dwarf2_move_insn): New function.
+ * config/tc-mips.c (append_insn): Use dwarf2_move_insn.
+
+2013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
+
+ Revert:
+
+ 2011-09-05 Richard Sandiford <rdsandiford@googlemail.com>
+
+ PR gas/13024
+ * dwarf2dbg.c (pending_lines, pending_lines_tail): New variables.
+ (dwarf2_gen_line_info_1): Delete.
+ (dwarf2_push_line, dwarf2_flush_pending_lines): New functions.
+ (dwarf2_gen_line_info, dwarf2_emit_label): Use them.
+ (dwarf2_consume_line_info): Call dwarf2_flush_pending_lines.
+ (dwarf2_directive_loc): Push previous .locs instead of generating
+ them immediately.
+
+2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
+
+ * config/tc-mips.c (ISA_SUPPORTS_VIRT_ASE): Support micromips.
+ (ISA_SUPPORTS_VIRT64_ASE): Support 64-bit micromips.
+
+2013-06-13 Nick Clifton <nickc@redhat.com>
+
+ PR gas/15602
+ * config/tc-m68k.h (TC_CHECK_ADJUSTED_BROKEN_DOT_WORD): Define.
+ * config/tc-m68k.c (tc_m68k_check_adjusted_broken_word): New
+ function. Generates an error if the adjusted offset is out of a
+ 16-bit range.
+
+2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
+
+ * config/tc-nios2.c (md_apply_fix): Mask constant
+ BFD_RELOC_NIOS2_HIADJ16 value to 16 bits.
+
+2013-06-10 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (append_insn): Don't do branch relaxation for
+ MIPS-3D instructions either.
+ (md_convert_frag): Update the COPx branch mask accordingly.
+
+ * config/tc-mips.c (md_show_usage): Document --[no-]relax-branch
+ option.
+ * doc/as.texinfo (Overview): Add --relax-branch and
+ --no-relax-branch.
+ * doc/c-mips.texi (MIPS Opts): Document --relax-branch and
+ --no-relax-branch.
+
+2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
+
+ * config/tc-nios2.c (nios2_parse_args): Allow trap argument to
+ omitted.
+
+2013-06-08 Catherine Moore <clm@codesourcery.com>
+
+ * config/tc-mips.c (is_opcode_valid): Build ASE mask.
+ (is_opcode_valid_16): Pass ase value to opcode_is_member.
+ (append_insn): Change INSN_xxxx to ASE_xxxx.
+
+2013-06-01 George Thomas <george.thomas@atmel.com>
+
+ * gas/config/tc-avr.c: Change ISA for devices with USB support to
+ AVR_ISA_XMEGAU
+
+2013-05-31 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (md_begin): Don't align text/data/bss sections
+ for ELF.
+
+2013-05-31 Paul Brook <paul@codesourcery.com>
+
+ gas/
+ * config/tc-mips.c (s_ehword): New.
+
+2013-05-30 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-mips.c (md_apply_fix): Support BFD_RELOC_MIPS_EH.
+
+2013-05-29 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * write.c (resolve_reloc_expr_symbols): On REL targets don't
+ convert relocs who have no relocatable field either. Rephrase
+ the conditional so that the PC-relative check is only applied
+ for REL targets.
+
+2013-05-28 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
+
+ * config/tc-mips.c (macro) <ld>: Don't use $zero for address
+ calculation.
+
+2013-05-28 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): Update to use
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 instead of
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE.
+ (md_apply_fix): Likewise.
+ (aarch64_force_relocation): Likewise.
+
+2013-05-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/tc-arm.c (it_fsm_post_encode): Improve
+ warning messages about deprecated IT block formats.
+
+2013-05-28 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * config/tc-aarch64.c (md_apply_fix): Move value range checking
+ inside fx_done condition.
+
+2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
+
+ * config/tc-mips.c (macro): Handle M_LQC2_AB and M_SQC2_AB.
+
+2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
+
+ * config/tc-ppc.c (ppc_setup_opcodes): Use new_seg to fix error
+ and clean up warning when using PRINT_OPCODE_TABLE.
+
+2013-05-20 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_apply_fix): Hoist code common to insn
+ and data fixups performing shift/high adjust/sign extension on
+ fieldval. Sink fx_pcrel handling and checks. Use fixP->fx_size
+ when writing data fixups rather than recalculating size.
+
+2013-05-16 Jan-Benedict Glaw <jbglaw@lug-owl.de>
+
+ * doc/c-msp430.texi: Fix typo.
+
+2013-05-16 Tristan Gingold <gingold@adacore.com>
+
+ * config/tc-ppc.c (ppc_is_toc_sym): Symbols of class XMC_TC
+ are also TOC symbols.
+
+2013-05-16 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-msp430.c: Make -mmcu recognise more part numbers.
+ Add -mcpu command to specify core type.
+ * doc/c-msp430.texi: Update documentation.
+
+2013-05-09 Andrew Pinski <apinski@cavium.com>
+
+ * config/tc-mips.c (struct mips_set_options): New ase_virt field.
+ (mips_opts): Update for the new field.
+ (file_ase_virt): New variable.
+ (ISA_SUPPORTS_VIRT_ASE): New macro.
+ (ISA_SUPPORTS_VIRT64_ASE): New macro.
+ (MIPS_CPU_ASE_VIRT): New define.
+ (is_opcode_valid): Handle ase_virt.
+ (macro_build): Handle "+J".
+ (validate_mips_insn): Likewise.
+ (mips_ip): Likewise.
+ (enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
+ (md_longopts): Add mvirt and mnovirt
+ (md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
+ (mips_after_parse_args): Handle ase_virt field.
+ (s_mipsset): Handle "virt" and "novirt".
+ (mips_elf_final_processing): Add a comment about virt ASE might need
+ a new flag.
+ (md_show_usage): Print out the usage of -mvirt and mno-virt options.
+ * doc/c-mips.texi: Document -mvirt and -mno-virt.
+ Document ".set virt" and ".set novirt".
+
+2013-05-09 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_apply_fix): Sign extend fieldval under
+ control of operand flag bits.
+
+2013-05-07 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (PPC_VLE_SPLIT16A): Delete unused macro.
+ (PPC_VLE_SPLIT16D, PPC_VLE_LO16A, PPC_VLE_LO16D): Likewise.
+ (PPC_VLE_HI16A, PPC_VLE_HI16D): Likewise.
+ (PPC_VLE_HA16A, PPC_VLE_HA16D): Likewise.
+ (md_apply_fix): Set fx_no_overflow for assorted relocations.
+ Shift and sign-extend fieldval for use by some VLE reloc
+ operand->insert functions.
+
+2013-05-06 Paul Brook <paul@codesourcery.com>
+ Catherine Moore <clm@codesourcery.com>
+
+ * config/tc-mips.c (md_pcrel_from): Handle BFD_RELOC_32_PCREL.
+ (limited_pcrel_reloc_p): Likewise.
+ (md_apply_fix): Likewise.
+ (tc_gen_reloc): Likewise.
+
+2013-05-06 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (limited_pcrel_reloc_p): New function.
+ (mips_fix_adjustable): Adjust pc-relative check to use
+ limited_pc_reloc_p.
+
+2013-05-02 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_pseudo_table): Add stabd and stabs entries.
+ (s_mips_stab): Do not restrict to stabn only.
+
2013-05-02 Nick Clifton <nickc@redhat.com>
* config/tc-msp430.c: Add support for the MSP430X architecture.
projects / deliverable / binutils-gdb.git / blobdiff