+2018-01-17 Jim Wilson <jimw@sifive.com>
+
+ * config/tc-riscv.c (validate_riscv_insn) <'z'>: New.
+ (riscv_ip) <'z'>: New.
+
+2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk.
+ (cpu_noarch): Add noibt, noshstk.
+ (parse_insn): Change cpucet to cpuibt.
+ * doc/c-i386.texi: Delete .cet. Add .ibt, .shstk.
+ * testsuite/gas/i386/cet-ibt-inval.l: New test.
+ * testsuite/gas/i386/cet-ibt-inval.s: Likewise.
+ * testsuite/gas/i386/cet-shstk-inval.l: Likewise.
+ * testsuite/gas/i386/cet-shstk-inval.s: Likewise.
+ * testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise.
+ * testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise.
+ * testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise.
+ * testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise.
+
+2018-01-16 Nick Clifton <nickc@redhat.com>
+
+ * po/fr.po: Updated French translation.
+
+2018-01-15 Jim Wilson <jimw@sifive.com>
+
+ * testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop.
+ * testsuite/gas/riscv/c-zero-imm.d: Likewise.
+
+2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (ToC): Define macro.
+ (ToU): Likewise.
+ (insns): Make use of above macros for new instructions introduced in
+ Armv8-M.
+
+2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (insns): Make blxns, bxns, tt, ttt, tta, ttat, vlldm
+ and vlstm conditionally executable and reindent parameters.
+ * testsuite/gas/arm/archv8m-cmse-main.s: Add conditional version of
+ aforementionned instructions.
+
+2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (it_fsm_post_encode): Do not warn if targeting M
+ profile architecture or if in autodetection mode. Clarify that
+ deprecation is for performance reason and concerns Armv8-A and Armv8-R.
+ * testsuite/gas/arm/armv8-ar-bad.l: Adapt to new IT deprecation warning
+ message.
+ * testsuite/gas/arm/armv8-ar-it-bad.l: Likewise.
+ * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: Likewise.
+ * testsuite/gas/arm/udf.l: Likewise.
+ * testsuite/gas/arm/udf.d: Assemble for Armv8-A explicitely.
+
+2018-01-15 Nick Clifton <nickc@redhat.com>
+
+ * po/uk.po: Updated Ukranian translation.
+
+2018-01-13 Nick Clifton <nickc@redhat.com>
+
+ * po/gas.pot: Regenerated.
+
+2018-01-13 Nick Clifton <nickc@redhat.com>
+
+ * configure: Regenerate.
+
+2018-01-13 Nick Clifton <nickc@redhat.com>
+
+ 2.30 branch created.
+ * NEWS: Add marker for 2.30.
+
+2018-01-12 Gunther Nikl <gnikl@users.sourceforge.net>
+
+ * gas/config/aout_gnu.h (USE_EXTENDED_RELOC): Explicitly
+ define to 0 and 1. Remove a dangling reference to "AMD 29000"
+ in a comment.
+
+2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * testsuite/i386/avx512_4fmaps_vl-warn.l: Likewise.
+ * testsuite/i386/avx512_4fmaps_vl-warn.s: Likewise.
+ * testsuite/i386/avx512_4fmaps_vl.d: Likewise.
+ * testsuite/i386/avx512_4fmaps_vl.s: Likewise.
+ * testsuite/i386/avx512_4vnniw_vl-intel.d: Likewise.
+ * testsuite/i386/avx512_4vnniw_vl.d: Likewise.
+ * testsuite/i386/avx512_4vnniw_vl.s: Likewise.
+ * testsuite/i386/i386.exp: Removed _vl tests for 4fmaps an 4vnniw
+ tests.
+ * testsuite/i386/x86-64-avx512_4fmaps_vl-intel.d: Removed.
+ * testsuite/i386/x86-64-avx512_4fmaps_vl-warn.l: Likewise.
+ * testsuite/i386/x86-64-avx512_4fmaps_vl-warn.s: Likewise.
+ * testsuite/i386/x86-64-avx512_4fmaps_vl.d: Likewise.
+ * testsuite/i386/x86-64-avx512_4fmaps_vl.s: Likewise.
+ * testsuite/i386/x86-64-avx512_4vnniw_vl-intel.d: Likewise.
+ * testsuite/i386/x86-64-avx512_4vnniw_vl.d: Likewise.
+ * testsuite/i386/x86-64-avx512_4vnniw_vl.s: Likewise.
+
+2018-01-11 Alan Modra <amodra@gmail.com>
+
+ * config/tc-arm.c (aeabi_set_public_attributes): Avoid false
+ positive "‘profile’ may be used uninitialized".
+
+2018-01-10 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/avx512_4fmaps.s,
+ testsuite/gas/i386/avx512_4fmaps_vl.s,
+ testsuite/gas/i386/x86-64-avx512_4fmaps.s,
+ testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Actually test
+ Disp8 forms (and the transition happening at the right
+ boundary).
+ * testsuite/gas/i386/avx512_4fmaps.d,
+ testsuite/gas/i386/avx512_4fmaps-intel.d,
+ testsuite/gas/i386/avx512_4fmaps_vl.d,
+ testsuite/gas/i386/avx512_4fmaps_vl-intel.d,
+ testsuite/gas/i386/x86-64-avx512_4fmaps.d,
+ testsuite/gas/i386/x86-64-avx512_4fmaps-intel.d,
+ testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d,
+ testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Adjust
+ expectations.
+
+2018-01-10 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/avx512bw.s,
+ testsuite/gas/i386/avx512bw_vl.s: Add VPCMP* tests with memory
+ operands.
+ * testsuite/gas/i386/avx512bw-intel.d,
+ testsuite/gas/i386/avx512bw.d,
+ testsuite/gas/i386/avx512bw_vl-intel.d.
+ testsuite/gas/i386/avx512bw_vl.d: Adjust expectations.
+
+2018-01-09 Jim Wilson <jimw@sifive.com>
+
+ * testsuite/gas/riscv/auipc-x0.d: New.
+ * testsuite/gas/riscv/auipc-x0.s: New.
+
+2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * config/tc-arm.c (insns): Add csdb, enable for Armv3 and above
+ in Arm execution state, and Armv6T2 and above in Thumb execution
+ state.
+ * testsuite/gas/arm/csdb.s: New.
+ * testsuite/gas/arm/csdb.d: New.
+ * testsuite/gas/arm/thumb2_it_bad.l: Add csdb.
+ * testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
+
+2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * testsuite/gas/aarch64/system.d: Update expected results to expect
+ CSDB for hint 0x14.
+
+2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/22681
+ * testsuite/gas/i386/i386.exp: Run x86-64-movd and
+ x86-64-movd-intel.
+ * testsuite/gas/i386/x86-64-movd-intel.d: New file.
+ * testsuite/gas/i386/x86-64-movd.d: Likewise.
+ * testsuite/gas/i386/x86-64-movd.s: Likewise.
+
2018-01-08 Nick Clifton <nickc@redhat.com>
PR 22553
projects / deliverable / binutils-gdb.git / blobdiff