Automatic date update in version.in

[deliverable/binutils-gdb.git] / gas / ChangeLog

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+2020-10-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/25878
+       PR gas/26740
+       * dwarf2dbg.c (file_entry): Remove auto_assigned.
+       (assign_file_to_slot): Remove the auto_assign argument.
+       (allocate_filenum): Updated.
+       (allocate_filename_to_slot): Reuse the input file entry in the
+       file table.
+       (dwarf2_where): Replace as_where with as_where_physical.
+       * testsuite/gas/i386/dwarf5-line-1.d: New file.
+       * testsuite/gas/i386/dwarf5-line-1.s: Likewise.
+       * testsuite/gas/i386/i386.exp: Run dwarf5-line-1.
+
+2020-10-16  Lili Cui  <lili.cui@intel.com>
+
+       * config/tc-i386.c (cpu_flags_match): Move Pseudo Prefix check
+       to ...
+       (match_template): Here.
+       * testsuite/gas/i386/avx-vnni-inval.l: New file.
+       * testsuite/gas/i386/avx-vnni-inval.s: Likewise.
+       * testsuite/gas/i386/avx-vnni.d: Delete invalid {vex2} test.
+       * testsuite/gas/i386/avx-vnni.s: Likewise.
+       * testsuite/gas/i386/i386.exp: Add AVX VNNI invalid tests.
+       * testsuite/gas/i386/x86-64-avx-vnni-inval.l: New file.
+       * testsuite/gas/i386/x86-64-avx-vnni-inval.s: Likewise.
+       * testsuite/gas/i386/x86-64-avx-vnni.d: Delete invalid {vex2} test.
+       * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise.
+
+2020-10-14  H.J. Lu  <hongjiu.lu@intel.com>
+           Lili Cui  <lili.cui@intel.com>
+
+       * NEWS: Add Intel AVX VNNI.
+       * config/tc-i386.c (cpu_arch): Add .avx_vnni and noavx_vnni.
+       (cpu_flags_match): Support CpuVEX_PREFIX.
+       * doc/c-i386.texi: Document .avx_vnni, noavx_vnni and how to
+       encode Intel VNNI instructions with VEX prefix.
+       * testsuite/gas/i386/avx-vnni.d: New file.
+       * testsuite/gas/i386/avx-vnni.s: Likewise.
+       * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise.
+       * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise.
+       * testsuite/gas/i386/i386.exp: Run AVX VNNI tests.
+
+2020-10-14  Lili Cui  <lili.cui@intel.com>
+
+       * NEWS: Add Intel HRESET.
+       * config/tc-i386.c (cpu_arch): Add .hreset.
+       (cpu_noarch): Likewise.
+       * doc/c-i386.texi: Document .hreset, nohreset.
+       * testsuite/gas/i386/i386.exp: Run HRESET tests.
+       * testsuite/gas/i386/hreset.d: New file.
+       * testsuite/gas/i386/x86-64-hreset.d: Likewise.
+       * testsuite/gas/i386/hreset.s: Likewise.
+
+2020-10-14  Lili Cui  <lili.cui@intel.com>
+
+       * NEWS: Add Intel UINTR.
+       * config/tc-i386.c (cpu_arch): Add .uintr.
+       (cpu_noarch): Likewise.
+       * doc/c-i386.texi: Document .uintr and nouintr.
+       * testsuite/gas/i386/i386.exp: Run UINTR tests.
+       * testsuite/gas/i386/x86-64-uintr.d: Likewise.
+       * testsuite/gas/i386/x86-64-uintr.s: Likewise.
+
+2020-10-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (load_insn_p): Check opcodeprefix == 0 for
+       base_opcode == 0xfc7.
+       (match_template): Likewise.
+       (process_suffix): Check opcodeprefix == PREFIX_0XF2 for CRC32.
+       (check_byte_reg): Likewise.
+       (output_insn): Don't add the 0xf3 prefix twice for PadLock
+       instructions.  Don't add prefix from non-VEX/EVEX base_opcode.
+
+2020-10-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (build_vex_prefix): Replace vexopcode with
+       opcodeprefix.
+       (build_evex_prefix): Likewise.
+       (is_any_vex_encoding): Don't check vexopcode.
+       (output_insn): Handle opcodeprefix.
+
 2020-10-09  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR gas/26703