+start-sanitize-d10v
+Wed Jul 31 14:46:11 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * config/tc-d10v.c: Disable range checking on 16-bit values.
+
+end-sanitize-d10v
+Wed Jul 31 16:27:19 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * config/tc-m68k.c (m68k_ip): Set ok_arch for every instruction,
+ not just the ones that don't match.
+
+start-sanitize-d10v
+Wed Jul 31 11:45:15 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * config/tc-d10v.c: Fixed bugs in short relocs and range checking.
+
+end-sanitize-d10v
+Wed Jul 31 15:41:42 1996 James G. Smith <jsmith@cygnus.co.uk>
+
+ * config/tc-arm.c: Changed INSN_SIZE to variable insn_size, as
+ pre-cursor to adding Thumb support. Also added cpu_variant flag
+ information to each of the asm_flg structures.
+ (md_parse_option): Updated ARM7 parsing to allow 't' for
+ thumb/halfword support, aswell as 'm' for long multiply.
+ (md_show_usage): Updated help message.
+ (md_assemble): Check that instruction flags are applicated to the
+ current cpu variant.
+ (md_apply_fix3, tc_gen_reloc): Add BFD_RELOC_ARM_OFFSET_IMM8 and
+ BFD_RELOC_ARM_HWLITERAL relocation support for new halfword and
+ signextension instructions.
+ (do_ldst): Generate halfword and signextension variants if
+ mnemonic flags match.
+ (ldst_extend): Do not allow shifts in the offset field of halfword
+ or signextension instructions.
+ (validate_offset_imm): Provide check on halfword and signextension
+ immediate range.
+ (add_to_lit_pool): Merge identical literal pool values.
+
+Tue Jul 30 14:28:23 1996 Jeffrey A Law (law@cygnus.com)
+
+ * config/tc-hppa.c (selector_table): Add 'E' selector.
+ (cons_fix_new_hppa): Don't coke on e_esel.
+ (tc_gen_reloc, SOM version): Handle R_COMP2 when used
+ to help generate exception handling tables.
+ (md_apply_fix): Don't try to apply fixups with an e_esel
+ selector.
+ (hppa_fix_adjustable): Fixups with e_esel selectors
+ are not adjustable.
+
+Tue Jul 30 15:51:41 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * config/tc-sparc.c (md_pseudo_table): Add 2byte, 4byte, and 8byte
+ pseudo-ops.
+
+start-sanitize-d10v
+Fri Jul 26 11:43:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * config/tc-d10v.c: Added lots of error checking. Added hacks
+ to support accumulator shifts.
+
+end-sanitize-d10v
+Fri Jul 26 11:56:08 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * symbols.c (S_SET_EXTERNAL): Let .weak override.
+ (S_CLEAR_EXTERNAL): Likewise.
+ (S_SET_WEAK): Remove error; just let .weak override.
+
+start-sanitize-d10v
+Thu Jul 25 15:22:51 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * config/tc-d10v.c (md_assemble): Now handles multiline
+ instructions.
+
+Thu Jul 25 12:03:33 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * config/tc-d10v.c: Fix packaging bug. Added range checking.
+ Added kludge for divs instruction. Fixed minor problem with
+ multiple text sections.
+ * config/tc-d10v.h (d10v_cleanup): Change prototype.
+
+Tue Jul 23 10:49:36 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * config/tc-d10v.c (md_apply_fix3): Fix all instruction
+ addresses to be right-shifted by 2.
+
+Mon Jul 22 11:32:36 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * config/tc-d10v.c: Many changes to get relocs working.
+ (register_name): No longer creates a symbol for register names.
+ (pre_defined_registers): moved to opcodes/d10v-opc.c.
+ (d10v_insert_operand): Now works correctly for either container.
+ * config/tc-d10v.h (d10v_cleanup): Declare.
+
+end-sanitize-d10v
+Mon Jul 22 14:01:33 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * config/tc-mips.c (tc_gen_reloc): BFD_RELOC_PCREL_HI16_S and
+ BFD_RELOC_PCREL_LO16 are expected to be PC relative.
+
+Mon Jul 22 12:46:55 1996 Richard Henderson <rth@tamu.edu>
+
+ * tc-alpha.c: Patches to track current minimum alignment to reduce
+ the number of fragments created with frag_align.
+ (alpha_current_align): New static variable.
+ (s_alpha_text): Reset alignment to 0.
+ (s_alpha_data, s_alpha_rdata, s_alpha_sdata): Likewise.
+ (s_alpha_stringer, s_alpha_space): New functions.
+ (s_alpha_cons, alpha_flush_pending_output): Remove functions.
+ (alpha_cons_align): New function to replace both of them.
+ (emit_insn): Only align if alpha_current_align is less than 2;
+ reset alpha_current_align to 2.
+ (s_alpha_gprel32): Likewise.
+ (s_alpha_section): New function. Basically duplicate the other
+ alpha section change hooks. Only define for ELF.
+ (s_alpha_float_cons): Simplify alignment handling.
+ (md_pseudo_table): Only define "rdata" and "sdata" if OBJ_ECOFF.
+ If OBJ_ELF, define "section", "section.s", "sect", and "sect.s".
+ Don't define the s_alpha_cons pseudo-ops. Do define
+ s_alpha_stringer and s_alpha_space pseudo-ops.
+ (alpha_align): Skip if less than current default alignment. Set
+ default alignment.
+ * tc-alpha.h (md_flush_pending_output): Remove.
+ (md_cons_align): Add.
+
+ * tc-alpha.c: Add oodles of function description comments.
+ (md_bignum_to_chars): Remove; there are no callers.
+ (md_show_usage): Mention some more variants.
+
Thu Jul 18 15:54:54 1996 Ian Lance Taylor <ian@cygnus.com>
+ From Andrew Gierth <ANDREWG@microlise.co.uk>:
+ * configure.in (sparc-*-sysv4*): New target.
+ * configure: Rebuild.
+
+ * config/tc-sparc.c (md_pseudo_table): Change uahalf, uaword, and
+ uaxword to use s_uacons.
+ (sparc_no_align_cons): New static variable.
+ (s_uacons): New static function.
+ (sparc_cons_align): If sparc_no_align_cons is set, just clear it
+ and return.
+
+ * config/tc-sparc.c (s_common): Remove unused label allocate_bss.
+
+ * configure.in: Add mips-*-irix6* target. Handle Irix 6 like Irix
+ 5 with regard to shared libraries.
+ * configure: Rebuild.
+
* config/tc-m68k.c (m68k_ip): Use the correct length when
allocating space for the unsupported architecture error message.
projects / deliverable / binutils-gdb.git / blobdiff