* emultempl/sunos.em (gld${EMULATION_NAME}_after_open): Move

[deliverable/binutils-gdb.git] / gas / ChangeLog

diff --git a/gas/ChangeLog b/gas/ChangeLog
index fbabc46f85b6ff929948670dadf7379e78604a43..b1d10d501376c9d7ebbb5442d82acff0fec342a1 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,10 +1,83 @@
 start-sanitize-d10v
+Wed Jul 31 14:46:11 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+       * config/tc-d10v.c: Disable range checking on 16-bit values.
+
+end-sanitize-d10v      
+Wed Jul 31 16:27:19 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+       * config/tc-m68k.c (m68k_ip): Set ok_arch for every instruction,
+       not just the ones that don't match.
+
+start-sanitize-d10v
+Wed Jul 31 11:45:15 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+       * config/tc-d10v.c: Fixed bugs in short relocs and range checking.
+
+end-sanitize-d10v
+Wed Jul 31 15:41:42 1996  James G. Smith  <jsmith@cygnus.co.uk>
+
+       * config/tc-arm.c: Changed INSN_SIZE to variable insn_size, as
+       pre-cursor to adding Thumb support. Also added cpu_variant flag
+       information to each of the asm_flg structures.
+       (md_parse_option): Updated ARM7 parsing to allow 't' for
+       thumb/halfword support, aswell as 'm' for long multiply.
+       (md_show_usage): Updated help message.
+       (md_assemble): Check that instruction flags are applicated to the
+       current cpu variant.
+       (md_apply_fix3, tc_gen_reloc): Add BFD_RELOC_ARM_OFFSET_IMM8 and
+       BFD_RELOC_ARM_HWLITERAL relocation support for new halfword and
+       signextension instructions.
+       (do_ldst): Generate halfword and signextension variants if
+       mnemonic flags match.
+       (ldst_extend): Do not allow shifts in the offset field of halfword
+       or signextension instructions.
+       (validate_offset_imm): Provide check on halfword and signextension
+       immediate range.
+       (add_to_lit_pool): Merge identical literal pool values.
+
+Tue Jul 30 14:28:23 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * config/tc-hppa.c (selector_table): Add 'E' selector.
+       (cons_fix_new_hppa): Don't coke on e_esel.
+       (tc_gen_reloc, SOM version): Handle R_COMP2 when used
+       to help generate exception handling tables.
+       (md_apply_fix): Don't try to apply fixups with an e_esel
+       selector.
+       (hppa_fix_adjustable): Fixups with e_esel selectors
+       are not adjustable.
+
+Tue Jul 30 15:51:41 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+       * config/tc-sparc.c (md_pseudo_table): Add 2byte, 4byte, and 8byte
+       pseudo-ops.
+
+start-sanitize-d10v
+Fri Jul 26 11:43:03 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+       * config/tc-d10v.c: Added lots of error checking.  Added hacks
+       to support accumulator shifts.
+       
+end-sanitize-d10v
+Fri Jul 26 11:56:08 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+       * symbols.c (S_SET_EXTERNAL): Let .weak override.
+       (S_CLEAR_EXTERNAL): Likewise.
+       (S_SET_WEAK): Remove error; just let .weak override.
+
+start-sanitize-d10v
+Thu Jul 25 15:22:51 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+       * config/tc-d10v.c (md_assemble): Now handles multiline
+       instructions.
+
 Thu Jul 25 12:03:33 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
        * config/tc-d10v.c: Fix packaging bug. Added range checking.
        Added kludge for divs instruction.  Fixed minor problem with
        multiple text sections.
-
+       * config/tc-d10v.h (d10v_cleanup): Change prototype. 
+       
 Tue Jul 23 10:49:36 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
        * config/tc-d10v.c (md_apply_fix3): Fix all instruction