+Mon Oct 19 12:35:43 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * cgen.c (gas_cgen_finish_insn): Update handling of CGEN_INT_INSN_P.
+ * cgen.h (gas_cgen_finish_insn): Update prototype.
+ * config/tc-m32r.c (m32r_insn): CGEN_INT_INSN -> CGEN_INT_INSN_P.
+ cgen_insn_t -> CGEN_INSN_INT.
+ (make_parallel): Update handling of CGEN_INT_INSN_P.
+ (assemble_parallel_insn): Ditto.
+ (target_make_parallel): New function.
+ (md_assemble): Use it.
+
+Mon Oct 19 13:16:12 1998 Catherine Moore <clm@cygnus.com>
+
+ * config/tc-m32r.c (m32r_force_relocation): Fix typo.
+
+Sun Oct 18 18:48:57 1998 Jeffrey A Law (law@cygnus.com)
+
+ * config/tc-sh.c (md_assemble): Make sure the entire opcode is
+ converted into lower case.
+
+Fri Oct 16 13:36:34 CDT Catherine Moore <clm@cygnus.com>
+
+ * cgen.c (gas_cgen_md_apply_fix3): Handle VTABLE relocs.
+ (gas_cgen_tc_gen_reloc): Likewise.
+ * config/tc-m32r.h (obj_fix_adjustable): Define.
+ * config/tc-m32r.c (m32r_fix_adjustable): New.
+ (m32r_force_relocation): Handle VTABLE relocs.
+
+Wed Oct 14 11:33:38 1998 Nick Clifton <nickc@cygnus.com>
+
+ * doc/c-arm.texi (ARM Directives): Document .ltorn directive.
+
+Mon Oct 12 11:07:21 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-m32r.c (assemble_parallel_insn): Convert second opcode
+ to lower case before parsing.
+
+ * config/tc-d30v.c (parallel_ok): Ignore conflicts when explicitly
+ parallel insns modift buts in the PSW as a side effect.
+
+Thu Oct 8 10:18:33 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-d30v.c (find_format): Test for missing flag and
+ control registers.
+
+ (md_apply_fix3): Fix error messages to avoid
+ assumption about presence of a symbol.
+
+ (parallel_ok): Disallow parallel instructions that both modify the
+ same flag register.
+
+ (find_format): Generate a warning if an odd numbered register is
+ used as the first register in a mutli-register instruction.
+
+Wed Oct 7 14:09:14 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-d30v.c (md_apply_fix3): Do not assume that bad
+ relocations are always associated with a symbol.
+
+Tue Oct 6 09:31:15 1998 Catherine Moore <clm@cygnus.com>
+
+ * tc-sparc.h (TC_FORCE_RELOCATION): Define.
+ (elf32_sparc_force_relocation): Declare.
+ * tc-sparc.c (md_apply_fix3): Handle vtable relocs.
+ (tc_gen_reloc): Handle vtable relocs.
+ (elf32_sparc_force_relocation): New.
+
+Mon Oct 5 09:25:32 1998 Catherine Moore <clm@cygnsu.com>
+
+ * symbols.c (S_IS_FUNCTION): New.
+ * config/tc-v850.h (obj_fix_adjustable): Define.
+ (TC_FORCE_RELOCATION): Define.
+ (v850_force_relocation): Declare.
+ * config/tc-v850.c (tc_gen_reloc): Use offset instead
+ of fx_addnumber for VTABLE reloc addends.
+ (md_apply_fix3): Handle VTABLE relocs.
+ (v850_fix_adjustable): New.
+ (v850_force_relocation): New.
+
+Mon Oct 5 00:48:52 1998 Jeffrey A Law (law@cygnus.com)
+
+ * tc-hppa.c (fp_operand_format): Add some additional formats.
+ (pa_ip): Do not automatically promote into pa2.0 mode.
+ (pa_level): Handle ".level 2.0".
+start-sanitize-cygnus
+ (struct pa_it): New field "trunc".
+ (pa_parse_fp_cnv_format): New function.
+ (pa_parse_ftest_gfx_completer): New function.
+ (pa_ip): Handle various new letters for PA2.0 support.
+end-sanitize-cygnus
+
+Sun Oct 4 20:57:43 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * config/tc-i386.c (md_assemble): Handle AMD_3DNOW_OPCODE.
+ * config/tc-i386.h (template.extension_opcode): Change to
+ unsigned int to allow full range of 8-bit opcode suffixes.
+ (None): Redefine as 0xffff.
+
+ From Jeff B Epler <jepler@usgs.gov>
+ * doc/c-i386.texi (i386-SIMD): New section.
+
+Thu Oct 1 15:37:54 1998 Richard Henderson <rth@cygnus.com>
+
+ * read.c (discard_rest_of_line): New function.
+ * read.h: Declare it.
+ * config/tc-alpha.c (s_alpha_mask, s_alpha_frame): Use it.
+
+Thu Oct 1 10:33:53 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-d10v.c (find_symbol_matching_register): New function.
+ (find_opcode): Cope with the case where a register name matches
+ a symbol name.
+
+Wed Sep 30 10:52:32 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-v850.c (md_pcrel_from): Rename to
+ v850_pcrel_from_section.
+ (v850_pcrel_from_section): Do not resolves symbols in other
+ sections.
+
+ * config/tc-v850.h (MD_PCREL_FROM_SECTION): Define.
+
+Mon Sep 28 11:01:20 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-d10v.c (find_opcode): Generate an error if a register
+ is supplied for an operand that should not be a register.
+
+Fri Sep 25 10:04:21 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-d30v.c (write_2_short): But do allow delayed branch
+ instructions to have another instruction in the right bin.
+
+Thu Sep 24 09:28:34 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-d30v.c (write_2_short): Do not allow instructions in
+ the right container if the left container holds a branch
+ instruction.
+
Wed Sep 23 10:54:29 1998 Nick Clifton <nickc@cygnus.com>
* config/tc-d30v.c (reg_name_search): Only warn if a name matches