+Mon Oct 19 12:35:43 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * cgen.c (gas_cgen_finish_insn): Update handling of CGEN_INT_INSN_P.
+ * cgen.h (gas_cgen_finish_insn): Update prototype.
+ * config/tc-m32r.c (m32r_insn): CGEN_INT_INSN -> CGEN_INT_INSN_P.
+ cgen_insn_t -> CGEN_INSN_INT.
+ (make_parallel): Update handling of CGEN_INT_INSN_P.
+ (assemble_parallel_insn): Ditto.
+ (target_make_parallel): New function.
+ (md_assemble): Use it.
+
+Mon Oct 19 13:16:12 1998 Catherine Moore <clm@cygnus.com>
+
+ * config/tc-m32r.c (m32r_force_relocation): Fix typo.
+
+Sun Oct 18 18:48:57 1998 Jeffrey A Law (law@cygnus.com)
+
+ * config/tc-sh.c (md_assemble): Make sure the entire opcode is
+ converted into lower case.
+
+Fri Oct 16 13:36:34 CDT Catherine Moore <clm@cygnus.com>
+
+ * cgen.c (gas_cgen_md_apply_fix3): Handle VTABLE relocs.
+ (gas_cgen_tc_gen_reloc): Likewise.
+ * config/tc-m32r.h (obj_fix_adjustable): Define.
+ * config/tc-m32r.c (m32r_fix_adjustable): New.
+ (m32r_force_relocation): Handle VTABLE relocs.
+
+Wed Oct 14 11:33:38 1998 Nick Clifton <nickc@cygnus.com>
+
+ * doc/c-arm.texi (ARM Directives): Document .ltorn directive.
+
+Mon Oct 12 11:07:21 1998 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-m32r.c (assemble_parallel_insn): Convert second opcode
+ to lower case before parsing.
+
+ * config/tc-d30v.c (parallel_ok): Ignore conflicts when explicitly
+ parallel insns modift buts in the PSW as a side effect.
+
Thu Oct 8 10:18:33 1998 Nick Clifton <nickc@cygnus.com>
* config/tc-d30v.c (find_format): Test for missing flag and
control registers.
+
+ (md_apply_fix3): Fix error messages to avoid
+ assumption about presence of a symbol.
+
+ (parallel_ok): Disallow parallel instructions that both modify the
+ same flag register.
+
+ (find_format): Generate a warning if an odd numbered register is
+ used as the first register in a mutli-register instruction.
Wed Oct 7 14:09:14 1998 Nick Clifton <nickc@cygnus.com>
projects / deliverable / binutils-gdb.git / blobdiff