+2020-06-02 Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
+ Jim Wilson <jimw@sifive.com>
+
+ PR 26051
+ * doc/c-riscv.texi (RISC-V-Formats): Add missing I format using
+ simm12(rs1). Correct S format to use simm12(rs1). Drop SB and B
+ formats using simm12(rs1). Correct SB and B to use rs1 and rs2.
+ Move B before SB. Move J before UJ.
+
+2020-06-01 Alex Coplan <alex.coplan@arm.com>
+
+ * write.c (relax_segment): Fix handling of negative offset when
+ relaxing an rs_org frag.
+ * testsuite/gas/aarch64/org-neg.d: New test.
+ * testsuite/gas/aarch64/org-neg.l: Error output for test.
+ * testsuite/gas/aarch64/org-neg.s: Input for test.
+ * testsuite/gas/arm/org-neg.d: New test.
+ * testsuite/gas/arm/org-neg.l: Error output for test.
+ * testsuite/gas/arm/org-neg.s: Input for test.
+
+2020-05-28 Stephen Casner <casner@acm.org>
+
+ Fix unexpected failures in gas testsuite for pdp11-aout target.
+ These are caused by the PDP11's mix of little-endian octets in
+ shorts but shorts in big endian order for long or quad.
+
+ * config/tc-pdp11.c (md_number_to_chars): Implement .quad
+ * testsuite/gas/all/gas.exp: Select alternate test scripts for
+ pdp11, skip octa test completely.
+ * testsuite/gas/all/eqv-dot-pdp11.s: Identical to eqv-dot.s
+ * testsuite/gas/all/eqv-dot-pdp11.d: Match different octet order.
+ * testsuite/gas/all/cond-pdp11.l: Match different octet order.
+
+2020-05-28 Alex Coplan <alex.coplan@arm.com>
+
+ * frags.c (frag_grow): Fix comment.
+
+2020-05-27 Stephen Casner <casner@acm.org>
+
+ PR gas/26001
+ * config/tc-pdp11.c (parse_reg): Distinguish register names from
+ symbols that begin with a register name.
+ * testsuite/gas/pdp11/pdp11.exp: Add test of such symbols.
+ * testsuite/gas/pdp11/pr26001.s: Likewise.
+ * testsuite/gas/pdp11/pr26001.d: Likewise.
+
+2020-05-27 Simon Cook <simon.cook@embecosm.com>
+
+ * config/tc-riscv.c (riscv_init_csr_hash): NULL initilize next
+ pointer when creating struct riscv_csr_extra.
+
+2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ * testsuite/gas/i386/align-branch-9.d: Updated for PECOFF.
+ * testsuite/gas/i386/inval-avx512f.s: Add .p2align for PECOFF.
+ * testsuite/gas/i386/inval-avx512f.l: Updated.
+
+2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+
+ * testsuite/gas/s390/zarch-z13.d: Add regexp checks for vector
+ load/store instruction variants with alignment hints.
+ * testsuite/gas/s390/zarch-z13.s: Emit new vector load/store
+ instruction variants with alignment hints.
+
+2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26044
+ * config/tc-xgate.c (md_apply_fix): Check BFD_RELOC_XGATE_PCREL_X
+ instead of R_XGATE_PCREL_X.
+ (xgate_parse_operand): Replace R_XGATE_PCREL_X with
+ BFD_RELOC_XGATE_PCREL_X.
+
+2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26044
+ * config/tc-visium.c (md_convert_frag): Replace fragP->fr_literal
+ with &fragP->fr_literal[0].
+
+2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26044
+ * config/tc-vax.c (md_estimate_size_before_relax): Replace
+ fragP->fr_literal with &fragP->fr_literal[0].
+ (md_convert_frag): Likewise.
+
+2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26044
+ * config/tc-v850.c (md_convert_frag): Replace fragP->fr_literal
+ with &fragP->fr_literal[0].
+
+2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26044
+ * config/tc-crx.c (getreg_image): Change argument type to int.
+ (md_convert_frag): Replace fragP->fr_literal with
+ &fragP->fr_literal[0].
+
+2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26044
+ * onfig/tc-score.c (s3_do_macro_bcmp): Replace overlapping
+ sprintf with memmove.
+
+2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-mcore.c (md_convert_frag): Replace fragP->fr_literal
+ with &fragP->fr_literal[0].
+
+2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26041
+ * config/tc-cr16.c (md_assemble): Use memmove to concatenate
+ 2 overlapping strings.
+
+2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-cr16.c (md_convert_frag): Replace fragP->fr_literal
+ with &fragP->fr_literal[0].
+
+2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-csky.c (md_convert_frag): Replace fragp->fr_literal
+ with &fragp->fr_literal[0].
+ * config/tc-microblaze.c (md_apply_fix): Likewise.
+ * config/tc-sh.c (md_convert_frag): Likewise.
+
+2020-05-24 Jim Wilson <jimw@sifive.com>
+
+ PR 26025
+ * config/tc-riscv.c (riscv_pre_output_hook): Change s type from const
+ asection to segT. New locals seg and subseg. Call subseg_set before
+ fix_new_exp. Call subseg_set after loop to restore original values.
+
+2020-05-21 Alan Modra <amodra@gmail.com>
+
+ * atof-generic.c: Replace "if (x) free (x)" with "free (x)"
+ throughout.
+ * config/obj-elf.c: Likewise.
+ * config/tc-aarch64.c: Likewise.
+ * config/tc-arm.c: Likewise.
+ * config/tc-m68k.c: Likewise.
+ * config/tc-nios2.c: Likewise.
+ * config/tc-tic30.c: Likewise.
+ * ecoff.c: Likewise.
+ * read.c: Likewise.
+ * stabs.c: Likewise.
+ * symbols.c: Likewise.
+ * testsuite/gas/all/test-gen.c: Likewise.
+
2020-05-20 Nelson Chu <nelson.chu@sifive.com>
* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
projects / deliverable / binutils-gdb.git / blobdiff