Make power8 the default cpu when assembling for 64-bit little endian targets.

[deliverable/binutils-gdb.git] / gas / ChangeLog

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 1e0ebb2304d337d72455c3130b2ec129f2c4623c..d0f047e3358223883156292209284ff0d20be93e 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,113 @@
+2018-03-30  Peter Bergner <bergner@vnet.ibm.com>
+
+       PR binutils/23013
+       * config/tc-ppc.c (ppc_set_cpu): Select appropriate cpu when ppc_obj64
+       and little endian.
+
+2018-03-28  Renlin Li  <renlin.li@arm.com>
+
+       PR ld/22970
+       * config/tc-aarch64.c (reloc_table): Update entry for tprel_lo12 and
+       tprel_lo12_nc with pseudo relocations.
+       (ldst_lo12_determine_real_reloc_type): Add new relocations support.
+       (parse_operands): Handle BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12 and
+       BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC pseudo relocations.
+       (md_apply_fix): Add handling for new relocation.
+       (aarch64_force_relocation): Likewise.
+       * testsuite/gas/aarch64/reloc-tprel_lo12-ldst16.d: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12-ldst16.s: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12-ldst32.d: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12-ldst32.s: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12-ldst64.d: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12-ldst64.s: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12-ldst8.d: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12-ldst8.s: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst16.d: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst16.s: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst32.d: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst32.s: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst64.d: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst64.s: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst8.d: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst8.s: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12-ldst16-ilp32.d: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12-ldst32-ilp32.d: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12-ldst64-ilp32.d: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12-ldst8-ilp32.d: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst16-ilp32.d: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst32-ilp32.d: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst64-ilp32.d: New.
+       * testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst8-ilp32.d: New.
+
+2018-03-28  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (check_VecOperands): Replace uses of
+       .vecesize. Always initialize op.
+       * testsuite/gas/i386/avx512_vpopcntdq.s,
+       testsuite/gas/i386/avx512bitalg_vl.s: Add Intel syntax vpopcnt
+       broadcast cases with explicit operand size.
+       * testsuite/gas/i386/avx512_vpopcntdq.d,
+       testsuite/gas/i386/avx512_vpopcntdq-intel.d,
+       testsuite/gas/i386/avx512bitalg_vl.d
+       testsuite/gas/i386/avx512bitalg_vl-intel.d: Adjust expectations.
+
+2018-03-28  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (struct Broadcast_Operation): Adjust comment.
+       (check_VecOperands): Re-write broadcast validation code.
+       (check_VecOperations): Replace BROADCAST_1TO* uses.
+       * testsuite/gas/i386/inval-avx512f.s: Add various broadcast
+       cases.
+       * testsuite/gas/i386/inval-avx512f.l: Adjust expectations.
+
+2018-03-28  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (process_suffix): Check .todword/.toqword
+       before zapping suffix.
+
+2018-03-28  Jan Beulich  <jbeulich@suse.com>
+
+       * testsuite/gas/i386/ilp32/x86-64-simd-suffix.d,
+       testsuite/gas/i386/x86-64-simd-suffix.d: Drop q suffix from
+       cvt*2si.
+
+2018-03-28  Nick Clifton  <nickc@redhat.com>
+
+       PR 22988
+       * config/tc-aarch64.c (parse_operands): Add code to handle
+       AARCH64_OPN_SVE_ADDR_R.
+       * testsuite/gas/aarch64/sve.s: Add tests for LDFF1xx instructions
+       with an assumed XZR offset address register.
+       * testsuite/gas/aarch64/sve.d: Update expected disassembly.
+
+2018-03-22  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (check_VecOperands): Latch
+       i.broadcast->operand into op.
+
+2018-03-22  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (match_template): Special case base opcode
+       0xa0 with HLE prefix.
+       * testsuite/gas/i386/hle.s: Add mov-accumulator-to-disp cases.
+       * testsuite/gas/i386/hle.d, testsuite/gas/i386/hle-intel.d:
+       Adjust expectations.
+
+2018-03-22  Jan Beulich  <jbeulich@suse.com>
+
+       * testsuite/gas/i386/opts.s: Add bndmov cases.
+       * testsuite/gas/i386/opts.d, testsuite/gas/i386/opts-intel.d,
+       testsuite/gas/i386/sse2avx-opts.d,
+       testsuite/gas/i386/sse2avx-opts-intel.d: Adjust expectations.
+
+2018-03-22  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (match_mem_size): Extend sub-xmmword
+       exceptions.
+       * testsuite/gas/i386/xmmword.l, testsuite/gas/i386/xmmword.s:
+       New.
+       * testsuite/gas/i386/i386.exp: Run new test.
+
 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 
        * config/tc-i386.c (match_template): Also match 2nd and 4th