Add 2.30 branch notes to ChangeLogs and NEWS files.
[deliverable/binutils-gdb.git] / gas / ChangeLog
index d8d4a28083dc00c28bb1e323d37bc8c1f066e6a9..f442950c13202bce92952ad0bcd63a2d72b3278b 100644 (file)
@@ -1,3 +1,224 @@
+2018-06-24  Nick Clifton  <nickc@redhat.com>
+
+       2.31 branch created.
+       * NEWS: Add marker for 2.31.
+
+2018-06-22  Tamar Christina  <tamar.christina@arm.com>
+
+       * testsuite/gas/aarch64/addsub.s: Add negs to zero reg test.
+       * testsuite/gas/aarch64/addsub.d: Likewise.
+
+2018-06-21  Alan Modra  <amodra@gmail.com>
+
+       * doc/Makefile.am (AUTOMAKE_OPTIONS): Add "foreign".
+       * doc/Makefile.in: Regenerate.
+
+2018-06-20  Nick Clifton  <nickc@redhat.com>
+
+       PR 21458
+       * tc-arm.c (do_adr): Only set the bottom bit of an imported thumb
+       function symbol address if -mthumb-interwork is active.
+       (do_adrl): Likewise.
+       * doc/c-arm.texi: Update descriptions of the -mthumb-interwork
+       option and the ADR and ADRL pseudo-ops.
+       * NEWS: Mention the new behaviour of the ADR and ADRL pseudo-ops.
+       * testsuite/gas/arm/pr21458.d: Add -mthumb-interwork option to
+       assembler command line.
+       * testsuite/gas/arm/adr.d: Likewise.
+       * testsuite/gas/arm/adrl.d: Likewise.
+
+2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
+
+       PR gas/23305
+       * config/tc-riscv.c (riscv_ip): Add format specifier 'B' for
+       constants and symbols.
+       * testsuite/gas/riscv/lla32.d: New file.
+       * testsuite/gas/riscv/lla32.s: Likewise.
+       * testsuite/gas/riscv/lla64-fail.d: Likewise.
+       * testsuite/gas/riscv/lla64-fail.l: Likewise.
+       * testsuite/gas/riscv/lla64-fail.s: Likewise.
+       * testsuite/gas/riscv/lla64.d: Likewise.
+       * testsuite/gas/riscv/lla64.s: Likewise.
+
+2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
+
+       * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11, add subdir-objects.
+       (TARG_CPU_O, OBJ_FORMAT_O, ATOF_TARG_O): Add config/ prefix.
+       * configure.ac (TARG_CPU_O, OBJ_FORMAT_O, ATOF_TARG_O, emfiles,
+       extra_objects): Add config/ prefix.
+       * doc/as.texinfo: Rename to...
+       * doc/as.texi: ... this.
+       * doc/Makefile.am: Rename as.texinfo to as.texi throughout.
+       Remove DISTCLEANFILES hack.
+       (AUTOMAKE_OPTIONS): Remove 1.8, cygnus, add no-texinfo.tex and
+       info-in-builddir.
+       * Makefile.in: Re-generate.
+       * aclocal.m4: Re-generate.
+       * config.in: Re-generate.
+       * configure: Re-generate.
+       * doc/Makefile.in: Re-generate.
+
+2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
+
+       * NEWS: Mention MIPS Global INValidate ASE support.
+       * config/tc-mips.c (options): Add OPTION_GINV and OPTION_NO_GINV.
+       (md_longopts): Likewise.
+       (mips_ases): Define availability for GINV.
+       (mips_convert_ase_flags): Map ASE_GINV to AFL_ASE_GINV.
+       (md_show_usage): Add help for -mginv and -mno-ginv.
+       * doc/as.texinfo: Document -mginv, -mno-ginv.
+       * doc/c-mips.texi: Document -mginv, -mno-ginv, .set ginv and
+       .set noginv.
+       * testsuite/gas/mips/ase-errors-1.s: Add error checks for GINV
+       ASE.
+       * testsuite/gas/mips/ase-errors-2.s: Likewise.
+       * testsuite/gas/mips/ase-errors-1.l: Likewise.
+       * testsuite/gas/mips/ase-errors-2.l: Likewise.
+       * testsuite/gas/mips/ginv.d: New test.
+       * testsuite/gas/mips/ginv-err.d: New test.
+       * testsuite/gas/mips/ginv-err.l: New test stderr output.
+       * testsuite/gas/mips/ginv.s: New test source.
+       * testsuite/gas/mips/ginv-err.s: New test source.
+       * testsuite/gas/mips/mips.exp: Run the new tests.
+
+2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
+           Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
+           Maciej W. Rozycki  <macro@mips.com>
+
+       * NEWS: Mention CRC ASE support.
+       * config/tc-mips.c (options): Add OPTION_CRC and OPTION_NO_CRC.
+       (md_longopts): Likewise.
+       (md_show_usage): Add help for -mcrc and -mno-crc.
+       (mips_ases): Define availability for CRC and CRC64.
+       (mips_convert_ase_flags): Map ASE_CRC to AFL_ASE_CRC.
+       * doc/as.texinfo: Document -mcrc, -mno-crc.
+       * doc/c-mips.texi: Document -mcrc, -mno-crc, .set crc and
+       .set no-crc.
+       * testsuite/gas/mips/ase-errors-1.l: Add error checks for CRC
+       ASE.
+       * testsuite/gas/mips/ase-errors-2.l: Likewise.
+       * testsuite/gas/mips/ase-errors-1.s: Likewise.
+       * testsuite/gas/mips/ase-errors-2.s: Likewise.
+       * testsuite/gas/mips/crc.d: New test.
+       * testsuite/gas/mips/crc64.d: New test.
+       * testsuite/gas/mips/crc-err.d: New test.
+       * testsuite/gas/mips/crc64-err.d: New test.
+       * testsuite/gas/mips/crc-err.l: New test stderr output.
+       * testsuite/gas/mips/crc64-err.l: New test stderr output.
+       * testsuite/gas/mips/crc.s: New test source.
+       * testsuite/gas/mips/crc64.s: New test source.
+       * testsuite/gas/mips/crc-err.s: New test source.
+       * testsuite/gas/mips/crc64-err.s: New test source.
+       * testsuite/gas/mips/mips.exp: Run the new tests.
+
+2018-06-11  Maciej W. Rozycki  <macro@mips.com>
+
+       * config/tc-mips.c (md_show_usage): Correct help text for `-O0'
+       and `-O'.  Mention `-O1'.  Add `-O2' and its description.
+
+2018-06-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/tc-arm.c (arm_cpus): Add Cortex-A76 entry.
+       * doc/c-arm.texi (-mcpu): Document cortex-a76.
+
+2018-06-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/tc-aarch64.c (aarch64_cpus): Add Cortex-A76 entry.
+       * doc/c-aarch64.texi (-mcpu): Document cortex-a76.
+
+2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
+
+       PR 20319
+       * testsuite/gas/aarch64/illegal-3.s: Test if unallocated FMOV encodings
+       are detected as undefined.
+       * testsuite/gas/aarch64/illegal-3.d: Likewise.
+       * testsuite/gas/aarch64/illegal.s: Test if FMOV instructions that are
+       changing the size from 32 bits to 64 bits and vice versa trigger an
+       error.
+       * testsuite/gas/aarch64/illegal.l: Likewise.
+
+2018-06-08  Tamar Christina  <tamar.christina@arm.com>
+
+       PR binutils/21446
+       * tc-aarch64.c (record_operand_error, record_operand_error_with_data):
+         Initialize non_fatal.
+
+2018-06-06  Sameera Deshpande  <sameera.deshpande@linaro.org>
+
+       * config/tc-aarch64.c (aarch64_cpus): Add support of ARMv8.4 in
+       saphira.
+
+2018-06-05  Alan Modra  <amodra@gmail.com>
+
+       * Makefile.in: Regenerate.
+
+2018-06-04  Volodymyr Arbatov  <arbatov@cadence.com>
+
+       * config/tc-xtensa.c (elf32xtensa_separate_props): New
+       declaration.
+       (option_separate_props, option_no_separate_props): New
+       enumeration constants.
+       (md_longopts): Add separate-prop-tables option.
+       (md_parse_option): Add cases for option_separate_props and
+       option_no_separate_props.
+       (md_show_usage): Add help for [no-]separate-prop-tables options.
+
+2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * configure: Regenerated.
+
+2018-06-01  Alexandre Oliva <aoliva@redhat.com>
+
+       * dwarf2dbg.c (dwarf2_consume_line_info): Drop view.
+
+2018-06-01  Jan Beulich  <jbeulich@suse.com>
+
+       * testsuite/gas/i386/ilp32/x86-64-opcode.d,
+       testsuite/gas/i386/x86-64-opcode.d: Adjust expectations.
+
+2018-06-01  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (add_prefix): Check REX bits individually.
+       * testsuite/gas/i386/rex.s: Add tests for overriding individual
+       REX bits, including when others are already set.
+       * testsuite/gas/i386/ilp32/rex.d, testsuite/gas/i386/rex.d:
+       Adjust expectations.
+
+2018-06-01  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (control): Delete.
+       (parse_real_register): Simply check "control" bit. Re-wrap.
+
+2018-06-01  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (build_modrm_byte): Drop REX_B from condition
+       checking for the need of emitting LOCK. Check "control" bit just
+       once.
+
+2018-06-01  Jan Beulich  <jbeulich@suse.com>
+
+       *  testsuite/gas/i386/invpcid.s,
+       testsuite/gas/i386/x86-64-invpcid.s: Add test with explicit
+       "oword ptr".
+       * testsuite/gas/i386/invpcid.d,
+       testsuite/gas/i386/invpcid-intel.d,
+       testsuite/gas/i386/x86-64-invpcid.d,
+       testsuite/gas/i386/x86-64-invpcid-intel.d: Adjust expectations.
+
+2018-05-30  Amit Pawar  <amit.pawar@amd.com>
+
+       * config/tc-i386.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
+       * doc/c-i386.texi : Document znver2.
+       * gas/testsuite/gas/i386/arch-13.s: Updated for znver2.
+       * gas/testsuite/gas/i386/arch-13.d: Updated.
+       * gas/testsuite/gas/i386/arch-13-znver1.d: Updated.
+       * gas/testsuite/gas/i386/arch-13-znver2.d: New file.
+       * gas/testsuite/gas/i386/x86-64-arch-3.s: Updated for znver2.
+       * gas/testsuite/gas/i386/x86-64-arch-3.d: Updated.
+       * gas/testsuite/gas/i386/x86-64-arch-3-znver1.d: Updated.
+       * gas/testsuite/gas/i386/x86-64-arch-3-znver2.d: New file.
+       * gas/testsuite/gas/i386/i386.exp: Updated for new test.
+
 2018-05-25  Alan Modra  <amodra@gmail.com>
 
        * po/POTFILES.in: Regenerate.
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