+2016-11-13 Anthony Green <green@moxielogic.org>
+
+ * config/tc-moxie.c (md_assemble): Assemble 'bad' opcode.
+
+2016-11-11 Nick Clifton <nickc@redhat.com>
+
+ PR gas/20732
+ * expr.c (integer_constant): If tc_allow_L_suffix is defined and
+ non-zero then accept a L or LL suffix.
+ * testsuite/gas/sparc/pr20732.d: New test source file.
+ * testsuite/gas/sparc/pr20732.d: New test output file.
+ * testsuite/gas/sparc/sparc.exp: Run new test.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * testsuite/gas/aarch64/pac.s: Add ARMv8.3 branch instruction tests.
+ * testsuite/gas/aarch64/pac.d: Likewise.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * config/tc-aarch64.c (process_omitted_operand): Handle AARCH64_OPND_Rm_SP.
+ (parse_operands): Likewise.
+ * testsuite/gas/aarch64/pac.s: Add pacga.
+ * testsuite/gas/aarch64/pac.d: Add pacga.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * testsuite/gas/aarch64/pac.s: New.
+ * testsuite/gas/aarch64/pac.d: New.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * testsuite/gas/aarch64/sysreg-3.s: New.
+ * testsuite/gas/aarch64/sysreg-3.d: New.
+ * testsuite/gas/aarch64/illegal-sysreg-3.l: New.
+ * testsuite/gas/aarch64/illegal-sysreg-3.d: New.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * testsuite/gas/aarch64/system-3.s: New.
+ * testsuite/gas/aarch64/system-3.d: New.
+ * testsuite/gas/aarch64/system.d: Update expected output.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * config/tc-aarch64.c (aarch64_archs): Add "armv8.3-a".
+ * doc/c-aarch64.texi (-march): Likewise.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * config/tc-aarch64.c (aarch64_features): Fix "simd" and "crypto".
+ * testsuite/gas/aarch64/illegal-crypto-nofp.d: New.
+ * testsuite/gas/aarch64/illegal-crypto-nofp.l: New.
+ * testsuite/gas/aarch64/illegal-fp16-nofp.d: New.
+ * testsuite/gas/aarch64/illegal-fp16-nofp.l: New.
+ * testsuite/gas/aarch64/illegal-fp16-nofp.s: New.
+
+2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/20799
+ * testsuite/gas/i386/opcode.s: Add a test for EVEX vpextrw.
+ * testsuite/gas/i386/opcode-intel.d: Updated.
+ * testsuite/gas/i386/opcode-suffix.d: Likewise.
+ * testsuite/gas/i386/opcode.d: Likewise.
+ * testsuite/gas/i386/x86-64-avx512bw-opts.s: Remove vpextrw
+ tests.
+ * testsuite/gas/i386/x86-64-avx512bw-opts-intel.d: Updated.
+ * testsuite/gas/i386/x86-64-avx512bw-opts.d: Likewise.
+
+2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/20754
+ * testsuite/gas/i386/opcode-suffix.d: Updated.
+
+2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/20775
+ * testsuite/gas/i386/i386.exp: Run fpu-bad.
+ * testsuite/gas/i386/fpu-bad.d: New file.
+ * testsuite/gas/i386/fpu-bad.s: Likewise.
+
+2016-11-04 Nathan Sidwell <nathan@acm.org>
+
+ gas/
+ * input-scrub.c (partial_size): Make size_t.
+ (buffer_length): Likewise. Adjust meaning.
+ (struct input_save): Adjust partial_size type.
+ (input_scrub_reinit): New.
+ (input_scrub_push, input_scrub_begin): Use it.
+ (input_scrub_next_buffer): Fix buffer extension logic. Only scan
+ newly read buffer for newline.
+
+2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * config/tc-arc.c (find_opcode_match): Use insert function to
+ validate matching address type operands.
+ * testsuite/gas/arc/nps400-10.d: New file.
+ * testsuite/gas/arc/nps400-10.s: New file.
+
+2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (cortex-m33): Declare new processor.
+ * doc/c-arm.texi (-mcpu ARM command line option): Document new
+ Cortex-M33 processor.
+ * NEWS: Mention ARM Cortex-M33 support.
+
+2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (cortex-m23): Declare new processor.
+ * doc/c-arm.texi (-mcpu ARM command line option): Document new
+ Cortex-M23 processor.
+ * NEWS: Mention ARM Cortex-M23 support.
+
+2016-11-04 Palmer Dabbelt <palmer@dabbelt.com>
+ Andrew Waterman <andrew@sifive.com>
+
+ * Makefile.am (CPU_DOCS): Add c-riscv.texi.
+ * Makefile.in: Regenerate.
+ * doc/all.texi: Set RISCV.
+ * doc/as.texinfo: Add RISCV options.
+ Add RISC-V-Dependent node.
+ Include c-riscv.texi.
+ * doc/c-riscv.texi: Rename RISC-V Options to RISC-V-Opts.
+
+2016-11-03 Graham Markall <graham.markall@embecosm.com>
+
+ * testsuite/gas/arc/nps400-6.s: Change ldbit tests so that limm
+ operands are out of the range of an s9, in order to fix the test.
+ * testsuite/gas/arc/nps400-6.d: Updated to match new expected output.
+
+2016-11-03 Graham Markall <graham.markall@embecosm.com>
+
+ * testsuite/gas/arc/nps-400-9.d: Added.
+ * testsuite/gas/arc/nps-400-9.s: Added.
+
+2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * config/tc-arc.c (struct arc_insn): Change type of insn field.
+ (md_number_to_chars_midend): Support 6- and 8-byte values.
+ (emit_insn0): Update debug output.
+ (find_opcode_match): Likewise.
+ (build_fake_opcode_hash_entry): Delete.
+ (find_special_case_long_opcode): Delete.
+ (find_special_case): Remove long format special case handling.
+ (insert_operand): Change instruction type and update debug print
+ format.
+ (assemble_insn): Change instruction type, update debug print
+ formats, and remove unneeded assert.
+
2016-11-03 Graham Markall <graham.markall@embecosm.com>
* config/tc-arc.c (assemble_insn): Replace use of ARC_SHORT with