+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (match_mem_size): Generalize broadcast special
+ casing.
+ (check_VecOperands): Zap xmmword/ymmword/zmmword when more than
+ one of byte/word/dword/qword is set alongside a SIMD register in
+ a template's operand.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (match_template): Extend code in logic
+ rejecting certain suffixes in certain modes to also cover mask
+ register use and VecSIB. Drop special casing of broadcast. Skip
+ immediates in the check.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (match_template): Fold duplicate code in
+ logic rejecting certain suffixes in certain modes. Drop
+ pointless "else".
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (process_suffix): Exlucde !vexw insns
+ alongside !norex64 ones.
+ * testsuite/gas/i386/x86-64-avx512bw.s: Test VPEXTR* and VPINSR*
+ with both 32- and 64-bit GPR operands.
+ * testsuite/gas/i386/x86-64-avx512f.s: Test VEXTRACTPS with both
+ 32- and 64-bit GPR operands.
+ * testsuite/gas/i386/x86-64-avx512bw-intel.d,
+ testsuite/gas/i386/x86-64-avx512bw.d,
+ testsuite/gas/i386/x86-64-avx512f-intel.d,
+ testsuite/gas/i386/x86-64-avx512f.d: Adjust expectations.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (md_assemble): Drop use of rex64.
+ (process_suffix): For REX.W for 64-bit CRC32.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (i386_addressing_mode): For 32-bit
+ addressing for MPX insns without base/index.
+ * testsuite/gas/i386/mpx-16bit.s,
+ * testsuite/gas/i386/mpx-16bit.d: New.
+ * testsuite/gas/i386/i386.exp: Run new test.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/adx.s, testsuite/gas/i386/cet.s,
+ testsuite/gas/i386/ept.s, testsuite/gas/i386/fsgs.s,
+ testsuite/gas/i386/invpcid.s, testsuite/gas/i386/movdir.s,
+ testsuite/gas/i386/ptwrite.s, testsuite/gas/i386/vmx.s,
+ * testsuite/gas/i386/code16.s: Add CR, DR, and TR access cases
+ as well as a BSWAP one.
+ * testsuite/gas/i386/rdpid.s: Add 16-bit case.
+ * testsuite/gas/i386/sse2-16bit.s: Cover more insns.
+ * testsuite/gas/i386/adx-intel.d, testsuite/gas/i386/adx.d,
+ testsuite/gas/i386/cet-intel.d, testsuite/gas/i386/cet.d,
+ testsuite/gas/i386/code16.d, testsuite/gas/i386/ept-intel.d,
+ testsuite/gas/i386/ept.d, testsuite/gas/i386/fsgs-intel.d,
+ testsuite/gas/i386/fsgs.d, testsuite/gas/i386/invpcid-intel.d,
+ testsuite/gas/i386/invpcid.d, testsuite/gas/i386/movdir-intel.d,
+ testsuite/gas/i386/movdir.d, testsuite/gas/i386/ptwrite-intel.d,
+ testsuite/gas/i386/ptwrite.d, testsuite/gas/i386/rdpid-intel.d,
+ testsuite/gas/i386/rdpid.d, testsuite/gas/i386/sse2-16bit.d,
+ testsuite/gas/i386/vmx.d: Adjust expectations.
+
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (md_assemble): Also exclude tpause and umwait
+ from having their operands swapped.
+ * testsuite/gas/i386/waitpkg.s,
+ testsuite/gas/i386/x86-64-waitpkg.s: Add tpause and umwait
+ 3-operand cases as well as testing of 16-bit code generation.
+ * testsuite/gas/i386/waitpkg.d,
+ testsuite/gas/i386/waitpkg-intel.d,
+ testsuite/gas/i386/x86-64-waitpkg.d,
+ testsuite/gas/i386/x86-64-waitpkg-intel.d: Adjust expectations.
+
+2020-03-04 Nelson Chu <nelson.chu@sifive.com>
+
+ * config/tc-riscv.c (percent_op_utype): Support the modifier
+ %got_pcrel_hi.
+ * doc/c-riscv.texi: Add documentation.
+ * testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new
+ modifier %got_pcrel_hi.
+ * testsuite/gas/riscv/no-relax-reloc.s: Likewise.
+ * testsuite/gas/riscv/relax-reloc.d: Likewise.
+ * testsuite/gas/riscv/relax-reloc.s: Likewise.
+
+ * doc/c-riscv.texi (relocation modifiers): Add documentation.
+ (RISC-V-Formats): Update the section name from "Instruction Formats"
+ to "RISC-V Instruction Formats".
+
+2020-03-04 Alexandre Oliva <oliva@adacore.com>
+
+ * config/tc-arm.c (md_apply_fix): Warn if a PC-relative load is
+ detected in a section which does not have at least 4 byte
+ alignment.
+ * testsuite/gas/arm/armv8-ar-it-bad.s: Add alignment directive.
+ * testsuite/gas/arm/ldr-t.s: Likewise.
+ * testsuite/gas/arm/sp-pc-usage-t.s: Likewise.
+ * testsuite/gas/arm/sp-pc-usage-t.d: Finish test at end of
+ disassembly, ignoring any NOPs that may have been inserted because
+ of section alignment.
+ * testsuite/gas/arm/ldr-t.d: Likewise.
+
+2020-03-04 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (cpu_arch): Add .sev_es entry.
+ * doc/c-i386.texi: Mention sev_es.
+ * testsuite/gas/i386/arch-13.s: Add SEV-ES case.
+ * testsuite/gas/i386/arch-13.d: Extend -march=. Adjust
+ expectations.
+ * testsuite/gas/i386/arch-13-znver1.d,
+ testsuite/gas/i386/arch-13-znver2.d: Extend -march=.
+
+2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (match_template): Replace ignoresize and
+ defaultsize with mnemonicsize.
+ (process_suffix): Likewise.
+
+2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
+
+ PR 25627
+ * config/tc-z80.c (emit_ld_rr_m): Fix invalid compilation of
+ instruction LD IY,(HL).
+ * testsuite/gas/z80/ez80_adl_all.d: Update expected disassembly.
+ * testsuite/gas/z80/ez80_adl_all.s: Add tests of the instruction.
+ * testsuite/gas/z80/ez80_z80_all.d: Update expected disassembly.
+ * testsuite/gas/z80/ez80_z80_all.s: Add tests of the instruction.
+
+2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25622
+ * testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
+ x86-64-default-suffix-avx.
+ * testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
+ vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
+ * testsuite/gas/i386/noreg64.d: Updated.
+ * testsuite/gas/i386/noreg64.l: Likewise.
+ * testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
+ * testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
+ * testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
+
2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25604
projects / deliverable / binutils-gdb.git / blobdiff