x86: reduce amount of various VCVT* templates

[deliverable/binutils-gdb.git] / gas / ChangeLog

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 859f01fae7915fdf1bc21f4d504ec5ccd088f06d..f81ec12b9daafef718e8d3dbc5b71c9c28c6952c 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,83 @@
+2020-03-06  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (match_mem_size): Generalize broadcast special
+       casing.
+       (check_VecOperands): Zap xmmword/ymmword/zmmword when more than
+       one of byte/word/dword/qword is set alongside a SIMD register in
+       a template's operand.
+
+2020-03-06  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (match_template): Extend code in logic
+       rejecting certain suffixes in certain modes to also cover mask
+       register use and VecSIB. Drop special casing of broadcast. Skip
+       immediates in the check.
+
+2020-03-06  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (match_template): Fold duplicate code in
+       logic rejecting certain suffixes in certain modes. Drop
+       pointless "else".
+
+2020-03-06  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (process_suffix): Exlucde !vexw insns
+       alongside !norex64 ones.
+       * testsuite/gas/i386/x86-64-avx512bw.s: Test VPEXTR* and VPINSR*
+       with both 32- and 64-bit GPR operands.
+       * testsuite/gas/i386/x86-64-avx512f.s: Test VEXTRACTPS with both
+       32- and 64-bit GPR operands.
+       * testsuite/gas/i386/x86-64-avx512bw-intel.d,
+       testsuite/gas/i386/x86-64-avx512bw.d,
+       testsuite/gas/i386/x86-64-avx512f-intel.d,
+       testsuite/gas/i386/x86-64-avx512f.d: Adjust expectations.
+
+2020-03-06  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (md_assemble): Drop use of rex64.
+       (process_suffix): For REX.W for 64-bit CRC32.
+
+2020-03-06  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (i386_addressing_mode): For 32-bit
+       addressing for MPX insns without base/index.
+       * testsuite/gas/i386/mpx-16bit.s,
+       * testsuite/gas/i386/mpx-16bit.d: New.
+       * testsuite/gas/i386/i386.exp: Run new test.
+
+2020-03-06  Jan Beulich  <jbeulich@suse.com>
+
+       * testsuite/gas/i386/adx.s, testsuite/gas/i386/cet.s,
+       testsuite/gas/i386/ept.s, testsuite/gas/i386/fsgs.s,
+       testsuite/gas/i386/invpcid.s, testsuite/gas/i386/movdir.s,
+       testsuite/gas/i386/ptwrite.s, testsuite/gas/i386/vmx.s,
+       * testsuite/gas/i386/code16.s: Add CR, DR, and TR access cases
+       as well as a BSWAP one.
+       * testsuite/gas/i386/rdpid.s: Add 16-bit case.
+       * testsuite/gas/i386/sse2-16bit.s: Cover more insns.
+       * testsuite/gas/i386/adx-intel.d, testsuite/gas/i386/adx.d,
+       testsuite/gas/i386/cet-intel.d, testsuite/gas/i386/cet.d,
+       testsuite/gas/i386/code16.d, testsuite/gas/i386/ept-intel.d,
+       testsuite/gas/i386/ept.d, testsuite/gas/i386/fsgs-intel.d,
+       testsuite/gas/i386/fsgs.d, testsuite/gas/i386/invpcid-intel.d,
+       testsuite/gas/i386/invpcid.d, testsuite/gas/i386/movdir-intel.d,
+       testsuite/gas/i386/movdir.d, testsuite/gas/i386/ptwrite-intel.d,
+       testsuite/gas/i386/ptwrite.d, testsuite/gas/i386/rdpid-intel.d,
+       testsuite/gas/i386/rdpid.d, testsuite/gas/i386/sse2-16bit.d,
+       testsuite/gas/i386/vmx.d: Adjust expectations.
+
+2020-03-06  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (md_assemble): Also exclude tpause and umwait
+       from having their operands swapped.
+       * testsuite/gas/i386/waitpkg.s,
+       testsuite/gas/i386/x86-64-waitpkg.s: Add tpause and umwait
+       3-operand cases as well as testing of 16-bit code generation.
+       * testsuite/gas/i386/waitpkg.d,
+       testsuite/gas/i386/waitpkg-intel.d,
+       testsuite/gas/i386/x86-64-waitpkg.d,
+       testsuite/gas/i386/x86-64-waitpkg-intel.d: Adjust expectations.
+
 2020-03-04  Nelson Chu  <nelson.chu@sifive.com>
 
        * config/tc-riscv.c (percent_op_utype): Support the modifier