+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-mips.c (mips16_ip): Handle `.e' and `.t' instruction
+ suffixes followed by a null character rather than a space too.
+ * testsuite/gas/mips/mips16-insn-length-noargs.d: New test.
+ * testsuite/gas/mips/mips16-insn-length-noargs.s: New test
+ source.
+ * testsuite/gas/mips/mips.exp: Run the new test.
+
+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips16-extend-swap.d: New test.
+ * testsuite/gas/mips/mips16-extend-swap.s: New test source.
+ * testsuite/gas/mips/mips.exp: Run the new test.
+
+2016-12-23 Joe Seymour <joe.s@somniumtech.com>
+
+ * config/tc-msp430.c (msp430_mcu_data): Sync with data from TI's
+ devices.csv file as of September 2016.
+
+2016-12-23 Tristan Gingold <gingold@adacore.com>
+
+ * configure: Regenerate.
+
+2016-12-23 Tristan Gingold <gingold@adacore.com>
+
+ * NEWS: Add marker for 2.28.
+
+2016-12-23 Tristan Gingold <gingold@adacore.com>
+
+ * po/gas.pot: Regenerate.
+
+2016-12-21 Andrew Waterman <andrew@sifive.com>
+
+ * config/tc-riscv.c (riscv_make_nops): Emit 2-byte NOPs.
+ (riscv_frag_align_code): Correct frag_align_code arg.
+
+2016-12-21 Tim Newsome <tim@sifive.com>
+
+ * config/tc-riscv.c (riscv_pre_output_hook): Remove const from
+ loc4_frag.
+
+2016-12-21 Alan Modra <amodra@gmail.com>
+
+ * doc/c-lm32.texi: Fix chars with high bit set.
+ * testsuite/gas/bfin/vector2.s: Likewise.
+
+2016-12-21 Alan Modra <amodra@gmail.com>
+
+ PR gas/10946
+ * doc/as.texinfo (Chars): Document escape sequences.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips16-sub.d: New test.
+ * testsuite/gas/mips/mips16-32@mips16-sub.d: New test.
+ * testsuite/gas/mips/mips16e-32@mips16-sub.d: New test.
+ * testsuite/gas/mips/mips16e-sub.d: New test.
+ * testsuite/gas/mips/mips16-32@mips16e-sub.d: New test.
+ * testsuite/gas/mips/mips16-64@mips16e-sub.d: New test.
+ * testsuite/gas/mips/mips16e-64-sub.d: New test.
+ * testsuite/gas/mips/mips16-32@mips16e-64-sub.d: New test.
+ * testsuite/gas/mips/mips16-64@mips16e-64-sub.d: New test.
+ * testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: New test.
+ * testsuite/gas/mips/mips16-sub.s: New test source.
+ * testsuite/gas/mips/mips16e-sub.s: New test source.
+ * testsuite/gas/mips/mips16e-64-sub.s: New test source.
+ * testsuite/gas/mips/mips.exp: Run the new tests.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips16e.s: Add a RESTORE instruction.
+ * testsuite/gas/mips/mips16e.d: Adjust accordingly.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips16.d: Adjust test for multiple MIPS16
+ ISA testing.
+ * testsuite/gas/mips/mips16-64.d: Adjust test for multiple
+ MIPS16 ISA testing.
+ * testsuite/gas/mips/mips16e-64.d: Adjust test for multiple
+ MIPS16 ISA testing.
+ * testsuite/gas/mips/mips16-macro.d: Adjust test for multiple
+ MIPS16 ISA testing.
+ * testsuite/gas/mips/mips16e-64.s: Ensure MIPS16 ISA annotation.
+ * testsuite/gas/mips/mips16e-64.l: Rename to...
+ * testsuite/gas/mips/mips16e-32@mips16e-64.l: ... this.
+ * testsuite/gas/mips/mips16-64@mips16.d: New test.
+ * testsuite/gas/mips/mips16-64@mips16-64.d: New test.
+ * testsuite/gas/mips/mips16e-32@mips16e-64.d: New test.
+ * testsuite/gas/mips/mips16-32@mips16-macro.d: New test.
+ * testsuite/gas/mips/mips16-64@mips16-macro.d: New test.
+ * testsuite/gas/mips/mips16e-32@mips16-macro.d: New test.
+ * testsuite/gas/mips/mips16-32@mips16-macro-e.d: New test.
+ * testsuite/gas/mips/mips16e-32@mips16-macro-e.d: New test.
+ * testsuite/gas/mips/mips16-32@mips16-macro-t.d: New test.
+ * testsuite/gas/mips/mips16e-32@mips16-macro-t.d: New test.
+ * testsuite/gas/mips/mips16e-32@mips16e-64.l: New stderr output.
+ * testsuite/gas/mips/mips16-32@mips16-macro.l: New stderr
+ output.
+ * testsuite/gas/mips/mips16e-32@mips16-macro.l: New stderr
+ output.
+ * testsuite/gas/mips/mips16-32@mips16-macro-e.l: New stderr
+ output.
+ * testsuite/gas/mips/mips16e-32@mips16-macro-e.l: New stderr
+ output.
+ * testsuite/gas/mips/mips16-32@mips16-macro-t.l: New stderr
+ output.
+ * testsuite/gas/mips/mips16e-32@mips16-macro-t.l: New stderr
+ output.
+ * testsuite/gas/mips/mips.exp: Run `mips16', `mips16-64',
+ `mips16-macro', `mips16-macro-t', `mips16-macro-e' and
+ `mips16e-64' testing across multiple MIPS16 ISAs. Fold
+ `mips16-macro' and `mips16e-64' list test invocations into
+ corresponding dump tests.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips.exp (run_dump_test_arch): Add
+ `mips16e' and `mips16' prefixes.
+ (run_list_test_arch): Likewise.
+ Rename `mips16' architecture to `mips16-32'. Add `mips16-64',
+ `mips16e-32' and `mips16e-64' architectures. Update `rol64',
+ `mips16e', `elf${el}-rel2' and `elf-rel4' test invocations
+ accordingly.
+ * testsuite/gas/mips/mips16e@branch-swap-3.d: New test.
+ * testsuite/gas/mips/mips16e@branch-swap-4.d: New test.
+ * testsuite/gas/mips/mips16e@loc-swap-dis.d: New test.
+ * testsuite/gas/mips/mips16e@loc-swap.d: New test.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/loc-swap.s: Use zeros rather than NOPs for
+ trailing alignment padding.
+ * testsuite/gas/mips/loc-swap.d: Adjust accordingly.
+ * testsuite/gas/mips/micromips@loc-swap.d: Likewise.
+ * testsuite/gas/mips/mips16@loc-swap-dis.d: Likewise.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-mips.c (micromips_insn_length): Use
+ `mips_opcode_32bit_p'.
+ (is_size_valid): Adjust description.
+ (is_size_valid_16): New function.
+ (validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16
+ operand decoding.
+ (validate_mips16_insn): Remove `a' and `i' operand code special
+ casing, use `mips_opcode_32bit_p' to determine instruction
+ width.
+ (append_insn): Adjust forced MIPS16 instruction size
+ determination.
+ (match_mips16_insn): Likewise. Don't shift the instruction's
+ opcode with the `a' and `i' operand codes. Use
+ `mips_opcode_32bit_p' in operand decoding.
+ (match_mips16_insns): Check for forced instruction size's
+ validity.
+ (mips16_ip): Don't force instruction size in the `noautoextend'
+ mode.
+ * testsuite/gas/mips/mips16-jal-e.d: New test.
+ * testsuite/gas/mips/mips16-jal-t.d: New test.
+ * testsuite/gas/mips/mips16-macro-e.d: New test.
+ * testsuite/gas/mips/mips16-macro-t.d: New test.
+ * testsuite/gas/mips/mips16-jal-t.l: New stderr output.
+ * testsuite/gas/mips/mips16-macro-e.l: New stderr output.
+ * testsuite/gas/mips/mips16-macro-t.l: New stderr output.
+ * testsuite/gas/mips/mips16-jal-e.s: New test source.
+ * testsuite/gas/mips/mips16-jal-t.s: New test source.
+ * testsuite/gas/mips/mips16-macro-e.s: New test source.
+ * testsuite/gas/mips/mips16-macro-t.s: New test source.
+ * testsuite/gas/mips/mips.exp: Run the new tests.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips16-macro.l: New list test.
+ * testsuite/gas/mips/mips.exp: Run the new test.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips16-sdrasp.d: New test.
+ * testsuite/gas/mips/mips16-sdrasp.l: New stderr output.
+ * testsuite/gas/mips/mips16-sdrasp.s: New test source.
+ * testsuite/gas/mips/mips.exp: Run the new test.
+
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips.exp: Limit remaining tests that
+ require NewABI support to `has_newabi' targets.
+
+2015-12-20 Andrew Waterman <andrew@sifive.com>
+
+ * config/tc-riscv.c (riscv_pseudo_table): Remove "align",
+ "p2align", and "balign".
+ (s_align): Remove.
+ (riscv_handle_align): New function.
+ (riscv_frag_align_code): Likewise.
+ (riscv_make_nops): Likewise.
+ * config/tc-riscv.h (MAX_MEM_FOR_RS_ALIGN_CODE): Change to 7.
+ (HANDLE_ALIGN): Define.
+ (md_do_align): Define.
+ (riscv_handle_align): Declare.
+ (riscv_frag_align_code): Likewise.
+
+2016-12-20 Andrew Waterman <andrew@sifive.com>
+
+ * config/tc-riscv.h (xlen): Delete.
+ * config/tc-riscv.c (xlen): Make static.
+ (abi_xlen): New variable.
+ (options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC}
+ with OPTION_MABI.
+ (md_longopts): Likewise.
+ (md_parse_option): Likewise.
+ (riscv_elf_final_processing): Likewise.
+ * doc/as.texinfo (Target RISC-V options): Likewise.
+ * doc/c-riscv.texi (OPTIONS): Likewise.
+ * config/tc-riscv.c (float_mode): Removed.
+ (float_abi): New type, specifies the floating-point ABI.
+ (riscv_set_abi): New function.
+ (riscv_add_subset): Only allow lower-case ISA names and require
+ them to start with "rv".
+ (riscv_after_parse_args): Likewise.
+
+2016-12-20 Andrew Waterman <andrew@sifive.com>
+ Kuan-Lin Chen <kuanlinchentw@gmail.com>
+
+ * config/tc-riscv.c (riscv_set_options): Add relax.
+ (riscv_opts): Likewise.
+ (s_riscv_option): Add relax and norelax.
+ (riscv_apply_const_reloc): New function.
+ (append_insn): Move constant relocation handling to
+ riscv_apply_const_reloc.
+ (md_pcrel_from): Likewise.
+ (parse_relocation): Skip BFD_RELOC_UNUSED.
+ (md_pcrel_from): Handle BFD_RELOC_RISCV_SUB6,
+ BFD_RELOC_RISCV_RELAX, BFD_RELOC_RISCV_CFA.
+ (md_apply_fix): Likewise.
+ (riscv_pre_output_hook): New function.
+ * config/tc-riscv.h (md_pre_output_hook): Define.
+ (riscv_pre_output_hook): Declare.
+ (DWARF_CIE_DATA_ALIGNMENT): Always -4.
+
+2016-12-20 Andrew Waterman <andrew@sifive.com>
+
+ * config/tc-riscv.c: Formatting and comment fixes throughout.
+
+2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-mips.c (md_convert_frag): Report an error instead of
+ asserting on `ext'.
+ * testsuite/gas/mips/mips16-branch-unextended-1.d: New test.
+ * testsuite/gas/mips/mips16-branch-unextended-2.d: New test.
+ * testsuite/gas/mips/mips16-branch-unextended-1.s: New test
+ source.
+ * testsuite/gas/mips/mips16-branch-unextended-2.s: New test.
+ * testsuite/gas/mips/mips16-branch-unextended.l: New stderr
+ output.
+ * testsuite/gas/mips/mips.exp: Run the new tests.
+
+2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips16-sprel-swap.d: New test.
+ * testsuite/gas/mips/mips16-sprel-swap.s: New test source.
+ * testsuite/gas/mips/mips.exp: Run the new test.
+
+2016-12-13 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-aarch64.c (AARCH64_REG_TYPES): Remove CN register.
+ (get_reg_expected_msg): Remove CN register case.
+ (parse_operands): rewrite parser for CRn, CRm operand.
+ (reg_names): Remove CN register.
+ * testsuite/gas/aarch64/diagnostic.s: Add a new test case.
+ * testsuite/gas/aarch64/diagnostic.l: Adjust error message.
+
+2016-12-13 Jiong Wang <jiong.wang@arm.com>
+
+ * gas/testsuite/gas/aarch64/addsub.d: Support ILP32 mode.
+ * gas/testsuite/gas/aarch64/advsimd-across.d: Likewise.
+ * gas/testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
+ * gas/testsuite/gas/aarch64/advsimd-fp16.d: Likewise.
+ * gas/testsuite/gas/aarch64/advsimd-misc.d: Likewise.
+ * gas/testsuite/gas/aarch64/advsisd-copy.d: Likewise.
+ * gas/testsuite/gas/aarch64/advsisd-misc.d: Likewise.
+ * gas/testsuite/gas/aarch64/alias.d: Likewise.
+ * gas/testsuite/gas/aarch64/armv8-ras-1.d: Likewise.
+ * gas/testsuite/gas/aarch64/b_1.d: Likewise.
+ * gas/testsuite/gas/aarch64/beq_1.d: Likewise.
+ * gas/testsuite/gas/aarch64/bitfield-dump: Likewise.
+ * gas/testsuite/gas/aarch64/bitfield-no-aliases.d: Likewise.
+ * gas/testsuite/gas/aarch64/codealign.d: Likewise.
+ * gas/testsuite/gas/aarch64/codealign_1.d: Likewise.
+ * gas/testsuite/gas/aarch64/crc32-directive.d: Likewise.
+ * gas/testsuite/gas/aarch64/crc32.d: Likewise.
+ * gas/testsuite/gas/aarch64/crypto-directive.d: Likewise.
+ * gas/testsuite/gas/aarch64/crypto.d: Likewise.
+ * gas/testsuite/gas/aarch64/dwarf.d: Likewise.
+ * gas/testsuite/gas/aarch64/float-fp16.d: Likewise.
+ * gas/testsuite/gas/aarch64/floatdp2.d: Likewise.
+ * gas/testsuite/gas/aarch64/fp-armv8_3.d: Likewise.
+ * gas/testsuite/gas/aarch64/fp-const0-parse.d: Likewise.
+ * gas/testsuite/gas/aarch64/fp_cvt_int.d: Likewise.
+ * gas/testsuite/gas/aarch64/fpmov.d: Likewise.
+ * gas/testsuite/gas/aarch64/inst-directive.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldr_1.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldst-exclusive.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldst-reg-pair.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldst-reg-uns-imm.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.d: Likewise.
+ * gas/testsuite/gas/aarch64/lor-directive.d: Likewise.
+ * gas/testsuite/gas/aarch64/lor.d: Likewise.
+ * gas/testsuite/gas/aarch64/lse-atomic.d: Likewise.
+ * gas/testsuite/gas/aarch64/mapmisc.d: Likewise.
+ * gas/testsuite/gas/aarch64/mov-no-aliases.d: Likewise.
+ * gas/testsuite/gas/aarch64/mov.d: Likewise.
+ * gas/testsuite/gas/aarch64/movi.d: Likewise.
+ * gas/testsuite/gas/aarch64/movw_label.d: Likewise.
+ * gas/testsuite/gas/aarch64/msr.d: Likewise.
+ * gas/testsuite/gas/aarch64/neon-fp-cvt-int.d: Likewise.
+ * gas/testsuite/gas/aarch64/neon-frint.d: Likewise.
+ * gas/testsuite/gas/aarch64/neon-ins.d: Likewise.
+ * gas/testsuite/gas/aarch64/neon-not.d: Likewise.
+ * gas/testsuite/gas/aarch64/neon-vfp-reglist-post.d: Likewise.
+ * gas/testsuite/gas/aarch64/neon-vfp-reglist.d: Likewise.
+ * gas/testsuite/gas/aarch64/no-aliases.d: Likewise.
+ * gas/testsuite/gas/aarch64/optional.d: Likewise.
+ * gas/testsuite/gas/aarch64/pac.d: Likewise.
+ * gas/testsuite/gas/aarch64/pan-directive.d: Likewise.
+ * gas/testsuite/gas/aarch64/pan.d: Likewise.
+ * gas/testsuite/gas/aarch64/rdma-directive.d: Likewise.
+ * gas/testsuite/gas/aarch64/rdma.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_g0.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_g0_nc.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_g1.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_hi12.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-1.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-tlsldm-1.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-tlsldm-page-1.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-1.d: Likewise.
+ * gas/testsuite/gas/aarch64/shifted.d: Likewise.
+ * gas/testsuite/gas/aarch64/sve.d: Likewise.
+ * gas/testsuite/gas/aarch64/symbol.d: Likewise.
+ * gas/testsuite/gas/aarch64/sysreg-1.d: Likewise.
+ * gas/testsuite/gas/aarch64/sysreg-2.d: Likewise.
+ * gas/testsuite/gas/aarch64/sysreg-3.d: Likewise.
+ * gas/testsuite/gas/aarch64/sysreg.d: Likewise.
+ * gas/testsuite/gas/aarch64/system-2.d: Likewise.
+ * gas/testsuite/gas/aarch64/system-3.d: Likewise.
+ * gas/testsuite/gas/aarch64/system.d: Likewise.
+ * gas/testsuite/gas/aarch64/tbz_1.d: Likewise.
+ * gas/testsuite/gas/aarch64/tlbi_op.d: Likewise.
+ * gas/testsuite/gas/aarch64/tls.d: Likewise.
+ * gas/testsuite/gas/aarch64/uao-directive.d: Likewise.
+ * gas/testsuite/gas/aarch64/uao.d: Likewise.
+ * gas/testsuite/gas/aarch64/virthostext-directive.d: Likewise.
+ * gas/testsuite/gas/aarch64/virthostext.d: Likewise.
+ * gas/testsuite/gas/aarch64/adr_1.d: Restrict test under -mabi=lp64.
+ * gas/testsuite/gas/aarch64/int-insns.d: Likewise.
+ * gas/testsuite/gas/aarch64/programmer-friendly.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-data.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_g1_nc.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_g2.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst16.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst32.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst64.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst8.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst16.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst32.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst64.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst8.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-gotoff_g0_nc.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-gotoff_g1.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-gottprel_g0_nc.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-gottprel_g1.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-insn.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-tlsdesc_off_g0_nc.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-tlsdesc_off_g1.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-tlsgd_g0_nc.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-tlsgd_g1.d: Likewise.
+ * gas/testsuite/gas/aarch64/tail_padding.d: Likewise.
+ * gas/testsuite/gas/aarch64/tls-desc.d: Likewise.
+
+2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-mips.c (mips16_macro_build) <'>'>: Remove case.
+
+2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips16-extend.d: New test.
+ * testsuite/gas/mips/mips16-extend.s: New test source.
+ * testsuite/gas/mips/mips.exp: Run the new test.
+
+2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-arc.c (arc_show_cpu_list): Rename `spaces' local
+ variable to `space_buf'.
+
+2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-arm.c (encode_arm_shift): Rename `index' local
+ variable to `op_index'.
+
+2016-12-08 Alan Modra <amodra@gmail.com>
+
+ * configure: Regenerate.
+
+2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-mips.c (is_opcode_valid): Use local `isa'
+ consistently.
+
+2016-12-06 Nick Clifton <nickc@redhat.com>
+
+ PR gas/20901
+ * read.c (s_space): Place an upper limit on the number of spaces
+ generated.
+
+ PR gas/20896
+ * testsuite/gas/mmix/err-byte1.s: Adjust expected warning messages
+ to account for patch to next_char_of_string.
+
+2016-12-05 Nick Clifton <nickc@redhat.com>
+
+ PR gas/20902
+ * read.c (next_char_of_string): Do end advance past the end of the
+ buffer.
+
+ PR gas/20904
+ * as.h (SKIP_ALL_WHITESPACE): New macro.
+ * expr.c (operand): Use it.
+
+2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * config/tc-arm.c (do_vcmla, do_vcadd): Define.
+ (neon_scalar_for_vcmla): Define.
+ (enum operand_parse_code): Add OP_IROT1 and OP_IROT2.
+ (NEON_ENC_TAB): Add DDSI and QQSI variants.
+ (insns): Add vcmla and vcadd.
+ * testsuite/gas/arm/armv8_3-a-simd.d: New.
+ * testsuite/gas/arm/armv8_3-a-simd.s: New.
+ * testsuite/gas/arm/armv8_3-a-simd-bad.d: New.
+ * testsuite/gas/arm/armv8_3-a-simd-bad.l: New.
+ * testsuite/gas/arm/armv8_3-a-simd-bad.s: New.
+
+2016-12-05 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * testsuite/gas/arc/textauxregister-1.d: New file.
+ * testsuite/gas/arc/textauxregister-1.s: Likewise.
+ * testsuite/gas/arc/textcondcode-err.s: Likewise.
+ * testsuite/gas/arc/textcoreregister-err.s: Likewise.
+ * config/tc-arc.c (tokenize_extregister): Return bfd_boolean,
+ don't check second argument of extension auxiliary register for
+ signess.
+ (arc_extcorereg): Consider the return of tokenize_extregister
+ function call.
+
+2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * config/tc-arm.c (arm_ext_v8_3, do_vjcvt): Define.
+ (insns): Add vjcvt.
+ * testsuite/gas/aarch64/armv8_3-a-fp.s: New.
+ * testsuite/gas/aarch64/armv8_3-a-fp.d: New.
+ * testsuite/gas/aarch64/armv8_3-a-fp-bad.s: New.
+ * testsuite/gas/aarch64/armv8_3-a-fp-bad.d: New.
+ * testsuite/gas/aarch64/armv8_3-a-fp-bad.l: New.
+
+2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * config/tc-arm.c (arm_archs): Add "armv8.3-a".
+ * doc/c-arm.texi (-march): Add "armv8.3-a".
+
+2016-12-02 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * testsuite/gas/arc/cpu-em-err.s: New file.
+ * testsuite/gas/arc/cpu-em4-err.s: Likewise.
+ * testsuite/gas/arc/cpu-fpuda-err.s: Likewise.
+ * testsuite/gas/arc/cpu-hs-err.s: Likewise.
+ * testsuite/gas/arc/cpu-quarkse-err.s: Likewise.
+ * testsuite/gas/arc/noargs_a7.s: Add .cpu.
+ * config/tc-arc.c (ARC_CPU_TYPE_A6xx): Define.
+ (ARC_CPU_TYPE_A7xx): Likewise.
+ (ARC_CPU_TYPE_AV2EM): Likewise.
+ (ARC_CPU_TYPE_AV2HS): Likewise.
+ (cpu_types): Update list of known CPU names.
+ (arc_show_cpu_list): New function.
+ (md_show_usage): Print accepted CPU names.
+ (cl_features): New variable.
+ (arc_select_cpu): Use cl_features.
+ (arc_option): Allow various .cpu names.
+ (md_parse_option): Set cl_features.
+ * doc/c-arc.texi: Update -mcpu and .cpu documentation.
+
+2016-12-02 Josh Conner <joshconner@google.com>
+
+ * configure.tgt: Add support for fuchsia (OS).
+
+2016-12-01 Nick Clifton <nickc@redhat.com>
+
+ PR gas/20898
+ * app.c (do_scrub_chars): Do not attempt to unget EOF.
+
+ PR gas/20897
+ * subsegs.c (subsegs_print_statistics): Do nothing if no output
+ file was created.
+
+ PR gas/20895
+ * symbols.c (resolve_symbol_value): Gracefully handle erroneous
+ symbolic expressions.
+
+2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/tc-arc.c (find_opcode_match): New function argument
+ errmsg.
+ (assemble_tokens): Collect and report the eventual error message
+ found during opcode matching process.
+ * testsuite/gas/arc/lpcount-err.s: New file.
+ * testsuite/gas/arc/add_s-err.s: Update error message.
+
+2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
+ Amit Pawar <amit.pawar@amd.com>
+
+ PR binutils/20637
+ * testsuite/gas/i386/xop32reg.d: New file.
+ * testsuite/gas/i386/xop32reg.s: New file.
+ * testsuite/gas/i386/i386.exp: Run new test.
+
+2016-11-27 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
+
+ * arparse.y: Fix spelling in comments.
+
+2016-11-27 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
+
+ * config/bfin-lex.l: Fix spelling in comments.
+
+2016-11-27 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
+
+ * testsuite/gas/all/gas.exp: Fix spelling in comments.
+ * testsuite/gas/cris/cris.exp: Fix spelling in comments.
+ * testsuite/gas/hppa/basic/basic.exp: Fix spelling in comments.
+ * testsuite/gas/hppa/parse/parse.exp: Fix spelling in comments.
+ * testsuite/gas/hppa/reloc/reloc.exp: Fix spelling in comments.
+ * testsuite/gas/sh/arch/arch.exp: Fix spelling in comments.
+ * testsuite/gas/tic4x/tic4x.exp: Fix spelling in comments.
+
+2016-11-27 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
+
+ * testsuite/gas/arm/local_function.d: Fix spelling in comments.
+ * testsuite/gas/arm/req.s: Fix spelling in comments.
+ * testsuite/gas/arm/vfp1.s: Fix spelling in comments.
+ * testsuite/gas/arm/vfp1_t2.s: Fix spelling in comments.
+ * testsuite/gas/arm/vfp1xD.s: Fix spelling in comments.
+ * testsuite/gas/arm/vfp1xD_t2.s: Fix spelling in comments.
+ * testsuite/gas/mcore/allinsn.s: Fix spelling in comments.
+ * testsuite/gas/mips/24k-triple-stores-5.s: Fix spelling in comments.
+ * testsuite/gas/mips/delay.d: Fix spelling in comments.
+ * testsuite/gas/mips/nodelay.d: Fix spelling in comments.
+ * testsuite/gas/mips/r5900-full.s: Fix spelling in comments.
+ * testsuite/gas/mips/r5900.s: Fix spelling in comments.
+
+2016-11-27 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
+
+ * as.h: Fix spelling in comments.
+ * config/obj-ecoff.c: Fix spelling in comments.
+ * config/obj-macho.c: Fix spelling in comments.
+ * config/tc-aarch64.c: Fix spelling in comments.
+ * config/tc-arc.c: Fix spelling in comments.
+ * config/tc-arm.c: Fix spelling in comments.
+ * config/tc-avr.c: Fix spelling in comments.
+ * config/tc-cr16.c: Fix spelling in comments.
+ * config/tc-epiphany.c: Fix spelling in comments.
+ * config/tc-frv.c: Fix spelling in comments.
+ * config/tc-hppa.c: Fix spelling in comments.
+ * config/tc-hppa.h: Fix spelling in comments.
+ * config/tc-i370.c: Fix spelling in comments.
+ * config/tc-m68hc11.c: Fix spelling in comments.
+ * config/tc-m68k.c: Fix spelling in comments.
+ * config/tc-mcore.c: Fix spelling in comments.
+ * config/tc-mep.c: Fix spelling in comments.
+ * config/tc-metag.c: Fix spelling in comments.
+ * config/tc-mips.c: Fix spelling in comments.
+ * config/tc-mn10200.c: Fix spelling in comments.
+ * config/tc-mn10300.c: Fix spelling in comments.
+ * config/tc-nds32.c: Fix spelling in comments.
+ * config/tc-nios2.c: Fix spelling in comments.
+ * config/tc-ns32k.c: Fix spelling in comments.
+ * config/tc-pdp11.c: Fix spelling in comments.
+ * config/tc-ppc.c: Fix spelling in comments.
+ * config/tc-riscv.c: Fix spelling in comments.
+ * config/tc-rx.c: Fix spelling in comments.
+ * config/tc-score.c: Fix spelling in comments.
+ * config/tc-score7.c: Fix spelling in comments.
+ * config/tc-sparc.c: Fix spelling in comments.
+ * config/tc-tic54x.c: Fix spelling in comments.
+ * config/tc-vax.c: Fix spelling in comments.
+ * config/tc-xgate.h: Fix spelling in comments.
+ * config/tc-xtensa.c: Fix spelling in comments.
+ * config/tc-z80.c: Fix spelling in comments.
+ * dwarf2dbg.c: Fix spelling in comments.
+ * input-file.h: Fix spelling in comments.
+ * itbl-ops.c: Fix spelling in comments.
+ * read.c: Fix spelling in comments.
+ * stabs.c: Fix spelling in comments.
+ * symbols.c: Fix spelling in comments.
+ * write.c: Fix spelling in comments.
+ * testsuite/gas/all/itbl-test.c: Fix spelling in comments.
+ * testsuite/gas/tic4x/opclasses.h: Fix spelling in comments.
+
+2016-11-25 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * config/tc-sparc.c (sparc_ip): Avoid emitting a cbcond error
+ messages for non-cbcond instructions.
+ * testsuite/gas/sparc/cbcond-diag.s: New file.
+ * testsuite/gas/sparc/cbcond-diag.l: Likewise.
+ * testsuite/gas/sparc/sparc.exp (gas_64_check): Run cbcond-diag tests.
+
+2016-11-23 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * testsuite/gas/sparc/sparc.exp (gas_64_check): Make sure the
+ hwcaps-bump test is run with 64-bit objects.
+
+2016-11-23 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+
+ * config/tc-riscv.c: Add missing break.
+
+2016-11-23 Alan Modra <amodra@gmail.com>
+
+ * po/POTFILES.in: Regenerate.
+
+2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
+
+ * configure: Regenerate.
+
+2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
+ opcodes/sparc-opc.c.
+ (sparc_arch): Clarify the new role of the hwcap_allowed and
+ hwcap2_allowed fields.
+ (sparc_arch_table): Remove HWS_* and HWS2_* instances from
+ hwcap_allowed and hwcap2_allowed respectively.
+ (md_parse_option): Include the opcode arch hwcaps when processing
+ -A.
+ (sparc_ip): Use the current opcode arch hwcaps to update
+ hwcap_allowed, as well as the hwcaps of the instruction triggering
+ the bump.
+ * testsuite/gas/sparc/hwcaps-bump.s: New file.
+ * testsuite/gas/sparc/hwcaps-bump.l: Likewise.
+ * testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
+ hwcaps-bump.
+
+2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * testsuite/gas/arc/b.d: Update test result.
+
+2016-11-22 Alan Modra <amodra@gmail.com>
+
+ PR 20744
+ * config/tc-ppc.c: Delete VLE insn defines.
+ (md_assemble): Swap use_a_reloc and use_d_reloc.
+ * testsuite/gas/ppc/vle-reloc.d: Update.
+
+2016-11-21 Renlin Li <renlin.li@arm.com>
+
+ PR gas/20827
+ * config/tc-arm.c (encode_arm_shift): Don't assert for operands not
+ presented.
+ * testsuite/gas/arm/add-shift-two.d: New.
+ * testsuite/gas/arm/add-shift-two.s: New.
+
+2016-11-21 Alan Modra <amodra@gmail.com>
+
+ * configure.ac: Invoke ACX_PROG_CMP_IGNORE_INITIAL.
+ * Makefile.am (comparison): Rewrite using do_compare.
+ * configure: Regenerate.
+ * Makefile.in: Regenerate.
+ * doc/Makefile.in: Regenerate.
+
+2016-11-18 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * testsuite/gas/arc/cl-warn.s: New file.
+ * testsuite/gas/arc/cpu-pseudop-1.d: Likewise.
+ * testsuite/gas/arc/cpu-pseudop-1.s: Likewise.
+ * testsuite/gas/arc/cpu-pseudop-2.d: Likewise.
+ * testsuite/gas/arc/cpu-pseudop-2.s: Likewise.
+ * testsuite/gas/arc/cpu-warn2.s: Likewise.
+ * config/tc-arc.c (selected_cpu): Initialize.
+ (feature_type): New struct.
+ (feature_list): New variable.
+ (arc_check_feature): New function.
+ (arc_select_cpu): Check for .cpu duplicates. Don't overwrite the
+ current cpu features. Check if a feature is available for a given
+ cpu.
+ (md_parse_option): Test if features are available for a given cpu.
+
+2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*.
+ * testsuite/gas/aarch64/advsimd-armv8_3.d: New.
+ * testsuite/gas/aarch64/advsimd-armv8_3.s: New.
+ * testsuite/gas/aarch64/illegal-fcmla.s: New.
+ * testsuite/gas/aarch64/illegal-fcmla.l: New.
+ * testsuite/gas/aarch64/illegal-fcmla.d: New.
+
+2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Add ldaprb, ldaprh, ldapr tests.
+ * testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Likewise.
+ * testsuite/gas/aarch64/illegal-ldapr.s: Likewise.
+ * testsuite/gas/aarch64/illegal-ldapr.d: Likewise.
+ * testsuite/gas/aarch64/illegal-ldapr.l: Likewise.
+
+2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * testsuite/gas/aarch64/fp-armv8_3.s: Add fjcvtzs test.
+ * testsuite/gas/aarch64/fp-armv8_3.d: Likewise.
+ * testsuite/gas/aarch64/illegal-fjcvtzs.s: Likewise.
+ * testsuite/gas/aarch64/illegal-fjcvtzs.d: Likewise.
+ * testsuite/gas/aarch64/illegal-fjcvtzs.l: Likewise.
+ * testsuite/gas/aarch64/illegal-nofp-armv8_3.s: Likewise.
+ * testsuite/gas/aarch64/illegal-nofp-armv8_3.d: Likewise.
+ * testsuite/gas/aarch64/illegal-nofp-armv8_3.l: Likewise.
+
+2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_ADDR_SIMM10.
+ (fix_insn): Likewise.
+ (warn_unpredictable_ldst): Handle ldst_imm10.
+ * testsuite/gas/aarch64/pac.s: Add ldraa and ldrab tests.
+ * testsuite/gas/aarch64/pac.d: Likewise.
+ * testsuite/gas/aarch64/illegal-ldraa.s: New.
+ * testsuite/gas/aarch64/illegal-ldraa.l: New.
+ * testsuite/gas/aarch64/illegal-ldraa.d: New.
+
+2016-11-15 Nick Clifton <nickc@redhat.com>
+
+ PR gas/20803
+ * config/tc-sparc.c (cons_fix_new_sparc): Use unaligned relocs in
+ the .eh_frame section.
+
+2016-11-13 Anthony Green <green@moxielogic.org>
+
+ * config/tc-moxie.c (md_assemble): Assemble 'bad' opcode.
+
+2016-11-11 Nick Clifton <nickc@redhat.com>
+
+ PR gas/20732
+ * expr.c (integer_constant): If tc_allow_L_suffix is defined and
+ non-zero then accept a L or LL suffix.
+ * testsuite/gas/sparc/pr20732.d: New test source file.
+ * testsuite/gas/sparc/pr20732.d: New test output file.
+ * testsuite/gas/sparc/sparc.exp: Run new test.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * testsuite/gas/aarch64/pac.s: Add ARMv8.3 branch instruction tests.
+ * testsuite/gas/aarch64/pac.d: Likewise.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * config/tc-aarch64.c (process_omitted_operand): Handle AARCH64_OPND_Rm_SP.
+ (parse_operands): Likewise.
+ * testsuite/gas/aarch64/pac.s: Add pacga.
+ * testsuite/gas/aarch64/pac.d: Add pacga.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * testsuite/gas/aarch64/pac.s: New.
+ * testsuite/gas/aarch64/pac.d: New.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * testsuite/gas/aarch64/sysreg-3.s: New.
+ * testsuite/gas/aarch64/sysreg-3.d: New.
+ * testsuite/gas/aarch64/illegal-sysreg-3.l: New.
+ * testsuite/gas/aarch64/illegal-sysreg-3.d: New.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * testsuite/gas/aarch64/system-3.s: New.
+ * testsuite/gas/aarch64/system-3.d: New.
+ * testsuite/gas/aarch64/system.d: Update expected output.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * config/tc-aarch64.c (aarch64_archs): Add "armv8.3-a".
+ * doc/c-aarch64.texi (-march): Likewise.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * config/tc-aarch64.c (aarch64_features): Fix "simd" and "crypto".
+ * testsuite/gas/aarch64/illegal-crypto-nofp.d: New.
+ * testsuite/gas/aarch64/illegal-crypto-nofp.l: New.
+ * testsuite/gas/aarch64/illegal-fp16-nofp.d: New.
+ * testsuite/gas/aarch64/illegal-fp16-nofp.l: New.
+ * testsuite/gas/aarch64/illegal-fp16-nofp.s: New.
+
+2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/20799
+ * testsuite/gas/i386/opcode.s: Add a test for EVEX vpextrw.
+ * testsuite/gas/i386/opcode-intel.d: Updated.
+ * testsuite/gas/i386/opcode-suffix.d: Likewise.
+ * testsuite/gas/i386/opcode.d: Likewise.
+ * testsuite/gas/i386/x86-64-avx512bw-opts.s: Remove vpextrw
+ tests.
+ * testsuite/gas/i386/x86-64-avx512bw-opts-intel.d: Updated.
+ * testsuite/gas/i386/x86-64-avx512bw-opts.d: Likewise.
+
+2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/20754
+ * testsuite/gas/i386/opcode-suffix.d: Updated.
+
+2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/20775
+ * testsuite/gas/i386/i386.exp: Run fpu-bad.
+ * testsuite/gas/i386/fpu-bad.d: New file.
+ * testsuite/gas/i386/fpu-bad.s: Likewise.
+
+2016-11-04 Nathan Sidwell <nathan@acm.org>
+
+ gas/
+ * input-scrub.c (partial_size): Make size_t.
+ (buffer_length): Likewise. Adjust meaning.
+ (struct input_save): Adjust partial_size type.
+ (input_scrub_reinit): New.
+ (input_scrub_push, input_scrub_begin): Use it.
+ (input_scrub_next_buffer): Fix buffer extension logic. Only scan
+ newly read buffer for newline.
+
+2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * config/tc-arc.c (find_opcode_match): Use insert function to
+ validate matching address type operands.
+ * testsuite/gas/arc/nps400-10.d: New file.
+ * testsuite/gas/arc/nps400-10.s: New file.
+
+2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (cortex-m33): Declare new processor.
+ * doc/c-arm.texi (-mcpu ARM command line option): Document new
+ Cortex-M33 processor.
+ * NEWS: Mention ARM Cortex-M33 support.
+
+2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (cortex-m23): Declare new processor.
+ * doc/c-arm.texi (-mcpu ARM command line option): Document new
+ Cortex-M23 processor.
+ * NEWS: Mention ARM Cortex-M23 support.
+
+2016-11-04 Palmer Dabbelt <palmer@dabbelt.com>
+ Andrew Waterman <andrew@sifive.com>
+
+ * Makefile.am (CPU_DOCS): Add c-riscv.texi.
+ * Makefile.in: Regenerate.
+ * doc/all.texi: Set RISCV.
+ * doc/as.texinfo: Add RISCV options.
+ Add RISC-V-Dependent node.
+ Include c-riscv.texi.
+ * doc/c-riscv.texi: Rename RISC-V Options to RISC-V-Opts.
+
+2016-11-03 Graham Markall <graham.markall@embecosm.com>
+
+ * testsuite/gas/arc/nps400-6.s: Change ldbit tests so that limm
+ operands are out of the range of an s9, in order to fix the test.
+ * testsuite/gas/arc/nps400-6.d: Updated to match new expected output.
+
+2016-11-03 Graham Markall <graham.markall@embecosm.com>
+
+ * testsuite/gas/arc/nps-400-9.d: Added.
+ * testsuite/gas/arc/nps-400-9.s: Added.
+
+2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * config/tc-arc.c (struct arc_insn): Change type of insn field.
+ (md_number_to_chars_midend): Support 6- and 8-byte values.
+ (emit_insn0): Update debug output.
+ (find_opcode_match): Likewise.
+ (build_fake_opcode_hash_entry): Delete.
+ (find_special_case_long_opcode): Delete.
+ (find_special_case): Remove long format special case handling.
+ (insert_operand): Change instruction type and update debug print
+ format.
+ (assemble_insn): Change instruction type, update debug print
+ formats, and remove unneeded assert.
+
+2016-11-03 Graham Markall <graham.markall@embecosm.com>
+
+ * config/tc-arc.c (assemble_insn): Replace use of ARC_SHORT with
+ arc_opcode_len.
+
+2016-11-03 Graham Markall <graham.markall@embecosm.com>
+
+ * config/tc-arc.c (struct arc_insn): Replace short_insn flag with
+ len field.
+ (apply_fixups): Update to use len field.
+ (emit_insn0): Simplify code, making use of len field.
+ (md_convert_frag): Update to use len field.
+ (assemble_insn): Update to use len field.
+
+2016-11-03 Siddhesh Poyarekar <siddhesh.poyarekar@linaro.org>
+
+ * config/tc-aarch64.c (aarch64_cpus): Add falkor.
+ * config/tc-arm.c (arm_cpus): Likewise.
+ * doc/c-aarch64.texi: Likewise.
+ * doc/c-arm.texi: Likewise.
+
+2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/20754
+ * testsuite/gas/i386/opcode.s: Add tests for opcode 0x82.
+ * testsuite/gas/i386/opcode-intel.d: Updated.
+ * testsuite/gas/i386/opcode.d: Likewise.
+
2016-11-02 Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (SBIT_SHIFT): New.