-*- text -*-
+* Remove -mold-gcc command-line option for x86 targets.
+
+* Add -O[2|s] command-line options to x86 assembler to enable alternate
+ shorter instruction encoding.
+
+* Add support for .nops directive. It is currently supported only for
+ x86 targets.
+
+Changes in 2.30:
+
+* Add support for loaction views in DWARF debug line information.
+
+Changes in 2.29:
+
+* Add support for ELF SHF_GNU_MBIND.
+
+* Add support for the WebAssembly file format and wasm32 ELF conversion.
+
+* PowerPC gas now checks that the correct register class is used in
+ instructions. For instance, "addi %f4,%cr3,%r31" warns three times
+ that the registers are invalid.
+
+* Add support for the Texas Instruments PRU processor.
+
+* Support for the ARMv8-R architecture and Cortex-R52 processor has been
+ added to the ARM port.
+
+Changes in 2.28:
+
+* Add support for the RISC-V architecture.
+
+* Add support for the ARM Cortex-M23 and Cortex-M33 processors.
+
+Changes in 2.27:
+
+* Default to --enable-compressed-debug-sections=gas for Linux/x86 targets.
+
+* Add --no-pad-sections to stop the assembler from padding the end of output
+ sections up to their alignment boundary.
+
+* Support for the ARMv8-M architecture has been added to the ARM port. Support
+ for the ARMv8-M Security and DSP Extensions has also been added to the ARM
+ port.
+
+* ARC backend accepts .extInstruction, .extCondCode, .extAuxRegister, and
+ .extCoreRegister pseudo-ops that allow an user to define custom
+ instructions, conditional codes, auxiliary and core registers.
+
+* Add a configure option --enable-elf-stt-common to decide whether ELF
+ assembler should generate common symbols with the STT_COMMON type by
+ default. Default to no.
+
+* New command line option --elf-stt-common= for ELF targets to control
+ whether to generate common symbols with the STT_COMMON type.
+
+* Add ability to set section flags and types via numeric values for ELF
+ based targets.
+
+* Add a configure option --enable-x86-relax-relocations to decide whether
+ x86 assembler should generate relax relocations by default. Default to
+ yes, except for x86 Solaris targets older than Solaris 12.
+
+* New command line option -mrelax-relocations= for x86 target to control
+ whether to generate relax relocations.
+
+* New command line option -mfence-as-lock-add=yes for x86 target to encode
+ lfence, mfence and sfence as "lock addl $0x0, (%[re]sp)".
+
+* Add assembly-time relaxation option for ARC cpus.
+
+* Add --with-cpu=TYPE configure option for ARC gas. This allows the default
+ cpu type to be adjusted at configure time.
+
Changes in 2.26:
+* Add a configure option --enable-compressed-debug-sections={all,gas} to
+ decide whether DWARF debug sections should be compressed by default.
+
+* Add support for the ARC EM/HS, and ARC600/700 architectures. Remove
+ assembler support for Argonaut RISC architectures.
+
+* Symbol and label names can now be enclosed in double quotes (") which allows
+ them to contain characters that are not part of valid symbol names in high
+ level languages.
+
+* Added the correctly spelled -march=armv6kz, for ARMv6KZ support. The
+ previous spelling, -march=armv6zk, is still accepted.
+
* Support for the ARMv8.1 architecture has been added to the Aarch64 port.
Support for the individual ARMv8.1 Adv.SIMD, LOR and PAN architecture
extensions has also been added to the Aarch64 port.
of new CPUs and formats, lots of bugs fixed.
\f
-Copyright (C) 2012-2015 Free Software Foundation, Inc.
+Copyright (C) 2012-2018 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright