/* rl78-parse.y Renesas RL78 parser
- Copyright 2011
- Free Software Foundation, Inc.
+ Copyright (C) 2011-2015 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
%token HALT
%token INC INCW
%token MACH MACHU MOV MOV1 MOVS MOVW MULH MULHU MULU
-%token NOP
+%token NOP NOT1
%token ONEB ONEW OR OR1
%token POP PUSH
%token RET RETI RETB ROL ROLC ROLWC ROR RORC
/* ---------------------------------------------------------------------- */
| BC '$' EXPR
- { B1 (0xdc); PC1 ($3); }
+ { B1 (0xdc); PC1 ($3); rl78_relax (RL78_RELAX_BRANCH, 0); }
| BNC '$' EXPR
- { B1 (0xde); PC1 ($3); }
+ { B1 (0xde); PC1 ($3); rl78_relax (RL78_RELAX_BRANCH, 0); }
| BZ '$' EXPR
- { B1 (0xdd); PC1 ($3); }
+ { B1 (0xdd); PC1 ($3); rl78_relax (RL78_RELAX_BRANCH, 0); }
| BNZ '$' EXPR
- { B1 (0xdf); PC1 ($3); }
+ { B1 (0xdf); PC1 ($3); rl78_relax (RL78_RELAX_BRANCH, 0); }
| BH '$' EXPR
- { B2 (0x61, 0xc3); PC1 ($3); }
+ { B2 (0x61, 0xc3); PC1 ($3); rl78_relax (RL78_RELAX_BRANCH, 0); }
| BNH '$' EXPR
- { B2 (0x61, 0xd3); PC1 ($3); }
+ { B2 (0x61, 0xd3); PC1 ($3); rl78_relax (RL78_RELAX_BRANCH, 0); }
/* ---------------------------------------------------------------------- */
| DIVHU
{ B3 (0xce, 0xfb, 0x03); }
+/* Note that the DIVWU encoding was changed from [0xce,0xfb,0x04] to
+ [0xce,0xfb,0x0b]. Different versions of the Software Manual exist
+ with the same version number, but varying encodings. The version
+ here matches the hardware. */
+
| DIVWU
- { B3 (0xce, 0xfb, 0x04); }
+ { B3 (0xce, 0xfb, 0x0b); }
| MACHU
{ B3 (0xce, 0xfb, 0x05); }
| NOP
{ B1 (0x00); }
+/* ---------------------------------------------------------------------- */
+
+ | NOT1 CY
+ { B2 (0x71, 0xc0); }
+
/* ---------------------------------------------------------------------- */
| POP regw
;
andor1 : AND1 { $$ = 0x05; rl78_bit_insn = 1; }
- | OR1 { $$ = 0x06; rl78_bit_insn = 1;}
+ | OR1 { $$ = 0x06; rl78_bit_insn = 1; }
| XOR1 { $$ = 0x07; rl78_bit_insn = 1; }
;
-bt_bf : BT { $$ = 0x02; rl78_bit_insn = 1;}
- | BF { $$ = 0x04; rl78_bit_insn = 1; }
+bt_bf : BT { $$ = 0x02; rl78_bit_insn = 1; rl78_relax (RL78_RELAX_BRANCH, 0); }
+ | BF { $$ = 0x04; rl78_bit_insn = 1; rl78_relax (RL78_RELAX_BRANCH, 0); }
| BTCLR { $$ = 0x00; rl78_bit_insn = 1; }
;
OPC(MULHU),
OPC(MULU),
OPC(NOP),
+ OPC(NOT1),
OPC(ONEB),
OPC(ONEW),
OPC(OR),