/* rx-parse.y Renesas RX parser
- Copyright (C) 2008-2015 Free Software Foundation, Inc.
+ Copyright (C) 2008-2017 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
else rx_linkrelax_dsp (pos); \
F (displacement (v, msz), pos, 2)
-#define id24(a,b2,b3) B3 (0xfb+a, b2, b3)
+#define id24(a,b2,b3) B3 (0xfb + a, b2, b3)
static void rx_check_float_support (void);
static int rx_intop (expressionS, int, int);
static int displacement (expressionS, int);
static void rtsd_immediate (expressionS);
static void rx_range (expressionS, int, int);
+static void rx_check_v2 (void);
static int need_flag = 0;
static int rx_in_brackets = 0;
expressionS exp;
}
-%type <regno> REG FLAG CREG BCND BMCND SCCND
+%type <regno> REG FLAG CREG BCND BMCND SCCND ACC
%type <regno> flag bwl bw memex
%type <exp> EXPR disp
-%token REG FLAG CREG
+%token REG FLAG CREG ACC
%token EXPR UNKNOWN_OPCODE IS_OPCODE
%token BCLR BCND BMCND BNOT BRA BRK BSET BSR BTST
%token CLRPSW CMP
%token DBT DIV DIVU
-%token EDIV EDIVU EMUL EMULU
-%token FADD FCMP FDIV FMUL FREIT FSUB FTOI
+%token EDIV EDIVU EMACA EMSBA EMUL EMULA EMULU
+%token FADD FCMP FDIV FMUL FREIT FSUB FSQRT FTOI FTOU
%token INT ITOF
%token JMP JSR
-%token MACHI MACLO MAX MIN MOV MOVU MUL MULHI MULLO MULU MVFACHI MVFACMI MVFACLO
-%token MVFC MVTACHI MVTACLO MVTC MVTIPL
+%token MACHI MACLH MACLO MAX MIN MOV MOVCO MOVLI MOVU MSBHI MSBLH MSBLO MUL
+%token MULHI MULLH MULLO MULU MVFACHI MVFACGU MVFACMI MVFACLO MVFC MVTACGU
+%token MVTACHI MVTACLO MVTC MVTIPL
%token NEG NOP NOT
%token OR
%token POP POPC POPM PUSH PUSHA PUSHC PUSHM
-%token RACW REIT REVL REVW RMPA ROLC RORC ROTL ROTR ROUND RTE RTFI RTS RTSD
+%token RACL RACW RDACL RDACW REIT REVL REVW RMPA ROLC RORC ROTL ROTR ROUND
+%token RTE RTFI RTS RTSD
%token SAT SATR SBB SCCND SCMPU SETPSW SHAR SHLL SHLR SMOVB SMOVF
%token SMOVU SSTR STNZ STOP STZ SUB SUNTIL SWHILE
%token TST
+%token UTOF
%token WAIT
%token XCHG XOR
/* ---------------------------------------------------------------------- */
+ | MOV DOT_B '#' EXPR ',' '[' REG ']'
+ { B2 (0xf8, 0x04); F ($7, 8, 4); IMMB ($4, 12);}
+
+ | MOV DOT_W '#' EXPR ',' '[' REG ']'
+ { B2 (0xf8, 0x01); F ($7, 8, 4); IMMW ($4, 12);}
+
+ | MOV DOT_L '#' EXPR ',' '[' REG ']'
+ { B2 (0xf8, 0x02); F ($7, 8, 4); IMM ($4, 12);}
+
| MOV DOT_B '#' EXPR ',' disp '[' REG ']'
/* rx_disp5op changes the value if it succeeds, so keep it last. */
{ if ($8 <= 7 && rx_uintop ($4, 8) && rx_disp5op0 (&$6, BSIZE))
/* ---------------------------------------------------------------------- */
| PUSHC CREG
- { if ($2 < 16)
+ { if ($2 == 13)
+ { rx_check_v2 (); }
+ if ($2 < 16)
{ B2 (0x7e, 0xc0); F ($2, 12, 4); }
else
as_bad (_("PUSHC can only push the first 16 control registers")); }
/* ---------------------------------------------------------------------- */
| POPC CREG
- { if ($2 < 16)
+ { if ($2 == 13)
+ { rx_check_v2 (); }
+ if ($2 < 16)
{ B2 (0x7e, 0xe0); F ($2, 12, 4); }
else
as_bad (_("POPC can only pop the first 16 control registers")); }
| TST { sub_op = 12; } op_dp20_rim
| XOR { sub_op = 13; } op_dp20_rim
| NOT { sub_op = 14; sub_op2 = 0; } op_dp20_rr
- | STZ { sub_op = 14; } op_dp20_i
- | STNZ { sub_op = 15; } op_dp20_i
+ | STZ { sub_op = 14; sub_op2 = 0; } op_dp20_ri
+ | STNZ { sub_op = 15; sub_op2 = 1; } op_dp20_ri
/* ---------------------------------------------------------------------- */
| EMULU { sub_op = 7; } op_xchg
| XCHG { sub_op = 16; } op_xchg
| ITOF { sub_op = 17; } op_xchg
+ | UTOF { sub_op = 21; } op_xchg
/* ---------------------------------------------------------------------- */
/* ---------------------------------------------------------------------- */
- | FSUB { sub_op = 0; } float2_op
+ | FSUB { sub_op = 0; } float3_op
| FCMP { sub_op = 1; } float2_op
- | FADD { sub_op = 2; } float2_op
- | FMUL { sub_op = 3; } float2_op
+ | FADD { sub_op = 2; } float3_op
+ | FMUL { sub_op = 3; } float3_op
| FDIV { sub_op = 4; } float2_op
+ | FSQRT { sub_op = 8; } float2_op_ni
| FTOI { sub_op = 5; } float2_op_ni
+ | FTOU { sub_op = 9; } float2_op_ni
| ROUND { sub_op = 6; } float2_op_ni
+/* ---------------------------------------------------------------------- */
+
+
/* ---------------------------------------------------------------------- */
| SCCND DOT_L REG
| MULHI REG ',' REG
{ id24 (2, 0x00, 0x00); F ($2, 16, 4); F ($4, 20, 4); }
+ | MULHI REG ',' REG ',' ACC
+ { rx_check_v2 (); id24 (2, 0x00, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
| MULLO REG ',' REG
{ id24 (2, 0x01, 0x00); F ($2, 16, 4); F ($4, 20, 4); }
+ | MULLO REG ',' REG ',' ACC
+ { rx_check_v2 (); id24 (2, 0x01, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
| MACHI REG ',' REG
{ id24 (2, 0x04, 0x00); F ($2, 16, 4); F ($4, 20, 4); }
+ | MACHI REG ',' REG ',' ACC
+ { rx_check_v2 (); id24 (2, 0x04, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
| MACLO REG ',' REG
{ id24 (2, 0x05, 0x00); F ($2, 16, 4); F ($4, 20, 4); }
+ | MACLO REG ',' REG ',' ACC
+ { rx_check_v2 (); id24 (2, 0x05, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
/* ---------------------------------------------------------------------- */
/* We don't have syntax for these yet. */
| MVTACHI REG
{ id24 (2, 0x17, 0x00); F ($2, 20, 4); }
+ | MVTACHI REG ',' ACC
+ { rx_check_v2 (); id24 (2, 0x17, 0x00); F ($2, 20, 4); F ($4, 16, 1); }
| MVTACLO REG
{ id24 (2, 0x17, 0x10); F ($2, 20, 4); }
+ | MVTACLO REG ',' ACC
+ { rx_check_v2 (); id24 (2, 0x17, 0x10); F ($2, 20, 4); F ($4, 16, 1); }
| MVFACHI REG
{ id24 (2, 0x1f, 0x00); F ($2, 20, 4); }
+ | MVFACHI { sub_op = 0; } mvfa_op
| MVFACMI REG
{ id24 (2, 0x1f, 0x20); F ($2, 20, 4); }
+ | MVFACMI { sub_op = 2; } mvfa_op
| MVFACLO REG
{ id24 (2, 0x1f, 0x10); F ($2, 20, 4); }
-
+ | MVFACLO { sub_op = 1; } mvfa_op
| RACW '#' EXPR
{ id24 (2, 0x18, 0x00);
if (rx_uintop ($3, 4) && $3.X_add_number == 1)
F (1, 19, 1);
else
as_bad (_("RACW expects #1 or #2"));}
+ | RACW '#' EXPR ',' ACC
+ { rx_check_v2 (); id24 (2, 0x18, 0x00); F ($5, 16, 1);
+ if (rx_uintop ($3, 4) && $3.X_add_number == 1)
+ ;
+ else if (rx_uintop ($3, 4) && $3.X_add_number == 2)
+ F (1, 19, 1);
+ else
+ as_bad (_("RACW expects #1 or #2"));}
/* ---------------------------------------------------------------------- */
/* ---------------------------------------------------------------------- */
| MVTC REG ',' CREG
- { id24 (2, 0x68, 0x00); F ($4 % 16, 20, 4); F ($4 / 16, 15, 1);
+ { if ($4 == 13)
+ rx_check_v2 ();
+ id24 (2, 0x68, 0x00); F ($4 % 16, 20, 4); F ($4 / 16, 15, 1);
F ($2, 16, 4); }
/* ---------------------------------------------------------------------- */
| MVFC CREG ',' REG
- { id24 (2, 0x6a, 0); F ($2, 15, 5); F ($4, 20, 4); }
+ { if ($2 == 13)
+ rx_check_v2 ();
+ id24 (2, 0x6a, 0); F ($2, 15, 5); F ($4, 20, 4); }
/* ---------------------------------------------------------------------- */
/* ---------------------------------------------------------------------- */
| MVTC '#' EXPR ',' CREG
- { id24 (2, 0x73, 0x00); F ($5, 19, 5); IMM ($3, 12); }
+ { if ($5 == 13)
+ rx_check_v2 ();
+ id24 (2, 0x73, 0x00); F ($5, 19, 5); IMM ($3, 12); }
/* ---------------------------------------------------------------------- */
| SBB '#' EXPR ',' REG
{ id24 (2, 0x70, 0x20); F ($5, 20, 4); NBIMM ($3, 12); }
+/* ---------------------------------------------------------------------- */
+
+ | MOVCO REG ',' '[' REG ']'
+ { rx_check_v2 (); B3 (0xfd, 0x27, 0x00); F ($5, 16, 4); F ($2, 20, 4); }
+
+/* ---------------------------------------------------------------------- */
+
+ | MOVLI '[' REG ']' ',' REG
+ { rx_check_v2 (); B3 (0xfd, 0x2f, 0x00); F ($3, 16, 4); F ($6, 20, 4); }
+
+/* ---------------------------------------------------------------------- */
+
+ | EMACA REG ',' REG ',' ACC
+ { rx_check_v2 (); id24 (2, 0x07, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
+ | EMSBA REG ',' REG ',' ACC
+ { rx_check_v2 (); id24 (2, 0x47, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
+ | EMULA REG ',' REG ',' ACC
+ { rx_check_v2 (); id24 (2, 0x03, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
+ | MACLH REG ',' REG ',' ACC
+ { rx_check_v2 (); id24 (2, 0x06, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
+ | MSBHI REG ',' REG ',' ACC
+ { rx_check_v2 (); id24 (2, 0x44, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
+ | MSBLH REG ',' REG ',' ACC
+ { rx_check_v2 (); id24 (2, 0x46, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
+ | MSBLO REG ',' REG ',' ACC
+ { rx_check_v2 (); id24 (2, 0x45, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
+ | MULLH REG ',' REG ',' ACC
+ { rx_check_v2 (); id24 (2, 0x02, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
+ | MVFACGU { sub_op = 3; } mvfa_op
+ | MVTACGU REG ',' ACC
+ { rx_check_v2 (); id24 (2, 0x17, 0x30); F ($4, 16, 1); F ($2, 20, 4); }
+ | RACL '#' EXPR ',' ACC
+ { rx_check_v2 (); id24 (2, 0x19, 0x00); F ($5, 16, 1);
+ if (rx_uintop ($3, 4) && $3.X_add_number == 1)
+ ;
+ else if (rx_uintop ($3, 4) && $3.X_add_number == 2)
+ F (1, 19, 1);
+ else
+ as_bad (_("RACL expects #1 or #2"));}
+ | RDACL '#' EXPR ',' ACC
+ { rx_check_v2 (); id24 (2, 0x19, 0x40); F ($5, 16, 1);
+ if (rx_uintop ($3, 4) && $3.X_add_number == 1)
+ ;
+ else if (rx_uintop ($3, 4) && $3.X_add_number == 2)
+ F (1, 19, 1);
+ else
+ as_bad (_("RDACL expects #1 or #2"));}
+ | RDACW '#' EXPR ',' ACC
+ { rx_check_v2 (); id24 (2, 0x18, 0x40); F ($5, 16, 1);
+ if (rx_uintop ($3, 4) && $3.X_add_number == 1)
+ ;
+ else if (rx_uintop ($3, 4) && $3.X_add_number == 2)
+ F (1, 19, 1);
+ else
+ as_bad (_("RDACW expects #1 or #2"));}
+
/* ---------------------------------------------------------------------- */
;
{ B2 (0x7e, sub_op2 << 4); F ($1, 12, 4); }
;
-/* xchg, itof, emul, emulu */
+op_dp20_r
+ : REG ',' REG
+ { id24 (1, 0x4b + (sub_op2<<2), 0x00); F ($1, 16, 4); F ($3, 20, 4); }
+ ;
+
+op_dp20_ri
+ : { rx_check_v2 (); }
+ op_dp20_r
+ | op_dp20_i
+ ;
+
+/* xchg, utof, itof, emul, emulu */
op_xchg
: REG ',' REG
{ id24 (1, 0x03 + (sub_op<<2), 0); F ($1, 16, 4); F ($3, 20, 4); }
| op_shift_rot
;
+float3_op
+ : '#' EXPR ',' REG
+ { rx_check_float_support (); id24 (2, 0x72, sub_op << 4); F ($4, 20, 4); O4 ($2); }
+ | REG ',' REG
+ { rx_check_float_support (); id24 (1, 0x83 + (sub_op << 2), 0); F ($1, 16, 4); F ($3, 20, 4); }
+ | disp '[' REG ']' opt_l ',' REG
+ { rx_check_float_support (); id24 (1, 0x80 + (sub_op << 2), 0); F ($3, 16, 4); F ($7, 20, 4); DSP ($1, 14, LSIZE); }
+ | REG ',' REG ',' REG
+ { rx_check_v2 (); id24 (4, 0x80 + (sub_op << 4), 0 ); F ($1, 16, 4); F ($3, 20, 4); F ($5, 12, 4); }
+ ;
float2_op
: { rx_check_float_support (); }
{ id24 (1, 0x80 + (sub_op << 2), 0); F ($4, 16, 4); F ($8, 20, 4); DSP ($2, 14, LSIZE); }
;
+mvfa_op
+ : { rx_check_v2 (); }
+ '#' EXPR ',' ACC ',' REG
+ { id24 (2, 0x1e, sub_op << 4); F ($7, 20, 4); F ($5, 16, 1);
+ if (rx_uintop ($3, 4))
+ {
+ switch (exp_val ($3))
+ {
+ case 0:
+ F (1, 15, 1);
+ break;
+ case 1:
+ F (1, 15, 1);
+ F (1, 17, 1);
+ break;
+ case 2:
+ break;
+ default:
+ as_bad (_("IMM expects #0 to #2"));}
+ } else
+ as_bad (_("IMM expects #0 to #2"));}
+ ;
+
/* ====================================================================== */
disp : { $$ = zero_expr (); }
{ "isp", CREG, 10 },
{ "fintv", CREG, 11 },
{ "intb", CREG, 12 },
+ { "extb", CREG, 13 },
{ "pbp", CREG, 16 },
{ "pben", CREG, 17 },
{ "i", FLAG, 8 },
{ "u", FLAG, 9 },
+ { "a0", ACC, 0 },
+ { "a1", ACC, 1 },
+
#define OPC(x) { #x, x, IS_OPCODE }
OPC(ABS),
OPC(ADC),
OPC(DIVU),
OPC(EDIV),
OPC(EDIVU),
+ OPC(EMACA),
+ OPC(EMSBA),
OPC(EMUL),
+ OPC(EMULA),
OPC(EMULU),
OPC(FADD),
OPC(FCMP),
OPC(FDIV),
OPC(FMUL),
OPC(FREIT),
+ OPC(FSQRT),
+ OPC(FTOU),
OPC(FSUB),
OPC(FTOI),
OPC(INT),
OPC(ITOF),
OPC(JMP),
OPC(JSR),
+ OPC(MVFACGU),
OPC(MVFACHI),
OPC(MVFACMI),
OPC(MVFACLO),
OPC(MVFC),
+ OPC(MVTACGU),
OPC(MVTACHI),
OPC(MVTACLO),
OPC(MVTC),
OPC(MVTIPL),
OPC(MACHI),
OPC(MACLO),
+ OPC(MACLH),
OPC(MAX),
OPC(MIN),
OPC(MOV),
+ OPC(MOVCO),
+ OPC(MOVLI),
OPC(MOVU),
+ OPC(MSBHI),
+ OPC(MSBLH),
+ OPC(MSBLO),
OPC(MUL),
OPC(MULHI),
+ OPC(MULLH),
OPC(MULLO),
OPC(MULU),
OPC(NEG),
OPC(PUSHA),
OPC(PUSHC),
OPC(PUSHM),
+ OPC(RACL),
OPC(RACW),
+ OPC(RDACL),
+ OPC(RDACW),
OPC(REIT),
OPC(REVL),
OPC(REVW),
OPC(SUNTIL),
OPC(SWHILE),
OPC(TST),
+ OPC(UTOF),
OPC(WAIT),
OPC(XCHG),
OPC(XOR),
static struct
{
- char * string;
+ const char * string;
int token;
}
condition_opcode_table[] =
static struct
{
- char * string;
+ const char * string;
int val;
}
condition_table[] =
}
static int
-check_condition (char * base)
+check_condition (const char * base)
{
char * cp;
unsigned int i;
long v;
long mask, msb;
- if (exp.X_op == O_big && nbits == 32)
- return 1;
- if (exp.X_op != O_constant)
+ if (exp.X_op == O_big)
+ {
+ if (nbits == 32)
+ return 1;
+ if (exp.X_add_number == -1)
+ return 0;
+ }
+ else if (exp.X_op != O_constant)
return 0;
v = exp.X_add_number;
static int
immediate (expressionS exp, int type, int pos, int bits)
{
- /* We will emit constants ourself here, so negate them. */
+ /* We will emit constants ourselves here, so negate them. */
if (type == RXREL_NEGATIVE && exp.X_op == O_constant)
exp.X_add_number = - exp.X_add_number;
if (type == RXREL_NEGATIVE_BORROW)
if (rx_cpu == RX100 || rx_cpu == RX200)
rx_error (_("target CPU type does not support floating point instructions"));
}
+
+static void
+rx_check_v2 (void)
+{
+ if (rx_cpu < RXV2)
+ rx_error (_("target CPU type does not support v2 instructions"));
+}
projects / deliverable / binutils-gdb.git / blobdiff