/* Which ABI to use. */
enum aarch64_abi_type
{
- AARCH64_ABI_LP64 = 0,
- AARCH64_ABI_ILP32 = 1
+ AARCH64_ABI_NONE = 0,
+ AARCH64_ABI_LP64 = 1,
+ AARCH64_ABI_ILP32 = 2
};
+#ifndef DEFAULT_ARCH
+#define DEFAULT_ARCH "aarch64"
+#endif
+
+/* DEFAULT_ARCH is initialized in gas/configure.tgt. */
+static const char *default_arch = DEFAULT_ARCH;
+
/* AArch64 ABI for the output file. */
-static enum aarch64_abi_type aarch64_abi = AARCH64_ABI_LP64;
+static enum aarch64_abi_type aarch64_abi = AARCH64_ABI_NONE;
/* When non-zero, program to a 32-bit model, in which the C data types
int, long and all pointer types are 32-bit objects (ILP32); or to a
return PARSE_FAIL;
}
- if (in_reg_list == TRUE)
+ if (in_reg_list)
{
first_error (_("index not allowed inside register list"));
return PARSE_FAIL;
switch (mode)
{
case SHIFTED_LOGIC_IMM:
- if (aarch64_extend_operator_p (kind) == TRUE)
+ if (aarch64_extend_operator_p (kind))
{
set_syntax_error (_("extending shift is not permitted"));
return FALSE;
operand->shifter.amount = 1;
else if (exp.X_op == O_absent)
{
- if (aarch64_extend_operator_p (kind) == FALSE || exp_has_prefix)
+ if (!aarch64_extend_operator_p (kind) || exp_has_prefix)
{
set_syntax_error (_("missing shift amount"));
return FALSE;
const aarch64_opnd_qualifier_t *qualifiers = *qualifiers_list;
/* Most opcodes has much fewer patterns in the list. */
- if (empty_qualifier_sequence_p (qualifiers) == TRUE)
+ if (empty_qualifier_sequence_p (qualifiers))
{
DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence");
break;
{
/* Most opcodes has much fewer patterns in the list.
First NIL qualifier indicates the end in the list. */
- if (empty_qualifier_sequence_p (*qualifiers_list) == TRUE)
+ if (empty_qualifier_sequence_p (*qualifiers_list))
break;
if (i != qlf_idx)
REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
+ REGDEF (ip0, 16, R_64), REGDEF (IP0, 16, R_64),
+ REGDEF (ip1, 17, R_64), REGDEF (IP1, 17, R_64),
+ REGDEF (fp, 29, R_64), REGDEF (FP, 29, R_64),
+ REGDEF (lr, 30, R_64), REGDEF (LR, 30, R_64),
+
/* Floating-point single precision registers. */
REGSET (s, FP_S), REGSET (S, FP_S),
#ifdef OBJ_ELF
+/* Implement md_after_parse_args. This is the earliest time we need to decide
+ ABI. If no -mabi specified, the ABI will be decided by target triplet. */
+
+void
+aarch64_after_parse_args (void)
+{
+ if (aarch64_abi != AARCH64_ABI_NONE)
+ return;
+
+ /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
+ if (strlen (default_arch) > 7 && strcmp (default_arch + 7, ":32") == 0)
+ aarch64_abi = AARCH64_ABI_ILP32;
+ else
+ aarch64_abi = AARCH64_ABI_LP64;
+}
+
const char *
elf64_aarch64_target_format (void)
{
AARCH64_FEATURE_CRC), "Cortex-A72"},
{"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8,
AARCH64_FEATURE_CRC), "Cortex-A73"},
+ {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+ AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16),
+ "Cortex-A55"},
+ {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+ AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16),
+ "Cortex-A75"},
{"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8,
AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
"Samsung Exynos M1"},