static const attributes_t syntaxclass[] =
{
{ "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
- { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP }
+ { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP },
+ { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP },
+ { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP }
};
/* Extension instruction syntax classes modifiers. */
if (!mach_type_specified_p)
{
- if ((!strcasecmp ("ARC600", cpu))
- || (!strcasecmp ("ARC601", cpu))
- || (!strcasecmp ("A6", cpu)))
+ if ((!strcmp ("ARC600", cpu))
+ || (!strcmp ("ARC601", cpu))
+ || (!strcmp ("A6", cpu)))
{
md_parse_option (OPTION_MCPU, "arc600");
}
- else if ((!strcasecmp ("ARC700", cpu))
- || (!strcasecmp ("A7", cpu)))
+ else if ((!strcmp ("ARC700", cpu))
+ || (!strcmp ("A7", cpu)))
{
md_parse_option (OPTION_MCPU, "arc700");
}
- else if (!strcasecmp ("EM", cpu))
+ else if (!strcmp ("EM", cpu))
{
md_parse_option (OPTION_MCPU, "arcem");
}
- else if (!strcasecmp ("HS", cpu))
+ else if (!strcmp ("HS", cpu))
{
md_parse_option (OPTION_MCPU, "archs");
}
- else if (!strcasecmp ("NPS400", cpu))
+ else if (!strcmp ("NPS400", cpu))
{
md_parse_option (OPTION_MCPU, "nps400");
}
&& (einsn.major != 5) && (einsn.major != 9))
as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
- switch (einsn.syntax & (ARC_SYNTAX_3OP | ARC_SYNTAX_2OP))
+ switch (einsn.syntax & ARC_SYNTAX_MASK)
{
case ARC_SYNTAX_3OP:
if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
break;
case ARC_SYNTAX_2OP:
+ case ARC_SYNTAX_1OP:
+ case ARC_SYNTAX_NOP:
if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
break;