static const attributes_t syntaxclass[] =
{
{ "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
- { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP }
+ { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP },
+ { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP },
+ { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP }
};
/* Extension instruction syntax classes modifiers. */
/* The default architecture. */
static int arc_mach_type;
-/* Non-zero if the cpu type has been explicitly specified. */
-static int mach_type_specified_p = 0;
+/* TRUE if the cpu type has been explicitly specified. */
+static bfd_boolean mach_type_specified_p = FALSE;
/* The hash table of instruction opcodes. */
static struct hash_control *arc_opcode_hash;
{
md_parse_option (OPTION_MCPU, "archs");
}
+ else if (!strcmp ("NPS400", cpu))
+ {
+ md_parse_option (OPTION_MCPU, "nps400");
+ }
else
as_fatal (_("could not find the architecture"));
if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach))
as_fatal (_("could not set architecture and machine"));
+
+ /* Set elf header flags. */
+ bfd_set_private_flags (stdoutput, arc_eflag);
}
else
if (arc_mach_type != mach)
case OPTION_MCPU:
{
arc_select_cpu (arg);
- mach_type_specified_p = 1;
+ mach_type_specified_p = TRUE;
break;
}
&& (einsn.major != 5) && (einsn.major != 9))
as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
- switch (einsn.syntax & (ARC_SYNTAX_3OP | ARC_SYNTAX_2OP))
+ switch (einsn.syntax & ARC_SYNTAX_MASK)
{
case ARC_SYNTAX_3OP:
if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
break;
case ARC_SYNTAX_2OP:
+ case ARC_SYNTAX_1OP:
+ case ARC_SYNTAX_NOP:
if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
break;