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[deliverable/binutils-gdb.git] / gas / config / tc-arm.c

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index fa61988aa40a241920fda982d91f5a7d749a497d..19ead2e3b7337f36ab59a1256f261345508ea4b9 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -57,7 +57,7 @@
 /* Architectures are the sum of the base and extensions */
 #define ARM_ARCH_V4    (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
 #define ARM_ARCH_V4T   (ARM_ARCH_V4 | ARM_THUMB)
-#define ARM_ARCH_V5    (ARM_ARCH_V4 | ARM_EXT_V5 )
+#define ARM_ARCH_V5    (ARM_ARCH_V4 | ARM_EXT_V5)
 #define ARM_ARCH_V5T   (ARM_ARCH_V5 | ARM_THUMB)
 
 /* Some useful combinations:  */
@@ -139,10 +139,11 @@ CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
 symbolS * GOT_symbol;          /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
 #endif
 
-CONST int md_reloc_size = 8;           /* Size of relocation record */
-
-static int thumb_mode = 0;      /* non-zero if assembling thumb instructions */
+CONST int md_reloc_size = 8;   /* Size of relocation record */
 
+static int thumb_mode = 0;      /* 0: assemble for ARM, 1: assemble for Thumb,
+                                  2: assemble for Thumb even though target cpu
+                                  does not support thumb instructions */
 typedef struct arm_fix
 {
   int thumb_mode;
@@ -1260,7 +1261,7 @@ s_force_thumb (ignore)
      
   if (! thumb_mode)
     {
-      thumb_mode = 1;
+      thumb_mode = 2;
       
       record_alignment (now_seg, 1);
     }
@@ -1382,7 +1383,11 @@ arm_s_text (ignore)
   if (now_seg != text_section)
     s_ltorg (0);
   
+#ifdef OBJ_ELF
+  obj_elf_text (ignore);
+#else
   s_text (ignore);
+#endif
 }
 
 static void
@@ -1397,7 +1402,11 @@ arm_s_data (ignore)
   else if (now_seg != data_section)
     s_ltorg (0);
   
+#ifdef OBJ_ELF
+  obj_elf_data (ignore);
+#else
   s_data (ignore);
+#endif
 }
 
 #ifdef OBJ_ELF
@@ -6068,7 +6077,7 @@ md_assemble (str)
       if (opcode)
        {
          /* Check that this instruction is supported for this CPU.  */
-         if ((opcode->variants & cpu_variant) == 0)
+         if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
             {
                as_bad (_("selected processor does not support this opcode"));
                return;
@@ -6114,7 +6123,7 @@ md_assemble (str)
                  if (opcode->comp_suffix)
                    {
                       if (*opcode->comp_suffix != '\0')
-                        as_bad (_("Opcode `%s' must have suffix from <%s>\n"),
+                        as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
                             str, opcode->comp_suffix);
                       else
                         /* Not a conditional instruction. */
@@ -6155,7 +6164,6 @@ _("Warning: Use of the 'nv' conditional is deprecated\n"));
              else
                cond_code = COND_ALWAYS;
 
-
              /* Apply the conditional, or complain it's not allowed. */
              if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
                {
@@ -6399,7 +6407,8 @@ md_parse_option (c, arg)
             }
           else if (streq (str, "thumb-interwork"))
             {
-              cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB | ARM_ARCH_V4;
+             if ((cpu_variant & ARM_THUMB) == 0)
+               cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
 #if defined OBJ_COFF || defined OBJ_ELF
               support_interwork = true;
 #endif
@@ -6521,6 +6530,7 @@ md_parse_option (c, arg)
                case 70:
                case 700:
                case 710:
+               case 720:
                case 7100:
                case 7500:
                  break;
@@ -6633,7 +6643,6 @@ md_parse_option (c, arg)
                    default:  as_bad (_("Invalid architecture variant -m%s"), arg); break;
                    }
                  break;
-
                  
                default:
                  as_bad (_("Invalid architecture variant -m%s"), arg);
@@ -6670,7 +6679,7 @@ md_show_usage (fp)
 _("\
  ARM Specific Assembler Options:\n\
   -m[arm][<processor name>] select processor variant\n\
-  -m[arm]v[2|2a|3|3m|4|4t|5]select architecture variant\n\
+  -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
   -mthumb                   only allow Thumb instructions\n\
   -mthumb-interwork         mark the assembled code as supporting interworking\n\
   -mall                     allow any instruction\n\