#define ARM_250 ARM_3
#define ARM_6 0x00000008
#define ARM_7 ARM_6 /* same core instruction set */
+#define ARM_8 ARM_6 /* same core instruction set */
+#define ARM_9 ARM_6 /* same core instruction set */
#define ARM_CPU_MASK 0x0000000f
/* The following bitmasks control CPU extensions (ARM7 onwards): */
#define ARM_LONGMUL 0x00000010 /* allow long multiplies */
#define ARM_HALFWORD 0x00000020 /* allow half word loads */
#define ARM_THUMB 0x00000040 /* allow BX instruction */
+#define ARM_EXT_V5 0x00000080 /* allow CLZ etc */
-#define ARM_ARCHv4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
+/* Architectures are the sum of the base and extensions */
+#define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
+#define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
+#define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
+#define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
/* Some useful combinations: */
#define ARM_ANY 0x00ffffff
-#define ARM_2UP 0x00fffffe
+#define ARM_2UP (ARM_ANY - ARM_1)
#define ARM_ALL ARM_2UP /* Not arm1 only */
#define ARM_3UP 0x00fffffc
#define ARM_6UP 0x00fffff8 /* Includes ARM7 */
#ifndef CPU_DEFAULT
#if defined __thumb__
-#define CPU_DEFAULT (ARM_ARCHv4 | ARM_THUMB)
+#define CPU_DEFAULT (ARM_ARCH_V4 | ARM_THUMB)
#else
#define CPU_DEFAULT ARM_ALL
#endif
#define FPU_DEFAULT FPU_ALL
#endif
+#define streq(a, b) (strcmp (a, b) == 0)
+#define skip_whitespace(str) while (* (str) == ' ') ++ (str)
+
static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
static int target_oabi = 0;
/* Also note that comments like this one will always work. */
CONST char line_comment_chars[] = "#";
+#ifdef TE_LINUX
+CONST char line_separator_chars[] = ";";
+#else
CONST char line_separator_chars[] = "";
+#endif
/* Chars that can be used to separate mant from exp in floating point nums */
CONST char EXP_CHARS[] = "eE";
CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
+/* Prefix characters that indicate the start of an immediate
+ value. */
+#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
+
+#ifdef OBJ_ELF
+symbolS * GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
+#endif
+
CONST int md_reloc_size = 8; /* Size of relocation record */
static int thumb_mode = 0; /* non-zero if assembling thumb instructions */
/* Functions called by parser */
/* ARM instructions */
-static void do_arit PARAMS ((char *operands, unsigned long flags));
-static void do_cmp PARAMS ((char *operands, unsigned long flags));
-static void do_mov PARAMS ((char *operands, unsigned long flags));
-static void do_ldst PARAMS ((char *operands, unsigned long flags));
-static void do_ldmstm PARAMS ((char *operands, unsigned long flags));
-static void do_branch PARAMS ((char *operands, unsigned long flags));
-static void do_swi PARAMS ((char *operands, unsigned long flags));
-/* Pseudo Op codes */
-static void do_adr PARAMS ((char *operands, unsigned long flags));
-static void do_nop PARAMS ((char *operands, unsigned long flags));
-/* ARM 2 */
-static void do_mul PARAMS ((char *operands, unsigned long flags));
-static void do_mla PARAMS ((char *operands, unsigned long flags));
-/* ARM 3 */
-static void do_swap PARAMS ((char *operands, unsigned long flags));
-/* ARM 6 */
-static void do_msr PARAMS ((char *operands, unsigned long flags));
-static void do_mrs PARAMS ((char *operands, unsigned long flags));
-/* ARM 7M */
-static void do_mull PARAMS ((char *operands, unsigned long flags));
-/* ARM THUMB */
-static void do_bx PARAMS ((char *operands, unsigned long flags));
-
-/* Coprocessor Instructions */
-static void do_cdp PARAMS ((char *operands, unsigned long flags));
-static void do_lstc PARAMS ((char *operands, unsigned long flags));
-static void do_co_reg PARAMS ((char *operands, unsigned long flags));
-static void do_fp_ctrl PARAMS ((char *operands, unsigned long flags));
-static void do_fp_ldst PARAMS ((char *operands, unsigned long flags));
-static void do_fp_ldmstm PARAMS ((char *operands, unsigned long flags));
-static void do_fp_dyadic PARAMS ((char *operands, unsigned long flags));
-static void do_fp_monadic PARAMS ((char *operands, unsigned long flags));
-static void do_fp_cmp PARAMS ((char *operands, unsigned long flags));
-static void do_fp_from_reg PARAMS ((char *operands, unsigned long flags));
-static void do_fp_to_reg PARAMS ((char *operands, unsigned long flags));
-
-static void fix_new_arm PARAMS ((fragS *frag, int where,
- short int size, expressionS *exp,
- int pc_rel, int reloc));
-static int arm_reg_parse PARAMS ((char **ccp));
-static int arm_psr_parse PARAMS ((char **ccp));
-static void symbol_locate PARAMS ((symbolS *, CONST char *, segT,
- valueT, fragS *));
+static void do_arit PARAMS ((char *, unsigned long));
+static void do_cmp PARAMS ((char *, unsigned long));
+static void do_mov PARAMS ((char *, unsigned long));
+static void do_ldst PARAMS ((char *, unsigned long));
+static void do_ldmstm PARAMS ((char *, unsigned long));
+static void do_branch PARAMS ((char *, unsigned long));
+static void do_swi PARAMS ((char *, unsigned long));
+/* Pseudo Op codes */
+static void do_adr PARAMS ((char *, unsigned long));
+static void do_adrl PARAMS ((char *, unsigned long));
+static void do_nop PARAMS ((char *, unsigned long));
+/* ARM 2 */
+static void do_mul PARAMS ((char *, unsigned long));
+static void do_mla PARAMS ((char *, unsigned long));
+/* ARM 3 */
+static void do_swap PARAMS ((char *, unsigned long));
+/* ARM 6 */
+static void do_msr PARAMS ((char *, unsigned long));
+static void do_mrs PARAMS ((char *, unsigned long));
+/* ARM 7M */
+static void do_mull PARAMS ((char *, unsigned long));
+/* ARM THUMB */
+static void do_bx PARAMS ((char *, unsigned long));
+
+/* Coprocessor Instructions */
+static void do_cdp PARAMS ((char *, unsigned long));
+static void do_lstc PARAMS ((char *, unsigned long));
+static void do_co_reg PARAMS ((char *, unsigned long));
+static void do_fp_ctrl PARAMS ((char *, unsigned long));
+static void do_fp_ldst PARAMS ((char *, unsigned long));
+static void do_fp_ldmstm PARAMS ((char *, unsigned long));
+static void do_fp_dyadic PARAMS ((char *, unsigned long));
+static void do_fp_monadic PARAMS ((char *, unsigned long));
+static void do_fp_cmp PARAMS ((char *, unsigned long));
+static void do_fp_from_reg PARAMS ((char *, unsigned long));
+static void do_fp_to_reg PARAMS ((char *, unsigned long));
+
+static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
+static int arm_reg_parse PARAMS ((char **));
+static int arm_psr_parse PARAMS ((char **));
+static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));
static int add_to_lit_pool PARAMS ((void));
-static unsigned validate_immediate PARAMS ((unsigned));
-static int validate_offset_imm PARAMS ((int, int));
+static unsigned validate_immediate PARAMS ((unsigned));
+static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
+static int validate_offset_imm PARAMS ((unsigned int, int));
static void opcode_select PARAMS ((int));
static void end_of_line PARAMS ((char *));
static int reg_required_here PARAMS ((char **, int));
static int my_get_float_expression PARAMS ((char **));
static int skip_past_comma PARAMS ((char **));
static int walk_no_bignums PARAMS ((symbolS *));
-static int negate_data_op PARAMS ((unsigned long *,
- unsigned long));
+static int negate_data_op PARAMS ((unsigned long *, unsigned long));
static int data_op2 PARAMS ((char **));
static int fp_op2 PARAMS ((char **));
static long reg_list PARAMS ((char **));
static void set_constant_flonums PARAMS ((void));
static valueT md_chars_to_number PARAMS ((char *, int));
static void insert_reg_alias PARAMS ((char *, int));
-static void output_inst PARAMS ((char *));
+static void output_inst PARAMS ((void));
+#ifdef OBJ_ELF
+static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
+#endif
/* ARM instructions take 4bytes in the object file, Thumb instructions
take 2: */
/* Pseudo ops */
{"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
+ {"adrl", 0x028f0000, NULL, NULL, ARM_ANY, do_adrl},
{"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
/* ARM 2 multiplies */
/* ARM 6 Coprocessor instructions */
{"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
{"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
+/* ScottB: our code uses 0x0128f000 for msr.
+ NickC: but this is wrong because the bits 16 and 19 are handled
+ by the PSR_xxx defines above. */
/* ARM 7M long multiplies - need signed/unsigned flags! */
{"smull", 0x00c00090, NULL, s_flag, ARM_LONGMUL, do_mull},
#define OPCODE_BIC 14
#define OPCODE_MVN 15
-static void do_t_nop PARAMS ((char *operands));
-static void do_t_arit PARAMS ((char *operands));
-static void do_t_add PARAMS ((char *operands));
-static void do_t_asr PARAMS ((char *operands));
-static void do_t_branch9 PARAMS ((char *operands));
-static void do_t_branch12 PARAMS ((char *operands));
-static void do_t_branch23 PARAMS ((char *operands));
-static void do_t_bx PARAMS ((char *operands));
-static void do_t_compare PARAMS ((char *operands));
-static void do_t_ldmstm PARAMS ((char *operands));
-static void do_t_ldr PARAMS ((char *operands));
-static void do_t_ldrb PARAMS ((char *operands));
-static void do_t_ldrh PARAMS ((char *operands));
-static void do_t_lds PARAMS ((char *operands));
-static void do_t_lsl PARAMS ((char *operands));
-static void do_t_lsr PARAMS ((char *operands));
-static void do_t_mov PARAMS ((char *operands));
-static void do_t_push_pop PARAMS ((char *operands));
-static void do_t_str PARAMS ((char *operands));
-static void do_t_strb PARAMS ((char *operands));
-static void do_t_strh PARAMS ((char *operands));
-static void do_t_sub PARAMS ((char *operands));
-static void do_t_swi PARAMS ((char *operands));
-static void do_t_adr PARAMS ((char *operands));
+static void do_t_nop PARAMS ((char *));
+static void do_t_arit PARAMS ((char *));
+static void do_t_add PARAMS ((char *));
+static void do_t_asr PARAMS ((char *));
+static void do_t_branch9 PARAMS ((char *));
+static void do_t_branch12 PARAMS ((char *));
+static void do_t_branch23 PARAMS ((char *));
+static void do_t_bx PARAMS ((char *));
+static void do_t_compare PARAMS ((char *));
+static void do_t_ldmstm PARAMS ((char *));
+static void do_t_ldr PARAMS ((char *));
+static void do_t_ldrb PARAMS ((char *));
+static void do_t_ldrh PARAMS ((char *));
+static void do_t_lds PARAMS ((char *));
+static void do_t_lsl PARAMS ((char *));
+static void do_t_lsr PARAMS ((char *));
+static void do_t_mov PARAMS ((char *));
+static void do_t_push_pop PARAMS ((char *));
+static void do_t_str PARAMS ((char *));
+static void do_t_strb PARAMS ((char *));
+static void do_t_strh PARAMS ((char *));
+static void do_t_sub PARAMS ((char *));
+static void do_t_swi PARAMS ((char *));
+static void do_t_adr PARAMS ((char *));
#define T_OPCODE_MUL 0x4340
#define T_OPCODE_TST 0x4200
{NULL, 0}
};
-#define bad_args _("Bad arguments to instruction");
-#define bad_pc _("r15 not allowed here");
+#define bad_args _("Bad arguments to instruction");
+#define bad_pc _("r15 not allowed here");
static struct hash_control * arm_ops_hsh = NULL;
static struct hash_control * arm_tops_hsh = NULL;
static void s_code PARAMS ((int));
static void s_force_thumb PARAMS ((int));
static void s_thumb_func PARAMS ((int));
+static void s_thumb_set PARAMS ((int));
+static void arm_s_text PARAMS ((int));
+static void arm_s_data PARAMS ((int));
+#ifdef OBJ_ELF
+static void arm_s_section PARAMS ((int));
+static void s_arm_elf_cons PARAMS ((int));
+#endif
static int my_get_expression PARAMS ((expressionS *, char **));
CONST pseudo_typeS md_pseudo_table[] =
{
- {"req", s_req, 0}, /* Never called becasue '.req' does not start line */
- {"bss", s_bss, 0},
- {"align", s_align, 0},
- {"arm", s_arm, 0},
- {"thumb", s_thumb, 0},
- {"code", s_code, 0},
- {"force_thumb", s_force_thumb, 0},
- {"thumb_func", s_thumb_func, 0},
- {"even", s_even, 0},
- {"ltorg", s_ltorg, 0},
- {"pool", s_ltorg, 0},
- {"word", cons, 4},
- {"extend", float_cons, 'x'},
- {"ldouble", float_cons, 'x'},
- {"packed", float_cons, 'p'},
- {0, 0, 0}
+ { "req", s_req, 0 }, /* Never called becasue '.req' does not start line */
+ { "bss", s_bss, 0 },
+ { "align", s_align, 0 },
+ { "arm", s_arm, 0 },
+ { "thumb", s_thumb, 0 },
+ { "code", s_code, 0 },
+ { "force_thumb", s_force_thumb, 0 },
+ { "thumb_func", s_thumb_func, 0 },
+ { "thumb_set", s_thumb_set, 0 },
+ { "even", s_even, 0 },
+ { "ltorg", s_ltorg, 0 },
+ { "pool", s_ltorg, 0 },
+ /* Allow for the effect of section changes. */
+ { "text", arm_s_text, 0 },
+ { "data", arm_s_data, 0 },
+#ifdef OBJ_ELF
+ { "section", arm_s_section, 0 },
+ { "section.s", arm_s_section, 0 },
+ { "sect", arm_s_section, 0 },
+ { "sect.s", arm_s_section, 0 },
+ { "word", s_arm_elf_cons, 4 },
+ { "long", s_arm_elf_cons, 4 },
+#else
+ { "word", cons, 4},
+#endif
+ { "extend", float_cons, 'x' },
+ { "ldouble", float_cons, 'x' },
+ { "packed", float_cons, 'p' },
+ { 0, 0, 0 }
};
/* Stuff needed to resolve the label ambiguity
int next_literal_pool_place = 0; /* Next free entry in the pool */
int lit_pool_num = 1; /* Next literal pool number */
symbolS * current_poolP = NULL;
-symbolS * symbol_make_empty PARAMS ((void));
static int
add_to_lit_pool ()
int lit_count = 0;
if (current_poolP == NULL)
- current_poolP = symbol_make_empty ();
+ current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
+ (valueT) 0, &zero_address_frag);
/* Check if this literal value is already in the pool: */
while (lit_count < next_literal_pool_place)
S_SET_VALUE (symbolP, valu);
symbol_clear_list_pointers(symbolP);
- symbolP->sy_frag = frag;
+ symbol_set_frag (symbolP, frag);
/* Link to end of symbol chain. */
{
#endif /* DEBUG_SYMS */
}
-symbolS *
-symbol_make_empty ()
-{
- symbolS * symbolP;
-
- symbolP = (symbolS *) obstack_alloc (¬es, sizeof (symbolS));
-
- /* symbol must be born in some fixed state. This seems as good as any. */
- memset (symbolP, 0, sizeof (symbolS));
-
- symbolP->bsym = bfd_make_empty_symbol (stdoutput);
- assert (symbolP->bsym != 0);
- symbolP->bsym->udata.p = (PTR) symbolP;
+/* Check that an immediate is valid, and if so, convert it to the right format. */
- return symbolP;
+static unsigned int
+validate_immediate (val)
+ unsigned int val;
+{
+ unsigned int a;
+ unsigned int i;
+
+#define rotate_left(v, n) (v << n | v >> (32 - n))
+
+ for (i = 0; i < 32; i += 2)
+ if ((a = rotate_left (val, i)) <= 0xff)
+ return a | (i << 7); /* 12-bit pack: [shift-cnt,const] */
+
+ return FAIL;
}
-/* Check that an immediate is valid, and if so, convert it to the right format. */
+/* Check to see if an immediate can be computed as two seperate immediate
+ values, added together. We already know that this value cannot be
+ computed by just one ARM instruction. */
static unsigned int
-validate_immediate (val)
+validate_immediate_twopart (val, highpart)
unsigned int val;
+ unsigned int * highpart;
{
- unsigned int a;
- unsigned int i;
+ unsigned int a;
+ unsigned int i;
+
+ for (i = 0; i < 32; i += 2)
+ if (((a = rotate_left (val, i)) & 0xff) != 0)
+ {
+ if (a & 0xff00)
+ {
+ if (a & ~ 0xffff)
+ continue;
+ * highpart = (a >> 8) | ((i + 24) << 7);
+ }
+ else if (a & 0xff0000)
+ {
+ if (a & 0xff000000)
+ continue;
-#define rotate_left(v, n) (v << n | v >> (32 - n))
-
- for (i = 0; i < 32; i += 2)
- if ((a = rotate_left (val, i)) <= 0xff)
- return a | (i << 7); /* 12-bit pack: [shift-cnt,const] */
- return FAIL;
+ * highpart = (a >> 16) | ((i + 16) << 7);
+ }
+ else
+ {
+ assert (a & 0xff000000);
+
+ * highpart = (a >> 24) | ((i + 8) << 7);
+ }
+
+ return (a & 0xff) | (i << 7);
+ }
+
+ return FAIL;
}
static int
validate_offset_imm (val, hwse)
- int val;
+ unsigned int val;
int hwse;
{
- if ((hwse && (val < -255 || val > 255))
- || (val < -4095 || val > 4095))
+ if ((hwse && val > 255) || val > 4095)
return FAIL;
return val;
}
}
static void
-s_ltorg (internal)
- int internal;
+s_ltorg (ignored)
+ int ignored;
{
int lit_count = 0;
char sym_name[20];
if (current_poolP == NULL)
- {
- /* Nothing to do */
- if (!internal)
- as_tsktsk (_("Nothing to put in the pool\n"));
- return;
- }
+ return;
/* Align pool as you have word accesses */
/* Only make a frag if we have to ... */
record_alignment (now_seg, 2);
- if (internal)
- as_tsktsk (_("Inserting implicit pool at change of section"));
-
sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
symbol_locate (current_poolP, sym_name, now_seg,
demand_empty_rest_of_line ();
}
+/* Perform a .set directive, but also mark the alias as
+ being a thumb function. */
+
+static void
+s_thumb_set (equiv)
+ int equiv;
+{
+ /* XXX the following is a duplicate of the code for s_set() in read.c
+ We cannot just call that code as we need to get at the symbol that
+ is created. */
+ register char * name;
+ register char delim;
+ register char * end_name;
+ register symbolS * symbolP;
+
+ /*
+ * Especial apologies for the random logic:
+ * this just grew, and could be parsed much more simply!
+ * Dean in haste.
+ */
+ name = input_line_pointer;
+ delim = get_symbol_end ();
+ end_name = input_line_pointer;
+ *end_name = delim;
+
+ SKIP_WHITESPACE ();
+
+ if (*input_line_pointer != ',')
+ {
+ *end_name = 0;
+ as_bad (_("Expected comma after name \"%s\""), name);
+ *end_name = delim;
+ ignore_rest_of_line ();
+ return;
+ }
+
+ input_line_pointer++;
+ *end_name = 0;
+
+ if (name[0] == '.' && name[1] == '\0')
+ {
+ /* XXX - this should not happen to .thumb_set */
+ abort ();
+ }
+
+ if ((symbolP = symbol_find (name)) == NULL
+ && (symbolP = md_undefined_symbol (name)) == NULL)
+ {
+#ifndef NO_LISTING
+ /* When doing symbol listings, play games with dummy fragments living
+ outside the normal fragment chain to record the file and line info
+ for this symbol. */
+ if (listing & LISTING_SYMBOLS)
+ {
+ extern struct list_info_struct * listing_tail;
+ fragS * dummy_frag = (fragS *) xmalloc (sizeof(fragS));
+ memset (dummy_frag, 0, sizeof(fragS));
+ dummy_frag->fr_type = rs_fill;
+ dummy_frag->line = listing_tail;
+ symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
+ dummy_frag->fr_symbol = symbolP;
+ }
+ else
+#endif
+ symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
+
+#ifdef OBJ_COFF
+ /* "set" symbols are local unless otherwise specified. */
+ SF_SET_LOCAL (symbolP);
+#endif /* OBJ_COFF */
+ } /* make a new symbol */
+
+ symbol_table_insert (symbolP);
+
+ * end_name = delim;
+
+ if (equiv
+ && S_IS_DEFINED (symbolP)
+ && S_GET_SEGMENT (symbolP) != reg_section)
+ as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
+
+ pseudo_set (symbolP);
+
+ demand_empty_rest_of_line ();
+
+ /* XXX Now we come to the Thumb specific bit of code. */
+
+ THUMB_SET_FUNC (symbolP, 1);
+ ARM_SET_THUMB (symbolP, 1);
+ ARM_SET_INTERWORK (symbolP, support_interwork);
+}
+
+/* If we change section we must dump the literal pool first. */
+static void
+arm_s_text (ignore)
+ int ignore;
+{
+ if (now_seg != text_section)
+ s_ltorg (0);
+
+ s_text (ignore);
+}
+
+static void
+arm_s_data (ignore)
+ int ignore;
+{
+ if (flag_readonly_data_in_text)
+ {
+ if (now_seg != text_section)
+ s_ltorg (0);
+ }
+ else if (now_seg != data_section)
+ s_ltorg (0);
+
+ s_data (ignore);
+}
+
+#ifdef OBJ_ELF
+static void
+arm_s_section (ignore)
+ int ignore;
+{
+ s_ltorg (0);
+
+ obj_elf_section (ignore);
+}
+#endif
+
static void
opcode_select (width)
int width;
end_of_line (str)
char * str;
{
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
- if (*str != '\0')
+ if (* str != '\0')
inst.error = _("Garbage following instruction");
}
*str = start;
/* In the few cases where we might be able to accept something else
- this error can be overridden */
+ this error can be overridden. */
sprintf (buff, _("Register expected, not '%.100s'"), start);
inst.error = buff;
}
/* In the few cases where we might be able to accept something else
- this error can be overridden */
+ this error can be overridden. */
inst.error = _("<psr(f)> expected");
/* Restore the start point. */
static int
co_proc_number (str)
- char **str;
+ char ** str;
{
int processor, pchar;
- while (**str == ' ')
- (*str)++;
+ skip_whitespace (* str);
/* The data sheet seems to imply that just a number on its own is valid
here, but the RISC iX assembler seems to accept a prefix 'p'. We will
{
expressionS expr;
- while (**str == ' ')
- (*str)++;
+ skip_whitespace (* str);
memset (&expr, '\0', sizeof (expr));
}
/* In the few cases where we might be able to accept something else
- this error can be overridden */
+ this error can be overridden. */
inst.error = _("Co-processor register expected");
- /* Restore the start point */
+ /* Restore the start point. */
*str = start;
return FAIL;
}
}
/* In the few cases where we might be able to accept something else
- this error can be overridden */
+ this error can be overridden. */
inst.error = _("Floating point register expected");
- /* Restore the start point */
+ /* Restore the start point. */
*str = start;
return FAIL;
}
{
int offset;
- while (**str == ' ')
- (*str)++;
+ skip_whitespace (* str);
- if (**str != '#')
+ if (! is_immediate_prefix (**str))
{
inst.error = _("immediate expression expected");
return FAIL;
}
(*str)++;
- if (my_get_expression (&inst.reloc.exp, str))
+
+ if (my_get_expression (& inst.reloc.exp, str))
return FAIL;
+
if (inst.reloc.exp.X_op == O_constant)
{
offset = inst.reloc.exp.X_add_number;
+
if (offset & 3)
{
inst.error = _("co-processor address must be word aligned");
cp_address_required_here (str)
char ** str;
{
- char *p = *str;
- int pre_inc = 0;
- int write_back = 0;
+ char * p = * str;
+ int pre_inc = 0;
+ int write_back = 0;
if (*p == '[')
{
int reg;
p++;
- while (*p == ' ')
- p++;
+ skip_whitespace (p);
- if ((reg = reg_required_here (&p, 16)) == FAIL)
+ if ((reg = reg_required_here (& p, 16)) == FAIL)
return FAIL;
- while (*p == ' ')
- p++;
+ skip_whitespace (p);
if (*p == ']')
{
p++;
- if (skip_past_comma (&p) == SUCCESS)
+
+ if (skip_past_comma (& p) == SUCCESS)
{
/* [Rn], #expr */
write_back = WRITE_BACK;
+
if (reg == REG_PC)
{
inst.error = _("pc may not be used in post-increment");
return FAIL;
}
- if (cp_address_offset (&p) == FAIL)
+ if (cp_address_offset (& p) == FAIL)
return FAIL;
}
else
{
/* '['Rn, #expr']'[!] */
- if (skip_past_comma (&p) == FAIL)
+ if (skip_past_comma (& p) == FAIL)
{
inst.error = _("pre-indexed expression expected");
return FAIL;
}
pre_inc = PRE_INDEX;
- if (cp_address_offset (&p) == FAIL)
+
+ if (cp_address_offset (& p) == FAIL)
return FAIL;
- while (*p == ' ')
- p++;
+ skip_whitespace (p);
if (*p++ != ']')
{
return FAIL;
}
- while (*p == ' ')
- p++;
+ skip_whitespace (p);
if (*p == '!')
{
static void
do_nop (str, flags)
- char *str;
+ char * str;
unsigned long flags;
{
- /* Do nothing really */
- inst.instruction |= flags; /* This is pointless */
+ /* Do nothing really. */
+ inst.instruction |= flags; /* This is pointless. */
end_of_line (str);
return;
}
char *str;
unsigned long flags;
{
- /* Only one syntax */
- while (*str == ' ')
- str++;
+ /* Only one syntax. */
+ skip_whitespace (str);
if (reg_required_here (&str, 12) == FAIL)
{
return;
}
-/* Three possible forms: "<psr>, Rm", "<psrf>, Rm", "<psrf>, #expression" */
+/* Three possible forms: "<psr>, Rm", "<psrf>, Rm", "<psrf>, #expression". */
static void
do_msr (str, flags)
- char *str;
+ char * str;
unsigned long flags;
{
int reg;
- while (*str == ' ')
- str ++;
+ skip_whitespace (str);
if (psr_required_here (&str, CPSR_ALL, SPSR_ALL) == SUCCESS)
{
else
{
if (psr_required_here (& str, CPSR_FLG, SPSR_FLG) == SUCCESS)
- {
- inst.instruction |= PSR_FLAGS;
- }
+ inst.instruction |= PSR_FLAGS;
else if (psr_required_here (& str, CPSR_CTL, SPSR_CTL) == SUCCESS)
- {
- inst.instruction |= PSR_CONTROL;
- }
+ inst.instruction |= PSR_CONTROL;
else
{
inst.error = bad_args;
/* Syntax could be "<psrf>, rm", "<psrf>, #expression" */
- if ((reg = reg_required_here (&str, 0)) != FAIL)
+ if ((reg = reg_required_here (& str, 0)) != FAIL)
;
- /* Immediate expression */
- else if (*(str++) == '#')
+ /* Immediate expression. */
+ else if (is_immediate_prefix (* str))
{
+ str ++;
inst.error = NULL;
- if (my_get_expression (&inst.reloc.exp, &str))
+
+ if (my_get_expression (& inst.reloc.exp, & str))
{
inst.error = _("Register or shift expression expected");
return;
*/
static void
do_mull (str, flags)
- char *str;
+ char * str;
unsigned long flags;
{
int rdlo, rdhi, rm, rs;
- /* only one format "rdlo, rdhi, rm, rs" */
- while (*str == ' ')
- str++;
+ /* Only one format "rdlo, rdhi, rm, rs" */
+ skip_whitespace (str);
if ((rdlo = reg_required_here (&str, 12)) == FAIL)
{
{
int rd, rm;
- /* only one format "rd, rm, rs" */
- while (*str == ' ')
- str++;
+ /* Only one format "rd, rm, rs" */
+ skip_whitespace (str);
if ((rd = reg_required_here (&str, 16)) == FAIL)
{
{
int rd, rm;
- /* only one format "rd, rm, rs, rn" */
- while (*str == ' ')
- str++;
+ /* Only one format "rd, rm, rs, rn" */
+ skip_whitespace (str);
if ((rd = reg_required_here (&str, 16)) == FAIL)
{
walk_no_bignums (sp)
symbolS * sp;
{
- if (sp->sy_value.X_op == O_big)
+ if (symbol_get_value_expression (sp)->X_op == O_big)
return 1;
- if (sp->sy_value.X_add_symbol)
+ if (symbol_get_value_expression (sp)->X_add_symbol)
{
- return (walk_no_bignums (sp->sy_value.X_add_symbol)
- || (sp->sy_value.X_op_symbol
- && walk_no_bignums (sp->sy_value.X_op_symbol)));
+ return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
+ || (symbol_get_value_expression (sp)->X_op_symbol
+ && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
}
return 0;
char * p;
char c;
- while (**str == ' ')
- (*str)++;
+ skip_whitespace (* str);
for (p = *str; isalpha (*p); p++)
;
return SUCCESS;
}
- while (*p == ' ')
- p++;
-
+ skip_whitespace (p);
+
if (unrestrict && reg_required_here (&p, 8) != FAIL)
{
inst.instruction |= shft->value | SHIFT_BY_REG;
*str = p;
return SUCCESS;
}
- else if (*p == '#')
+ else if (is_immediate_prefix (* p))
{
inst.error = NULL;
p++;
int value;
expressionS expr;
- while (**str == ' ')
- (*str)++;
+ skip_whitespace (* str);
if (reg_required_here (str, 0) != FAIL)
{
if (skip_past_comma (str) == SUCCESS)
- {
- /* Shift operation on register */
- return decode_shift (str, NO_SHIFT_RESTRICT);
- }
+ /* Shift operation on register. */
+ return decode_shift (str, NO_SHIFT_RESTRICT);
+
return SUCCESS;
}
else
{
/* Immediate expression */
- if (*((*str)++) == '#')
+ if (is_immediate_prefix (**str))
{
+ (*str)++;
inst.error = NULL;
+
if (my_get_expression (&inst.reloc.exp, str))
return FAIL;
return SUCCESS;
}
+ (*str)++;
inst.error = _("Register or shift expression expected");
return FAIL;
}
fp_op2 (str)
char ** str;
{
- while (**str == ' ')
- (*str)++;
+ skip_whitespace (* str);
if (fp_reg_required_here (str, 0) != FAIL)
return SUCCESS;
int i;
inst.error = NULL;
- while (**str == ' ')
- (*str)++;
+
+ skip_whitespace (* str);
/* First try and match exact strings, this is to guarantee that
some formats will work even for cross assembly */
char * str;
unsigned long flags;
{
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (reg_required_here (&str, 12) == FAIL
|| skip_past_comma (&str) == FAIL
/* This is a pseudo-op of the form "adr rd, label" to be converted
into a relative address of the form "add rd, pc, #label-.-8" */
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (reg_required_here (&str, 12) == FAIL
|| skip_past_comma (&str) == FAIL
return;
}
+static void
+do_adrl (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ /* This is a pseudo-op of the form "adrl rd, label" to be converted
+ into a relative address of the form:
+ add rd, pc, #low(label-.-8)"
+ add rd, rd, #high(label-.-8)" */
+
+ skip_whitespace (str);
+
+ if (reg_required_here (& str, 12) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || my_get_expression (& inst.reloc.exp, & str))
+ {
+ if (!inst.error)
+ inst.error = bad_args;
+ return;
+ }
+
+ end_of_line (str);
+
+ /* Frag hacking will turn this into a sub instruction if the offset turns
+ out to be negative. */
+ inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
+ inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
+ inst.reloc.pc_rel = 1;
+ inst.instruction |= flags;
+ inst.size = INSN_SIZE * 2;
+
+ return;
+}
+
static void
do_cmp (str, flags)
char * str;
unsigned long flags;
{
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (reg_required_here (&str, 16) == FAIL)
{
char * str;
unsigned long flags;
{
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (reg_required_here (&str, 12) == FAIL)
{
switch (**str)
{
case '#':
+ case '$':
(*str)++;
- if (my_get_expression (&inst.reloc.exp, str))
+ if (my_get_expression (& inst.reloc.exp, str))
return FAIL;
if (inst.reloc.exp.X_op == O_constant)
/* Halfword and signextension instructions have the
immediate value split across bits 11..8 and bits 3..0 */
if (hwse)
- inst.instruction |= add | HWOFFSET_IMM | (value >> 4) << 8 | value & 0xF;
+ inst.instruction |= add | HWOFFSET_IMM | ((value >> 4) << 8) | (value & 0xF);
else
inst.instruction |= add | value;
}
/* This is not ideal, but it is the simplest way of dealing with the
ARM7T halfword instructions (since they use a different
encoding, but the same mnemonic): */
- if (halfword = ((flags & 0x80000000) != 0))
+ halfword = (flags & 0x80000000) != 0;
+ if (halfword)
{
/* This is actually a load/store of a halfword, or a
signed-extension load */
flags = 0;
}
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
- if ((conflict_reg = reg_required_here (&str, 12)) == FAIL)
- return;
+ if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = bad_args;
+ return;
+ }
- if (skip_past_comma (&str) == FAIL)
+ if (skip_past_comma (& str) == FAIL)
{
inst.error = _("Address expected");
return;
int reg;
str++;
- while (*str == ' ')
- str++;
+
+ skip_whitespace (str);
if ((reg = reg_required_here (&str, 16)) == FAIL)
return;
- conflict_reg = (((conflict_reg == reg)
- && (inst.instruction & LOAD_BIT))
- ? 1 : 0);
+ /* Conflicts can occur on stores as well as loads. */
+ conflict_reg = (conflict_reg == reg);
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (*str == ']')
{
- str++;
+ str ++;
+
if (skip_past_comma (&str) == SUCCESS)
{
/* [Rn],... (post inc) */
if (ldst_extend (&str, halfword) == FAIL)
return;
if (conflict_reg)
- as_warn (_("destination register same as write-back base\n"));
+ as_warn (_("%s register same as write-back base"),
+ (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
}
else
{
if (halfword)
inst.instruction |= HWOFFSET_IMM;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (*str == '!')
{
if (conflict_reg)
- as_warn (_("destination register same as write-back base\n"));
+ as_warn (_("%s register same as write-back base"),
+ (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
str++;
inst.instruction |= WRITE_BACK;
}
if (ldst_extend (&str, halfword) == FAIL)
return;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (*str++ != ']')
{
return;
}
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (*str == '!')
{
if (conflict_reg)
- as_tsktsk (_("destination register same as write-back base\n"));
+ as_warn (_("%s register same as write-back base"),
+ (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
str++;
inst.instruction |= WRITE_BACK;
}
/* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
str++;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (my_get_expression (&inst.reloc.exp, &str))
return;
{
int reg;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if ((reg = reg_required_here (& str, -1)) == FAIL)
return FAIL;
} while (skip_past_comma (&str) != FAIL
|| (in_range = 1, *str++ == '-'));
str--;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (*str++ != '}')
{
}
}
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (*str == '|' || *str == '+')
{
int base_reg;
long range;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if ((base_reg = reg_required_here (&str, 16)) == FAIL)
return;
return;
}
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
+
if (*str == '!')
{
flags |= WRITE_BACK;
char * str;
unsigned long flags;
{
+ skip_whitespace (str);
+
/* Allow optional leading '#'. */
- while (*str == ' ')
- str++;
- if (*str == '#')
+ if (is_immediate_prefix (*str))
str++;
- if (my_get_expression (&inst.reloc.exp, &str))
+ if (my_get_expression (& inst.reloc.exp, & str))
return;
inst.reloc.type = BFD_RELOC_ARM_SWI;
inst.reloc.pc_rel = 0;
inst.instruction |= flags;
+
end_of_line (str);
+
return;
}
{
int reg;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if ((reg = reg_required_here (&str, 12)) == FAIL)
return;
return;
}
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if ((reg = reg_required_here (&str, 16)) == FAIL)
return;
return;
}
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (*str++ != ']')
{
{
if (my_get_expression (&inst.reloc.exp, &str))
return;
- inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
+
+#ifdef OBJ_ELF
+ {
+ char * save_in;
+
+ /* ScottB: February 5, 1998 */
+ /* Check to see of PLT32 reloc required for the instruction. */
+
+ /* arm_parse_reloc() works on input_line_pointer.
+ We actually want to parse the operands to the branch instruction
+ passed in 'str'. Save the input pointer and restore it later. */
+ save_in = input_line_pointer;
+ input_line_pointer = str;
+ if (inst.reloc.exp.X_op == O_symbol
+ && *str == '('
+ && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
+ {
+ inst.reloc.type = BFD_RELOC_ARM_PLT32;
+ inst.reloc.pc_rel = 0;
+ /* Modify str to point to after parsed operands, otherwise
+ end_of_line() will complain about the (PLT) left in str. */
+ str = input_line_pointer;
+ }
+ else
+ {
+ inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
+ inst.reloc.pc_rel = 1;
+ }
+ input_line_pointer = save_in;
+ }
+#else
+ inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
inst.reloc.pc_rel = 1;
+#endif /* OBJ_ELF */
+
end_of_line (str);
return;
}
{
int reg;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if ((reg = reg_required_here (&str, 0)) == FAIL)
return;
{
/* Co-processor data operation.
Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (co_proc_number (&str) == FAIL)
{
/* Co-processor register load/store.
Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (co_proc_number (&str) == FAIL)
{
/* Co-processor register transfer.
Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (co_proc_number (&str) == FAIL)
{
/* FP control registers.
Format: <WFS|RFS|WFC|RFC>{cond} Rn */
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (reg_required_here (&str, 12) == FAIL)
{
char * str;
unsigned long flags;
{
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
switch (inst.suffix)
{
{
int num_regs;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (fp_reg_required_here (&str, 12) == FAIL)
{
}
str++;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if ((reg = reg_required_here (&str, 16)) == FAIL)
return;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (*str != ']')
{
char * str;
unsigned long flags;
{
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
switch (inst.suffix)
{
char * str;
unsigned long flags;
{
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
switch (inst.suffix)
{
char * str;
unsigned long flags;
{
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (fp_reg_required_here (&str, 16) == FAIL)
{
char * str;
unsigned long flags;
{
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
switch (inst.suffix)
{
char * str;
unsigned long flags;
{
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (reg_required_here (&str, 12) == FAIL)
return;
{
int Rd, Rs, Rn = FAIL;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
|| skip_past_comma (&str) == FAIL)
return;
}
- if (*str == '#')
+ if (is_immediate_prefix (*str))
{
Rs = Rd;
str++;
Rn = Rs;
Rs = Rd;
}
- else if (*str == '#')
+ else if (is_immediate_prefix (*str))
{
str++;
if (my_get_expression (&inst.reloc.exp, &str))
{
int Rd, Rs, Rn = FAIL;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
|| skip_past_comma (&str) == FAIL)
return;
}
- if (*str == '#')
+ if (is_immediate_prefix (*str))
{
/* Two operand immediate format, set Rs to Rd. */
Rs = Rd;
Rn = Rs;
Rs = Rd;
}
- else if (*str == '#')
+ else if (is_immediate_prefix (*str))
{
str++;
if (my_get_expression (&inst.reloc.exp, &str))
{
int Rd, Rs = FAIL;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
|| skip_past_comma (&str) == FAIL)
return;
}
- if (*str == '#')
+ if (is_immediate_prefix (*str))
{
str++;
if (my_get_expression (&inst.reloc.exp, &str))
{
int Rd, Rb, Ro = FAIL;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
|| skip_past_comma (&str) == FAIL)
if (skip_past_comma (&str) != FAIL)
{
- if (*str == '#')
+ if (is_immediate_prefix (*str))
{
str++;
if (my_get_expression (&inst.reloc.exp, &str))
/* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
str++;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (my_get_expression (& inst.reloc.exp, & str))
return;
{
int Rd, Rs, Rn;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
return;
const char * name = S_GET_NAME (symbolP);
symbolS * new_target;
- /* This definitonmust agree with the one in gcc/config/arm/thumb.c */
+ /* This definiton must agree with the one in gcc/config/arm/thumb.c */
#define STUB_NAME ".real_start_of"
if (name == NULL)
do_t_branch23 (str)
char * str;
{
- if (my_get_expression (&inst.reloc.exp, &str))
+ if (my_get_expression (& inst.reloc.exp, & str))
return;
+
inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
inst.reloc.pc_rel = 1;
end_of_line (str);
{
int reg;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
return;
int Rb;
long range;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
return;
{
int Rd, Rb, Ro;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
|| skip_past_comma (&str) == FAIL
{
long range;
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if ((range = reg_list (&str)) == FAIL)
{
do_t_swi (str)
char * str;
{
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (my_get_expression (&inst.reloc.exp, &str))
return;
{
/* This is a pseudo-op of the form "adr rd, label" to be converted
into a relative address of the form "add rd, pc, #label-.-4" */
- while (*str == ' ')
- str++;
+ skip_whitespace (str);
if (reg_required_here (&str, 4) == FAIL /* Store Rd in temporary location inside instruction. */
|| skip_past_comma (&str) == FAIL
{
int i;
- if ((arm_ops_hsh = hash_new ()) == NULL
+ if ( (arm_ops_hsh = hash_new ()) == NULL
|| (arm_tops_hsh = hash_new ()) == NULL
|| (arm_cond_hsh = hash_new ()) == NULL
|| (arm_shift_hsh = hash_new ()) == NULL
if (support_interwork) flags |= F_INTERWORK;
if (uses_apcs_float) flags |= F_APCS_FLOAT;
if (pic_code) flags |= F_PIC;
+ if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT;
bfd_set_private_flags (stdoutput, flags);
}
break;
}
- /* Catch special cases */
+ /* Catch special cases. */
if (cpu_variant != (FPU_DEFAULT | CPU_DEFAULT))
{
- if (cpu_variant & ARM_THUMB)
+ if (cpu_variant & (ARM_EXT_V5 & ARM_THUMB))
+ mach = bfd_mach_arm_5T;
+ else if (cpu_variant & ARM_EXT_V5)
+ mach = bfd_mach_arm_5;
+ else if (cpu_variant & ARM_THUMB)
mach = bfd_mach_arm_4T;
- else if ((cpu_variant & ARM_ARCHv4) == ARM_ARCHv4)
+ else if ((cpu_variant & ARM_ARCH_V4) == ARM_ARCH_V4)
mach = bfd_mach_arm_4;
else if (cpu_variant & ARM_LONGMUL)
mach = bfd_mach_arm_3M;
This knows about the endian-ness of the target machine and does
THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
2 (short) and 4 (long) Floating numbers are put out as a series of
- LITTLENUMS (shorts, here at least)
- */
+ LITTLENUMS (shorts, here at least). */
void
md_number_to_chars (buf, val, n)
char * buf;
static valueT
md_chars_to_number (buf, n)
- char *buf;
+ char * buf;
int n;
{
valueT result = 0;
- unsigned char *where = (unsigned char *) buf;
+ unsigned char * where = (unsigned char *) buf;
if (target_big_endian)
{
return 0;
}
-/* The knowledge of the PC's pipeline offset is built into the relocs
- for the ELF port and into the insns themselves for the COFF port. */
+/* The knowledge of the PC's pipeline offset is built into the insns themselves. */
long
md_pcrel_from (fixP)
fixS * fixP;
{
/* PC relative addressing on the Thumb is slightly odd
as the bottom two bits of the PC are forced to zero
- for the calculation */
+ for the calculation. */
return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
}
-
+
return fixP->fx_where + fixP->fx_frag->fr_address;
}
valueT size;
{
#ifdef OBJ_ELF
- /* Don't align the dwarf2 debug sections */
- if (!strncmp (segment->name, ".debug", 5))
- return size;
-#endif
+ return size;
+#else
/* Round all sects to multiple of 4 */
return (size + 3) & ~3;
+#endif
}
-/* We have no need to default values of symbols. */
+/* Under ELF we need to default _GLOBAL_OFFSET_TABLE. Otherwise
+ we have no need to default values of symbols. */
/* ARGSUSED */
symbolS *
md_undefined_symbol (name)
char * name;
{
+#ifdef OBJ_ELF
+ if (name[0] == '_' && name[1] == 'G'
+ && streq (name, GLOBAL_OFFSET_TABLE_NAME))
+ {
+ if (!GOT_symbol)
+ {
+ if (symbol_find (name))
+ as_bad ("GOT already in the symbol table");
+
+ GOT_symbol = symbol_new (name, undefined_section,
+ (valueT)0, & zero_address_frag);
+ }
+
+ return GOT_symbol;
+ }
+#endif
+
return 0;
}
/* Note whether this will delete the relocation. */
#if 0 /* patch from REarnshaw to JDavis (disabled for the moment, since it doesn't work fully) */
- if ((fixP->fx_addsy == 0 || fixP->fx_addsy->sy_value.X_op == O_constant)
+ if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
&& !fixP->fx_pcrel)
#else
if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
&& S_IS_DEFINED (fixP->fx_addsy)
&& S_GET_SEGMENT (fixP->fx_addsy) != seg)
{
- if (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH)
+ if (target_oabi
+ && fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH)
value = 0;
else
value += md_pcrel_from (fixP);
}
}
- fixP->fx_addnumber = value; /* Remember value for emit_reloc */
+ fixP->fx_addnumber = value; /* Remember value for emit_reloc. */
switch (fixP->fx_r_type)
{
&& (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
{
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("invalid constant after fixup\n"));
+ _("invalid constant (%lx) after fixup"),
+ (unsigned long) value);
break;
}
md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
break;
- case BFD_RELOC_ARM_OFFSET_IMM:
+ case BFD_RELOC_ARM_ADRL_IMMEDIATE:
+ {
+ unsigned int highpart = 0;
+ unsigned int newinsn = 0xe1a00000; /* nop */
+ newimm = validate_immediate (value);
+ temp = md_chars_to_number (buf, INSN_SIZE);
+
+ /* If the instruction will fail, see if we can fix things up by
+ changing the opcode. */
+ if (newimm == (unsigned int) FAIL
+ && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
+ {
+ /* No ? OK - try using two ADD instructions to generate the value. */
+ newimm = validate_immediate_twopart (value, & highpart);
+
+ /* Yes - then make sure that the second instruction is also an add. */
+ if (newimm != (unsigned int) FAIL)
+ newinsn = temp;
+ /* Still No ? Try using a negated value. */
+ else if (validate_immediate_twopart (- value, & highpart) != (unsigned int) FAIL)
+ temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
+ /* Otherwise - give up. */
+ else
+ {
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("Unable to compute ADRL instructions for PC offset of 0x%x"), value);
+ break;
+ }
+
+ /* Replace the first operand in the 2nd instruction (which is the PC)
+ with the destination register. We have already added in the PC in the
+ first instruction and we do not want to do it again. */
+ newinsn &= ~ 0xf0000;
+ newinsn |= ((newinsn & 0x0f000) << 4);
+ }
+
+ newimm |= (temp & 0xfffff000);
+ md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
+
+ highpart |= (newinsn & 0xfffff000);
+ md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
+ }
+ break;
+
+ case BFD_RELOC_ARM_OFFSET_IMM:
sign = value >= 0;
- if ((value = validate_offset_imm (value, 0)) == FAIL)
+
+ if (value < 0)
+ value = - value;
+
+ if (validate_offset_imm (value, 0) == FAIL)
{
- as_bad (_("bad immediate value for offset (%d)"), val);
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("bad immediate value for offset (%ld)"), (long) value);
break;
}
- if (value < 0)
- value = -value;
newval = md_chars_to_number (buf, INSN_SIZE);
newval &= 0xff7ff000;
case BFD_RELOC_ARM_OFFSET_IMM8:
case BFD_RELOC_ARM_HWLITERAL:
sign = value >= 0;
- if ((value = validate_offset_imm (value, 1)) == FAIL)
+
+ if (value < 0)
+ value = - value;
+
+ if (validate_offset_imm (value, 1) == FAIL)
{
if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("invalid literal constant: pool needs to be closer\n"));
+ _("invalid literal constant: pool needs to be closer"));
else
- as_bad (_("bad immediate value for offset (%d)"), value);
+ as_bad (_("bad immediate value for half-word offset (%ld)"),
+ (long) value);
break;
}
- if (value < 0)
- value = -value;
-
newval = md_chars_to_number (buf, INSN_SIZE);
newval &= 0xff7ff0f0;
- newval |= ((value >> 4) << 8) | value & 0xf | (sign ? INDEX_UP : 0);
+ newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
md_number_to_chars (buf, newval, INSN_SIZE);
break;
case BFD_RELOC_ARM_LITERAL:
sign = value >= 0;
+
if (value < 0)
- value = -value;
+ value = - value;
- if ((value = validate_offset_imm (value, 0)) == FAIL)
+ if (validate_offset_imm (value, 0) == FAIL)
{
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("invalid literal constant: pool needs to be closer\n"));
+ _("invalid literal constant: pool needs to be closer"));
break;
}
case BFD_RELOC_ARM_PCREL_BRANCH:
newval = md_chars_to_number (buf, INSN_SIZE);
+
#ifdef OBJ_ELF
- newval &= 0xff000000;
if (! target_oabi)
value = fixP->fx_offset;
- else
-#else
- value = (value >> 2) & 0x00ffffff;
#endif
+ value = (value >> 2) & 0x00ffffff;
value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
newval = value | (newval & 0xff000000);
md_number_to_chars (buf, newval, INSN_SIZE);
diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
if (diff & 0x400000)
diff |= ~0x3fffff;
+#ifdef OBJ_ELF
+ value = fixP->fx_offset;
+#endif
value += diff;
if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
as_bad_where (fixP->fx_file, fixP->fx_line,
#endif
break;
+#ifdef OBJ_ELF
+ case BFD_RELOC_ARM_GOT32:
+ case BFD_RELOC_ARM_GOTOFF:
+ md_number_to_chars (buf, 0, 4);
+ break;
+#endif
+
case BFD_RELOC_RVA:
case BFD_RELOC_32:
if (fixP->fx_done || fixP->fx_pcrel)
#endif
break;
+#ifdef OBJ_ELF
+ case BFD_RELOC_ARM_PLT32:
+ /* It appears the instruction is fully prepared at this point. */
+ break;
+#endif
+
+ case BFD_RELOC_ARM_GOTPC:
+ md_number_to_chars (buf, value, 4);
+ break;
+
case BFD_RELOC_ARM_CP_OFF_IMM:
sign = value >= 0;
if (value < -1023 || value > 1023 || (value & 3))
if ((value + 2) & ~0x3fe)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset"));
+ _("Invalid offset, value too big (0x%08X)"), value);
/* Round up, since pc will be rounded down. */
newval |= (value + 2) >> 2;
case 9: /* SP load/store */
if (value & ~0x3fc)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset"));
+ _("Invalid offset, value too big (0x%08X)"), value);
newval |= value >> 2;
break;
case 6: /* Word load/store */
if (value & ~0x7c)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset"));
+ _("Invalid offset, value too big (0x%08X)"), value);
newval |= value << 4; /* 6 - 2 */
break;
case 7: /* Byte load/store */
if (value & ~0x1f)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset"));
+ _("Invalid offset, value too big (0x%08X)"), value);
newval |= value << 6;
break;
case 8: /* Halfword load/store */
if (value & ~0x3e)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset"));
+ _("Invalid offset, value too big (0x%08X)"), value);
newval |= value << 5; /* 6 - 1 */
break;
default:
as_bad_where (fixP->fx_file, fixP->fx_line,
- "Unable to process relocation for thumb opcode: %x", newval);
+ "Unable to process relocation for thumb opcode: %lx",
+ (unsigned long) newval);
break;
}
md_number_to_chars (buf, newval, THUMB_SIZE);
if (subtract ||
value & ~0x3fc)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid immediate for address calculation (value = 0x%08X)"), value);
+ _("Invalid immediate for address calculation (value = 0x%08lX)"),
+ (unsigned long) value);
newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
newval |= rd << 8;
newval |= value >> 2;
case 0x05: /* 8bit immediate CMP */
if (value < 0 || value > 255)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid immediate: %d is too large"), value);
+ _("Invalid immediate: %ld is too large"),
+ (long) value);
newval |= value;
break;
/* 5bit shift value (0..31) */
if (value < 0 || value > 31)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Illegal Thumb shift value: %d"), value);
+ _("Illegal Thumb shift value: %ld"), (long) value);
newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
newval |= value << 6;
md_number_to_chars (buf, newval , THUMB_SIZE);
case BFD_RELOC_NONE:
default:
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Bad relocation fixup type (%d)\n"), fixP->fx_r_type);
+ _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
}
return 1;
reloc = (arelent *) xmalloc (sizeof (arelent));
- reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
+ reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+ *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
/* @@ Why fx_addnumber sometimes and fx_offset other times? */
case BFD_RELOC_ARM_LITERAL:
case BFD_RELOC_ARM_HWLITERAL:
/* If this is called then the a literal has been referenced across
- a section boundry - possibly due to an implicit dump */
+ a section boundary - possibly due to an implicit dump */
as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Literal referenced across section boundry (Implicit dump?)"));
+ _("Literal referenced across section boundary (Implicit dump?)"));
return NULL;
+#ifdef OBJ_ELF
+ case BFD_RELOC_ARM_GOT32:
+ case BFD_RELOC_ARM_GOTOFF:
+ case BFD_RELOC_ARM_PLT32:
+ code = fixp->fx_r_type;
+ break;
+#endif
+
case BFD_RELOC_ARM_IMMEDIATE:
as_bad_where (fixp->fx_file, fixp->fx_line,
_("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
fixp->fx_r_type);
return NULL;
+ case BFD_RELOC_ARM_ADRL_IMMEDIATE:
+ as_bad_where (fixp->fx_file, fixp->fx_line,
+ _("ADRL used for a symbol not defined in the same file"),
+ fixp->fx_r_type);
+ return NULL;
+
case BFD_RELOC_ARM_OFFSET_IMM:
as_bad_where (fixp->fx_file, fixp->fx_line,
_("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
- default: type = "<unknown>"; break;
+ default: type = _("<unknown>"); break;
}
as_bad_where (fixp->fx_file, fixp->fx_line,
_("Can not represent %s relocation in this object file format (%d)"),
}
}
+#ifdef OBJ_ELF
+ if (code == BFD_RELOC_32_PCREL
+ && GOT_symbol
+ && fixp->fx_addsy == GOT_symbol)
+ {
+ code = BFD_RELOC_ARM_GOTPC;
+ reloc->addend = fixp->fx_offset = reloc->address;
+ }
+#endif
+
reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
if (reloc->howto == NULL)
return NULL;
}
+ /* HACK: Since arm ELF uses Rel instead of Rela, encode the
+ vtable entry to be used in the relocation's section offset. */
+ if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
+ reloc->address = fixp->fx_offset;
+
return reloc;
}
}
static void
-output_inst (str)
- char * str;
+output_inst PARAMS ((void))
{
char * to = NULL;
}
to = frag_more (inst.size);
+
if (thumb_mode && (inst.size > THUMB_SIZE))
{
assert (inst.size == (2 * THUMB_SIZE));
md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
- md_number_to_chars (to + 2, inst.instruction, THUMB_SIZE);
+ md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
+ }
+ else if (inst.size > INSN_SIZE)
+ {
+ assert (inst.size == (2 * INSN_SIZE));
+ md_number_to_chars (to, inst.instruction, INSN_SIZE);
+ md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
}
else
md_number_to_chars (to, inst.instruction, inst.size);
/* Align the previous label if needed. */
if (last_label_seen != NULL)
{
- last_label_seen->sy_frag = frag_now;
+ symbol_set_frag (last_label_seen, frag_now);
S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
S_SET_SEGMENT (last_label_seen, now_seg);
}
memset (&inst, '\0', sizeof (inst));
inst.reloc.type = BFD_RELOC_NONE;
- if (*str == ' ')
- str++; /* Skip leading white space */
-
+ skip_whitespace (str);
+
/* Scan up to the end of the op-code, which must end in white space or
end of string. */
for (start = p = str; *p != '\0'; p++)
if (thumb_mode)
{
- CONST struct thumb_opcode *opcode;
+ CONST struct thumb_opcode * opcode;
c = *p;
*p = '\0';
opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
*p = c;
+
if (opcode)
{
inst.instruction = opcode->value;
inst.size = opcode->size;
(*opcode->parms)(p);
- output_inst (start);
+ output_inst ();
return;
}
}
else
{
- CONST struct asm_opcode *opcode;
+ CONST struct asm_opcode * opcode;
inst.size = INSN_SIZE;
/* p now points to the end of the opcode, probably white space, but we
have to break the opcode up in case it contains condionals and flags;
keep trying with progressively smaller basic instructions until one
- matches, or we run out of opcode. */
+ matches, or we run out of opcode. */
q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
for (; q != str; q--)
{
*q = '\0';
opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
*q = c;
+
if (opcode && opcode->template)
{
unsigned long flag_bits = 0;
- char *r;
+ char * r;
- /* Check that this instruction is supported for this CPU */
+ /* Check that this instruction is supported for this CPU. */
if ((opcode->variants & cpu_variant) == 0)
goto try_shorter;
inst.instruction = opcode->value;
- if (q == p) /* Just a simple opcode */
+ if (q == p) /* Just a simple opcode. */
{
if (opcode->comp_suffix != 0)
as_bad (_("Opcode `%s' must have suffix from <%s>\n"), str,
inst.instruction |= COND_ALWAYS;
(*opcode->parms)(q, 0);
}
- output_inst (start);
+ output_inst ();
return;
}
- /* Now check for a conditional */
+ /* Now check for a conditional. */
r = q;
if (p - r >= 2)
{
else
inst.instruction |= COND_ALWAYS;
- /* if there is a compulsory suffix, it should come here, before
- any optional flags. */
+ /* If there is a compulsory suffix, it should come here, before
+ any optional flags. */
if (opcode->comp_suffix)
{
CONST char *s = opcode->comp_suffix;
for (flagno = 0; flag[flagno].template; flagno++)
{
- if (! strcmp (r, flag[flagno].template))
+ if (streq (r, flag[flagno].template))
{
flag_bits |= flag[flagno].set_bits;
break;
}
(*opcode->parms) (p, flag_bits);
- output_inst (start);
+ output_inst ();
return;
}
}
/* It wasn't an instruction, but it might be a register alias of the form
- alias .req reg
- */
+ alias .req reg */
q = p;
- while (*q == ' ')
- q++;
+ skip_whitespace (q);
c = *p;
*p = '\0';
char * r;
q += 4;
- while (*q == ' ')
- q++;
+ skip_whitespace (q);
for (r = q; *r != '\0'; r++)
if (*r == ' ')
if (reg == FAIL)
{
if (regnum != FAIL)
- {
- insert_reg_alias (str, regnum);
- }
+ insert_reg_alias (str, regnum);
else
- {
- as_warn (_("register '%s' does not exist\n"), q);
- }
+ as_warn (_("register '%s' does not exist"), q);
}
else if (regnum != FAIL)
{
if (reg != regnum)
as_warn (_("ignoring redefinition of register alias '%s'"), copy_of_str );
- /* Do not warn abpout redefinitions to the same alias. */
+ /* Do not warn about redefinitions to the same alias. */
}
else
as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
* -m[arm]3 Arm 3 processor
* -m[arm]6[xx], Arm 6 processors
* -m[arm]7[xx][t][[d]m] Arm 7 processors
- * -mstrongarm[110] Arm 8 processors
+ * -m[arm]8[10] Arm 8 processors
+ * -m[arm]9[20][tdmi] Arm 9 processors
+ * -mstrongarm[110[0]] StrongARM processors
+ * -m[arm]v[2345] Arm architecures
* -mall All (except the ARM1)
* FP variants:
* -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
* -moabi Old ELF ABI
*/
-CONST char * md_shortopts = "m:";
+CONST char * md_shortopts = "m:k";
struct option md_longopts[] =
{
#ifdef ARM_BI_ENDIAN
switch (*str)
{
case 'f':
- if (! strcmp (str, "fpa10"))
+ if (streq (str, "fpa10"))
cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
- else if (! strcmp (str, "fpa11"))
+ else if (streq (str, "fpa11"))
cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
- else if (! strcmp (str, "fpe-old"))
+ else if (streq (str, "fpe-old"))
cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
else
goto bad;
break;
case 'n':
- if (! strcmp (str, "no-fpu"))
+ if (streq (str, "no-fpu"))
cpu_variant &= ~FPU_ALL;
break;
#ifdef OBJ_ELF
case 'o':
- if (!strcmp (str, "oabi"))
+ if (streq (str, "oabi"))
target_oabi = true;
break;
#endif
case 't':
/* Limit assembler to generating only Thumb instructions: */
- if (! strcmp (str, "thumb"))
+ if (streq (str, "thumb"))
{
cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB;
cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
thumb_mode = 1;
}
- else if (! strcmp (str, "thumb-interwork"))
+ else if (streq (str, "thumb-interwork"))
{
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB | ARM_ARCHv4;
+ cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB | ARM_ARCH_V4;
#if defined OBJ_COFF || defined OBJ_ELF
support_interwork = true;
#endif
break;
default:
- if (! strcmp (str, "all"))
+ if (streq (str, "all"))
{
cpu_variant = ARM_ALL | FPU_ALL;
return 1;
str += 5;
- if (! strcmp (str, "32"))
+ if (streq (str, "32"))
{
uses_apcs_26 = false;
return 1;
}
- else if (! strcmp (str, "26"))
+ else if (streq (str, "26"))
{
uses_apcs_26 = true;
return 1;
}
- else if (! strcmp (str, "frame"))
+ else if (streq (str, "frame"))
{
/* Stack frames are being generated - does not affect
linkage of code. */
return 1;
}
- else if (! strcmp (str, "stack-check"))
+ else if (streq (str, "stack-check"))
{
/* Stack checking is being performed - does not affect
linkage, but does require that the functions
return 1;
}
- else if (! strcmp (str, "float"))
+ else if (streq (str, "float"))
{
/* Floating point arguments are being passed in the floating
point registers. This does affect linking, since this
uses_apcs_float = true;
return 1;
}
- else if (! strcmp (str, "reentrant"))
+ else if (streq (str, "reentrant"))
{
/* Reentrant code has been generated. This does affect
linking, since there is no point in linking reentrant/
switch (*str)
{
case '1':
- if (! strcmp (str, "1"))
+ if (streq (str, "1"))
cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
else
goto bad;
break;
case '2':
- if (! strcmp (str, "2"))
+ if (streq (str, "2"))
cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
- else if (! strcmp (str, "250"))
+ else if (streq (str, "250"))
cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
else
goto bad;
break;
case '3':
- if (! strcmp (str, "3"))
+ if (streq (str, "3"))
cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
else
goto bad;
break;
- case 's':
- if (! strcmp (str, "strongarm") || ! strcmp (str, "strongarm110"))
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7 | ARM_ARCHv4 | ARM_LONGMUL;
- else
- goto bad;
- break;
-
- case '8':
- if (! strcmp (str, "8"))
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7 | ARM_ARCHv4 | ARM_LONGMUL;
- else
- goto bad;
- break;
-
+ case '6':
switch (strtol (str, NULL, 10))
{
case 6:
switch (* str)
{
case 't':
- cpu_variant |= (ARM_THUMB | ARM_ARCHv4);
+ cpu_variant |= (ARM_THUMB | ARM_ARCH_V4);
break;
case 'm':
else
goto bad;
- case 'c': /* Unknown */
- case 'd': /* debug */
- case 'i': /* embedded ice */
+ case 'c': /* Left over from 710c processor name. */
+ case 'd': /* Debug */
+ case 'i': /* Embedded ICE */
/* Included for completeness in ARM processor naming. */
break;
}
break;
+ case '8':
+ if (streq (str, "8") || streq (str, "810"))
+ cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
+ else
+ goto bad;
+ break;
+
+ case '9':
+ if (streq (str, "9"))
+ cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
+ else if (streq (str, "920"))
+ cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL;
+ else if (streq (str, "920t"))
+ cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
+ else if (streq (str, "9tdmi"))
+ cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
+ else
+ goto bad;
+ break;
+
+ case 's':
+ if (streq (str, "strongarm")
+ || streq (str, "strongarm110")
+ || streq (str, "strongarm1100"))
+ cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
+ else
+ goto bad;
+ break;
+
case 'v':
/* Select variant based on architecture rather than processor */
switch (*++str)
break;
case '4':
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCHv4;
+ cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4;
+
+ switch (*++str)
+ {
+ case 't': cpu_variant |= ARM_THUMB; break;
+ case 0: break;
+ default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
+ }
+ break;
+
+ case '5':
+ cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V5;
switch (*++str)
{
}
break;
+ case 'k':
+ pic_code = 1;
+ break;
+
default:
return 0;
}
_("\
ARM Specific Assembler Options:\n\
-m[arm][<processor name>] select processor variant\n\
- -m[arm]v[2|2a|3|3m|4|4t] select architecture variant\n\
+ -m[arm]v[2|2a|3|3m|4|4t|5]select architecture variant\n\
-mthumb only allow Thumb instructions\n\
-mthumb-interwork mark the assembled code as supporting interworking\n\
-mall allow any instruction\n\
-mfpa10, -mfpa11 select floating point architecture\n\
-mfpe-old don't allow floating-point multiple instructions\n\
-mno-fpu don't allow any floating-point instructions.\n"));
+ fprintf (fp,
+_("\
+ -k generate PIC code.\n"));
#if defined OBJ_COFF || defined OBJ_ELF
fprintf (fp,
_("\
}
/* Mark whether the fix is to a THUMB instruction, or an ARM instruction */
- arm_data = (arm_fix_data *) obstack_alloc (¬es, sizeof (arm_fix_data));
+ arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
new_fix->tc_fix_data = (PTR) arm_data;
arm_data->thumb_mode = thumb_mode;
return;
}
-/* A good place to do this, although this was probably not intended
- * for this kind of use. We need to dump the literal pool before
- * references are made to a null symbol pointer. */
+
+/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
void
-arm_cleanup ()
+cons_fix_new_arm (frag, where, size, exp)
+ fragS * frag;
+ int where;
+ int size;
+ expressionS * exp;
{
- if (current_poolP != NULL)
+ bfd_reloc_code_real_type type;
+ int pcrel = 0;
+
+ /* Pick a reloc ...
+ *
+ * @@ Should look at CPU word size.
+ */
+ switch (size)
{
- subseg_set (text_section, 0); /* Put it at the end of text section */
- s_ltorg (0);
- listing_prev_line ();
+ case 2:
+ type = BFD_RELOC_16;
+ break;
+ case 4:
+ default:
+ type = BFD_RELOC_32;
+ break;
+ case 8:
+ type = BFD_RELOC_64;
+ break;
}
+
+ fix_new_exp (frag, where, (int) size, exp, pcrel, type);
+}
+
+/* A good place to do this, although this was probably not intended
+ for this kind of use. We need to dump the literal pool before
+ references are made to a null symbol pointer. */
+void
+arm_cleanup ()
+{
+ if (current_poolP == NULL)
+ return;
+
+ subseg_set (text_section, 0); /* Put it at the end of text section. */
+ s_ltorg (0);
+ listing_prev_line ();
}
void
}
if (ARM_IS_INTERWORK (sym))
- coffsymbol(sym->bsym)->native->u.syment.n_flags = 0xFF;
+ coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
}
#endif
#ifdef OBJ_ELF
{
if (THUMB_IS_FUNC (sym))
{
- elf_sym = elf_symbol (sym->bsym);
+ elf_sym = elf_symbol (symbol_get_bfdsym (sym));
bind = ELF_ST_BIND (elf_sym);
elf_sym->internal_elf_sym.st_info = ELF_ST_INFO (bind, STT_ARM_TFUNC);
}
int len;
if (thumb_mode && (len = strlen (name)) > 5
- && ! strcmp (name + len - 5, "/data"))
- {
- *(name + len - 5) = 0;
- }
+ && streq (name + len - 5, "/data"))
+ *(name + len - 5) = 0;
return name;
}
arm_fix_adjustable (fixP)
fixS * fixP;
{
-
if (fixP->fx_addsy == NULL)
return 1;
{
if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
- || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH)
+ || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
+ || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
return 1;
return 0;
}
-#endif /* OBJ_ELF */
+static bfd_reloc_code_real_type
+arm_parse_reloc ()
+{
+ char id[16];
+ char * ip;
+ int i;
+ static struct
+ {
+ char * str;
+ int len;
+ bfd_reloc_code_real_type reloc;
+ }
+ reloc_map[] =
+ {
+#define MAP(str,reloc) { str, sizeof (str)-1, reloc }
+ MAP ("(got)", BFD_RELOC_ARM_GOT32),
+ MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
+ /* ScottB: Jan 30, 1998 */
+ /* Added support for parsing "var(PLT)" branch instructions */
+ /* generated by GCC for PLT relocs */
+ MAP ("(plt)", BFD_RELOC_ARM_PLT32),
+ NULL, 0, BFD_RELOC_UNUSED
+#undef MAP
+ };
+
+ for (i = 0, ip = input_line_pointer;
+ i < sizeof (id) && (isalnum (*ip) || ispunct (*ip));
+ i++, ip++)
+ id[i] = tolower (*ip);
+
+ for (i = 0; reloc_map[i].str; i++)
+ if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
+ break;
+
+ input_line_pointer += reloc_map[i].len;
+
+ return reloc_map[i].reloc;
+}
+
+static void
+s_arm_elf_cons (nbytes)
+ int nbytes;
+{
+ expressionS exp;
+#ifdef md_flush_pending_output
+ md_flush_pending_output ();
+#endif
+
+ if (is_it_end_of_statement ())
+ {
+ demand_empty_rest_of_line ();
+ return;
+ }
+
+#ifdef md_cons_align
+ md_cons_align (nbytes);
+#endif
+
+ do
+ {
+ bfd_reloc_code_real_type reloc;
+
+ expression (& exp);
+
+ if (exp.X_op == O_symbol
+ && * input_line_pointer == '('
+ && (reloc = arm_parse_reloc()) != BFD_RELOC_UNUSED)
+ {
+ reloc_howto_type * howto = bfd_reloc_type_lookup (stdoutput, reloc);
+ int size = bfd_get_reloc_size (howto);
+
+ if (size > nbytes)
+ as_bad ("%s relocations do not fit in %d bytes", howto->name, nbytes);
+ else
+ {
+ register char * p = frag_more ((int) nbytes);
+ int offset = nbytes - size;
+
+ fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
+ & exp, 0, reloc);
+ }
+ }
+ else
+ emit_expr (& exp, (unsigned int) nbytes);
+ }
+ while (*input_line_pointer++ == ',');
+
+ input_line_pointer--; /* Put terminator back into stream. */
+ demand_empty_rest_of_line ();
+}
+
+#endif /* OBJ_ELF */
projects / deliverable / binutils-gdb.git / blobdiff