static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7);
static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);
static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
+static const arm_feature_set arm_ext_v8r = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R);
#ifdef OBJ_ELF
static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
#endif
MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without
a predication code. */
MVE_UNPREDICABLE_INSN, /* MVE instruction that is non-predicable. */
- NEUTRAL_IT_NO_VPT_INSN, /* Instruction that can be either inside or outside
- an IT block, but must not be in a VPT block. */
};
/* The maximum number of operands we need. */
[REG_TYPE_MMXWCG] = N_("iWMMXt scalar register expected"),
[REG_TYPE_XSCALE] = N_("XScale accumulator register expected"),
[REG_TYPE_MQ] = N_("MVE vector register expected"),
- [REG_TYPE_RNB] = N_("")
+ [REG_TYPE_RNB] = ""
};
/* Some well known registers that we refer to directly elsewhere. */
#define BAD_EL_TYPE _("bad element type for instruction")
#define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
-static struct hash_control * arm_ops_hsh;
-static struct hash_control * arm_cond_hsh;
-static struct hash_control * arm_vcond_hsh;
-static struct hash_control * arm_shift_hsh;
-static struct hash_control * arm_psr_hsh;
-static struct hash_control * arm_v7m_psr_hsh;
-static struct hash_control * arm_reg_hsh;
-static struct hash_control * arm_reloc_hsh;
-static struct hash_control * arm_barrier_opt_hsh;
+static htab_t arm_ops_hsh;
+static htab_t arm_cond_hsh;
+static htab_t arm_vcond_hsh;
+static htab_t arm_shift_hsh;
+static htab_t arm_psr_hsh;
+static htab_t arm_v7m_psr_hsh;
+static htab_t arm_reg_hsh;
+static htab_t arm_reloc_hsh;
+static htab_t arm_barrier_opt_hsh;
/* Stuff needed to resolve the label ambiguity
As:
p++;
while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
- reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
+ reg = (struct reg_entry *) str_hash_find_n (arm_reg_hsh, start, p - start);
if (!reg)
return NULL;
return -1;
if ((r = (struct reloc_entry *)
- hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
+ str_hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
return -1;
*str = q + 1;
struct reg_entry *new_reg;
const char *name;
- if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
+ if ((new_reg = (struct reg_entry *) str_hash_find (arm_reg_hsh, str)) != 0)
{
if (new_reg->builtin)
as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
new_reg->builtin = FALSE;
new_reg->neon = NULL;
- if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
- abort ();
+ str_hash_insert (arm_reg_hsh, name, new_reg);
return new_reg;
}
if (*oldname == '\0')
return FALSE;
- old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
+ old = (struct reg_entry *) str_hash_find (arm_reg_hsh, oldname);
if (!old)
{
as_warn (_("unknown register '%s' -- .req ignored"), oldname);
as_bad (_("invalid syntax for .unreq directive"));
else
{
- struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
+ struct reg_entry *reg = (struct reg_entry *) str_hash_find (arm_reg_hsh,
name);
if (!reg)
char * p;
char * nbuf;
- hash_delete (arm_reg_hsh, name, FALSE);
+ str_hash_delete (arm_reg_hsh, name);
free ((char *) reg->name);
- if (reg->neon)
- free (reg->neon);
+ free (reg->neon);
free (reg);
/* Also locate the all upper case and all lower case versions.
nbuf = strdup (name);
for (p = nbuf; *p; p++)
*p = TOUPPER (*p);
- reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
+ reg = (struct reg_entry *) str_hash_find (arm_reg_hsh, nbuf);
if (reg)
{
- hash_delete (arm_reg_hsh, nbuf, FALSE);
+ str_hash_delete (arm_reg_hsh, nbuf);
free ((char *) reg->name);
- if (reg->neon)
- free (reg->neon);
+ free (reg->neon);
free (reg);
}
for (p = nbuf; *p; p++)
*p = TOLOWER (*p);
- reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
+ reg = (struct reg_entry *) str_hash_find (arm_reg_hsh, nbuf);
if (reg)
{
- hash_delete (arm_reg_hsh, nbuf, FALSE);
+ str_hash_delete (arm_reg_hsh, nbuf);
free ((char *) reg->name);
- if (reg->neon)
- free (reg->neon);
+ free (reg->neon);
free (reg);
}
abort ();
}
- symbolP = symbol_new (symname, now_seg, value, frag);
+ symbolP = symbol_new (symname, now_seg, frag, value);
symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
switch (state)
memset (dummy_frag, 0, sizeof (fragS));
dummy_frag->fr_type = rs_fill;
dummy_frag->line = listing_tail;
- symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
+ symbolP = symbol_new (name, undefined_section, dummy_frag, 0);
dummy_frag->fr_symbol = symbolP;
}
else
#endif
- symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
+ symbolP = symbol_new (name, undefined_section, &zero_address_frag, 0);
#ifdef OBJ_COFF
/* "set" symbols are local unless otherwise specified. */
if (pool->symbol == NULL)
{
pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
- (valueT) 0, &zero_address_frag);
+ &zero_address_frag, 0);
pool->id = latest_pool_num ++;
}
return FAIL;
}
- shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
+ shift_name = (const struct asm_shift_name *) str_hash_find_n (arm_shift_hsh, *str,
p - *str);
if (shift_name == NULL)
|| strncasecmp (start, "psr", 3) == 0)
p = start + strcspn (start, "rR") + 1;
- psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
+ psr = (const struct asm_psr *) str_hash_find_n (arm_v7m_psr_hsh, start,
p - start);
if (!psr)
}
else
{
- psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
+ psr = (const struct asm_psr *) str_hash_find_n (arm_psr_hsh, start,
p - start);
if (!psr)
goto error;
n++;
}
- c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
+ c = (const struct asm_cond *) str_hash_find_n (arm_cond_hsh, cond, n);
if (!c)
{
inst.error = _("condition required");
while (ISALPHA (*q))
q++;
- o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
+ o = (const struct asm_barrier_opt *) str_hash_find_n (arm_barrier_opt_hsh, p,
q - p);
if (!o)
return FAIL;
OP_RNDMQ, /* Neon double precision (0..31) or MVE vector register. */
OP_RNDMQR, /* Neon double precision (0..31), MVE vector or ARM register.
*/
+ OP_RNSDMQR, /* Neon single or double precision, MVE vector or ARM register.
+ */
OP_RNQ, /* Neon quad precision register */
OP_RNQMQ, /* Neon quad or MVE vector register. */
OP_RVSD, /* VFP single or double precision register */
OP_oRNSDQ, /* Optional single, double or quad precision vector register */
OP_oRNSDQMQ, /* Optional single, double or quad register or MVE vector
register. */
+ OP_oRNSDMQ, /* Optional single, double register or MVE vector
+ register. */
OP_oSHll, /* LSL immediate */
OP_oSHar, /* ASR immediate */
OP_oSHllar, /* LSL or ASR immediate */
case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
case OP_oRND:
+ case OP_RNSDMQR:
+ po_reg_or_goto (REG_TYPE_VFS, try_rndmqr);
+ break;
+ try_rndmqr:
case OP_RNDMQR:
po_reg_or_goto (REG_TYPE_RN, try_rndmq);
break;
case OP_RVSD_COND:
po_reg_or_goto (REG_TYPE_VFSD, try_cond);
break;
+ case OP_oRNSDMQ:
case OP_RNSDMQ:
po_reg_or_goto (REG_TYPE_NSD, try_mq2);
break;
{
const struct asm_opcode *opcode;
- opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
+ opcode = (const struct asm_opcode *) str_hash_find (arm_ops_hsh, opname);
if (!opcode)
abort ();
enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_DDS,
NS_QQS, NS_QQQ, NS_QQR, NS_NULL);
- if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
- && inst.cond == COND_ALWAYS
+ if (inst.cond == COND_ALWAYS
&& ((unsigned)inst.instruction) == M_MNEM_vmullt)
{
+
if (rs == NS_QQQ)
{
-
- struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
- N_SUF_32 | N_F64 | N_P8
- | N_P16 | N_I_MVE | N_KEY);
- if (((et.type == NT_poly) && et.size == 8
- && ARM_CPU_IS_ANY (cpu_variant))
- || (et.type == NT_integer) || (et.type == NT_float))
+ if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
goto neon_vmul;
}
else
return;
}
+ if ((rs == NS_FD || rs == NS_QQI) && mode == neon_cvt_mode_n
+ && ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
+ {
+ /* We are dealing with vcvt with the 'ne' condition. */
+ inst.cond = 0x1;
+ inst.instruction = N_MNEM_vcvt;
+ do_neon_cvt_1 (neon_cvt_mode_z);
+ return;
+ }
+
/* VFP rather than Neon conversions. */
if (flavour >= neon_cvt_flavour_first_fp)
{
NEON_CHECK_CC | NEON_CHECK_ARCH))
return;
}
- else if (mode == neon_cvt_mode_n)
- {
- /* We are dealing with vcvt with the 'ne' condition. */
- inst.cond = 0x1;
- inst.instruction = N_MNEM_vcvt;
- do_neon_cvt_1 (neon_cvt_mode_z);
- return;
- }
/* fall through. */
case NS_DDI:
{
static void
do_neon_dyadic_long (void)
{
- enum neon_shape rs = neon_select_shape (NS_QDD, NS_QQQ, NS_QQR, NS_NULL);
+ enum neon_shape rs = neon_select_shape (NS_QDD, NS_HHH, NS_FFF, NS_DDD, NS_NULL);
if (rs == NS_QDD)
{
if (vfp_or_neon_is_neon (NEON_CHECK_ARCH | NEON_CHECK_CC) == FAIL)
static void
cxn_handle_predication (bfd_boolean is_accum)
{
- /* This function essentially checks for a suffix, not whether the instruction
- is inside an IT block or not.
- The CX* instructions should never have a conditional suffix -- this is not
- mentioned in the syntax. */
- if (conditional_insn ())
+ if (is_accum && conditional_insn ())
+ set_pred_insn_type (INSIDE_IT_INSN);
+ else if (conditional_insn ())
+ /* conditional_insn essentially checks for a suffix, not whether the
+ instruction is inside an IT block or not.
+ The non-accumulator versions should not have suffixes. */
inst.error = BAD_SYNTAX;
- /* Here we ensure that if the current element */
- else if (is_accum)
- set_pred_insn_type (NEUTRAL_IT_NO_VPT_INSN);
else
set_pred_insn_type (OUTSIDE_PRED_INSN);
}
&& mark_feature_used (&armv8m_fp))
&& !mark_feature_used (&mve_ext),
_("vcx instructions with S or D registers require either MVE"
- " or Armv8-M floating point etension."));
+ " or Armv8-M floating point extension."));
}
static void
*str = end;
/* Look for unaffixed or special-case affixed mnemonic. */
- opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
+ opcode = (const struct asm_opcode *) str_hash_find_n (arm_ops_hsh, base,
end - base);
if (opcode)
{
if (warn_on_deprecated && unified_syntax)
as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
affix = base + (opcode->tag - OT_odd_infix_0);
- cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
+ cond = (const struct asm_cond *) str_hash_find_n (arm_cond_hsh, affix, 2);
gas_assert (cond);
inst.cond = cond->value;
if (end - base < 2)
return NULL;
affix = end - 1;
- cond = (const struct asm_cond *) hash_find_n (arm_vcond_hsh, affix, 1);
- opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
+ cond = (const struct asm_cond *) str_hash_find_n (arm_vcond_hsh, affix, 1);
+ opcode = (const struct asm_opcode *) str_hash_find_n (arm_ops_hsh, base,
affix - base);
/* If this opcode can not be vector predicated then don't accept it with a
vector predication code. */
/* Look for suffixed mnemonic. */
affix = end - 2;
- cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
- opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
+ cond = (const struct asm_cond *) str_hash_find_n (arm_cond_hsh, affix, 2);
+ opcode = (const struct asm_opcode *) str_hash_find_n (arm_ops_hsh, base,
affix - base);
}
/* Look for infixed mnemonic in the usual position. */
affix = base + 3;
- cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
+ cond = (const struct asm_cond *) str_hash_find_n (arm_cond_hsh, affix, 2);
if (!cond)
return NULL;
memcpy (save, affix, 2);
memmove (affix, affix + 2, (end - affix) - 2);
- opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
+ opcode = (const struct asm_opcode *) str_hash_find_n (arm_ops_hsh, base,
(end - base) - 2);
memmove (affix + 2, affix, (end - affix) - 2);
memcpy (affix, save, 2);
gas_assert (0);
case IF_INSIDE_IT_LAST_INSN:
case NEUTRAL_IT_INSN:
- case NEUTRAL_IT_NO_VPT_INSN:
break;
case VPT_INSN:
close_automatic_it_block ();
break;
- case NEUTRAL_IT_NO_VPT_INSN:
- if (now_pred.type == VECTOR_PRED)
- {
- inst.error = BAD_NO_VPT;
- break;
- }
/* Fallthrough. */
case NEUTRAL_IT_INSN:
now_pred.block_length++;
}
break;
- case NEUTRAL_IT_NO_VPT_INSN:
- if (now_pred.type == VECTOR_PRED)
- {
- inst.error = BAD_NO_VPT;
- break;
- }
- /* Fallthrough. */
case NEUTRAL_IT_INSN:
/* The BKPT instruction is unconditional even in a IT or VPT
block. */
&& warn_on_restrict_it
&& !now_pred.warn_deprecated
&& warn_on_deprecated
- && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)
+ && (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)
+ || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8r))
&& !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m))
{
if (inst.instruction >= 0x10000)
ldrexd, t_ldrexd),
TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
strexd, t_strexd),
+#undef THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_v8r
+#undef ARM_VARIANT
+#define ARM_VARIANT & arm_ext_v8r
+
+/* ARMv8-R instructions. */
+ TUF("dfb", 57ff04c, f3bf8f4c, 0, (), noargs, noargs),
/* Defined in V8 but is in undefined encoding space for earlier
architectures. However earlier architectures are required to treat
#define ARM_VARIANT & fpu_neon_ext_v1
mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long),
- mnUF(vaddl, _vaddl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
- mnUF(vsubl, _vsubl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
+ mnUF(vaddl, _vaddl, 3, (RNSDQMQ, oRNSDMQ, RNSDMQR), neon_dyadic_long),
+ mnUF(vsubl, _vsubl, 3, (RNSDQMQ, oRNSDMQ, RNSDMQR), neon_dyadic_long),
mnUF(vand, _vand, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
mnUF(vbic, _vbic, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
for (p = nbuf; *p; p++)
*p = TOLOWER (*p);
- if (hash_find (arm_ops_hsh, nbuf) != NULL)
+ if (str_hash_find (arm_ops_hsh, nbuf) != NULL)
{
- static struct hash_control * already_warned = NULL;
+ static htab_t already_warned = NULL;
if (already_warned == NULL)
- already_warned = hash_new ();
+ already_warned = str_htab_create ();
/* Only warn about the symbol once. To keep the code
- simple we let hash_insert do the lookup for us. */
- if (hash_insert (already_warned, nbuf, NULL) == NULL)
- as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
+ simple we let str_hash_insert do the lookup for us. */
+ if (str_hash_find (already_warned, nbuf) == NULL)
+ {
+ as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
+ str_hash_insert (already_warned, nbuf, NULL);
+ }
}
else
free (nbuf);
as_bad (_("GOT already in the symbol table"));
GOT_symbol = symbol_new (name, undefined_section,
- (valueT) 0, & zero_address_frag);
+ &zero_address_frag, 0);
}
return GOT_symbol;
(((unsigned long) fixP->fx_frag->fr_address
+ (unsigned long) fixP->fx_where) & ~3)
+ (unsigned long) value);
+ else if (get_recorded_alignment (seg) < 2)
+ as_warn_where (fixP->fx_file, fixP->fx_line,
+ _("section does not have enough alignment to ensure safe PC-relative loads"));
if (value & ~0x3fc)
as_bad_where (fixP->fx_file, fixP->fx_line,
|| fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
|| fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
|| fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
+ || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH12
|| fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
|| fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
|| fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
unsigned mach;
unsigned int i;
- if ( (arm_ops_hsh = hash_new ()) == NULL
- || (arm_cond_hsh = hash_new ()) == NULL
- || (arm_vcond_hsh = hash_new ()) == NULL
- || (arm_shift_hsh = hash_new ()) == NULL
- || (arm_psr_hsh = hash_new ()) == NULL
- || (arm_v7m_psr_hsh = hash_new ()) == NULL
- || (arm_reg_hsh = hash_new ()) == NULL
- || (arm_reloc_hsh = hash_new ()) == NULL
- || (arm_barrier_opt_hsh = hash_new ()) == NULL)
+ if ( (arm_ops_hsh = str_htab_create ()) == NULL
+ || (arm_cond_hsh = str_htab_create ()) == NULL
+ || (arm_vcond_hsh = str_htab_create ()) == NULL
+ || (arm_shift_hsh = str_htab_create ()) == NULL
+ || (arm_psr_hsh = str_htab_create ()) == NULL
+ || (arm_v7m_psr_hsh = str_htab_create ()) == NULL
+ || (arm_reg_hsh = str_htab_create ()) == NULL
+ || (arm_reloc_hsh = str_htab_create ()) == NULL
+ || (arm_barrier_opt_hsh = str_htab_create ()) == NULL)
as_fatal (_("virtual memory exhausted"));
for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
- hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
+ if (str_hash_find (arm_ops_hsh, insns[i].template_name) == NULL)
+ str_hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
- hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
+ str_hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
for (i = 0; i < sizeof (vconds) / sizeof (struct asm_cond); i++)
- hash_insert (arm_vcond_hsh, vconds[i].template_name, (void *) (vconds + i));
+ str_hash_insert (arm_vcond_hsh, vconds[i].template_name, (void *) (vconds + i));
for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
- hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
+ str_hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
- hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
+ str_hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
- hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
+ str_hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
(void *) (v7m_psrs + i));
for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
- hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
+ str_hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
for (i = 0;
i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
i++)
- hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
+ str_hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
(void *) (barrier_opt_names + i));
#ifdef OBJ_ELF
for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
/* This makes encode_branch() use the EABI versions of this relocation. */
entry->reloc = BFD_RELOC_UNUSED;
- hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
+ str_hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
}
#endif
found:
/* Tag_CPU_arch_profile. */
- if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a)
- || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8)
- || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics)
- && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only)))
+ if (!ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8r)
+ && (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a)
+ || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8)
+ || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics)
+ && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only))))
*profile = 'A';
- else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r))
+ else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r)
+ || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8r))
*profile = 'R';
else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m))
*profile = 'M';
projects / deliverable / binutils-gdb.git / blobdiff