/* tc-crx.c -- Assembler code for the CRX CPU core.
- Copyright 2004, 2007 Free Software Foundation, Inc.
+ Copyright (C) 2004-2015 Free Software Foundation, Inc.
Contributed by Tomer Levi, NSC, Israel.
Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
MA 02110-1301, USA. */
#include "as.h"
+#include "bfd_stdint.h"
#include "safe-ctype.h"
#include "dwarf2dbg.h"
#include "opcode/crx.h"
OP_NOT_EVEN, /* Operand is Odd number, should be even. */
OP_ILLEGAL_DISPU4, /* Operand is not within DISPU4 range. */
OP_ILLEGAL_CST4, /* Operand is not within CST4 range. */
- OP_NOT_UPPER_64KB /* Operand is not within the upper 64KB
+ OP_NOT_UPPER_64KB /* Operand is not within the upper 64KB
(0xFFFF0000-0xFFFFFFFF). */
}
op_err;
static int get_opflags (operand_type);
static int get_number_of_operands (void);
static void parse_operand (char *, ins *);
-static int gettrap (char *);
-static void handle_LoadStor (char *);
-static int get_cinv_parameters (char *);
+static int gettrap (const char *);
+static void handle_LoadStor (const char *);
+static int get_cinv_parameters (const char *);
static long getconstant (long, int);
static op_err check_range (long *, int, unsigned int, int);
static int getreg_image (reg);
static reg
get_register (char *reg_name)
{
- const reg_entry *reg;
+ const reg_entry *rreg;
- reg = (const reg_entry *) hash_find (reg_hash, reg_name);
+ rreg = (const reg_entry *) hash_find (reg_hash, reg_name);
- if (reg != NULL)
- return reg->value.reg_val;
+ if (rreg != NULL)
+ return rreg->value.reg_val;
else
return nullregister;
}
static copreg
get_copregister (char *copreg_name)
{
- const reg_entry *copreg;
+ const reg_entry *coreg;
- copreg = (const reg_entry *) hash_find (copreg_hash, copreg_name);
+ coreg = (const reg_entry *) hash_find (copreg_hash, copreg_name);
- if (copreg != NULL)
- return copreg->value.copreg_val;
+ if (coreg != NULL)
+ return coreg->value.copreg_val;
else
return nullcopregister;
}
}
}
- assert ((int) fixP->fx_r_type > 0);
+ gas_assert ((int) fixP->fx_r_type > 0);
reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
if (reloc->howto == (reloc_howto_type *) NULL)
bfd_get_reloc_code_name (fixP->fx_r_type));
return NULL;
}
- assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
+ gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
return reloc;
}
/* Set up a hash table for the instructions. */
if ((crx_inst_hash = hash_new ()) == NULL)
as_fatal (_("Virtual memory exhausted"));
-
+
while (crx_instruction[i].mnemonic != NULL)
{
const char *mnemonic = crx_instruction[i].mnemonic;
hashret = hash_insert (crx_inst_hash, mnemonic,
- (PTR) &crx_instruction[i]);
+ (void *) &crx_instruction[i]);
if (hashret != NULL && *hashret != '\0')
as_fatal (_("Can't hash `%s': %s\n"), crx_instruction[i].mnemonic,
for (regtab = crx_regtab;
regtab < (crx_regtab + NUMREGS); regtab++)
{
- hashret = hash_insert (reg_hash, regtab->name, (PTR) regtab);
+ hashret = hash_insert (reg_hash, regtab->name, (void *) regtab);
if (hashret)
as_fatal (_("Internal Error: Can't hash %s: %s"),
regtab->name,
for (copregtab = crx_copregtab; copregtab < (crx_copregtab + NUMCOPREGS);
copregtab++)
{
- hashret = hash_insert (copreg_hash, copregtab->name, (PTR) copregtab);
+ hashret = hash_insert (copreg_hash, copregtab->name,
+ (void *) copregtab);
if (hashret)
as_fatal (_("Internal Error: Can't hash %s: %s"),
copregtab->name,
linkrelax = 1;
}
-/* Process constants (immediate/absolute)
+/* Process constants (immediate/absolute)
and labels (jump targets/Memory locations). */
static void
input_line_pointer = str;
expression (&crx_ins->exp);
-
+
switch (crx_ins->exp.X_op)
{
case O_big:
case arg_idxr:
crx_ins->rtype = BFD_RELOC_CRX_REGREL22;
break;
-
+
case arg_c:
if (IS_INSN_MNEMONIC ("bal") || IS_INSN_TYPE (DCR_BRANCH_INS))
crx_ins->rtype = BFD_RELOC_CRX_REL16;
else if (IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (COP_BRANCH_INS))
crx_ins->rtype = BFD_RELOC_CRX_REL8_CMP;
break;
-
+
case arg_ic:
if (IS_INSN_TYPE (ARITH_INS))
crx_ins->rtype = BFD_RELOC_CRX_IMM32;
case arg_c: /* Case 0x18. */
/* Set constant. */
process_label_constant (operandS, crx_ins);
-
+
if (cur_arg->type != arg_ic)
cur_arg->type = arg_c;
break;
operandE++;
*operandE = '\0';
process_label_constant (operandS, crx_ins);
- operandS = operandE;
+ operandS = operandE;
case arg_rbase: /* Case (r1). */
operandS++;
/* Set register base. */
*operandE = '\0';
process_label_constant (operandS, crx_ins);
operandS = ++operandE;
-
+
/* Set register base. */
while ((*operandE != ',') && (! ISSPACE (*operandE)))
operandE++;
default:
break;
}
-
+
if (strchr (operand, '(') != NULL)
{
if (strchr (operand, ',') != NULL
set_operand (operand, crx_ins);
}
-/* Parse the various operands. Each operand is then analyzed to fillup
+/* Parse the various operands. Each operand is then analyzed to fillup
the fields in the crx_ins data structure. */
static void
This routine is used by assembling the 'excp' instruction. */
static int
-gettrap (char *s)
+gettrap (const char *s)
{
const trap_entry *trap;
return 0;
}
-/* Post-Increment instructions, as well as Store-Immediate instructions, are a
- sub-group within load/stor instruction groups.
- Therefore, when parsing a Post-Increment/Store-Immediate insn, we have to
- advance the instruction pointer to the start of that sub-group (that is, up
+/* Post-Increment instructions, as well as Store-Immediate instructions, are a
+ sub-group within load/stor instruction groups.
+ Therefore, when parsing a Post-Increment/Store-Immediate insn, we have to
+ advance the instruction pointer to the start of that sub-group (that is, up
to the first instruction of that type).
Otherwise, the insn will be mistakenly identified as of type LD_STOR_INS. */
static void
-handle_LoadStor (char *operands)
+handle_LoadStor (const char *operands)
{
- /* Post-Increment instructions precede Store-Immediate instructions in
- CRX instruction table, hence they are handled before.
+ /* Post-Increment instructions precede Store-Immediate instructions in
+ CRX instruction table, hence they are handled before.
This synchronization should be kept. */
/* Assuming Post-Increment insn has the following format :
/* Cinv instruction requires special handling. */
static int
-get_cinv_parameters (char * operand)
+get_cinv_parameters (const char *operand)
{
- char *p = operand;
+ const char *p = operand;
int d_used = 0, i_used = 0, u_used = 0, b_used = 0;
while (*++p != ']')
static int
getreg_image (reg r)
{
- const reg_entry *reg;
+ const reg_entry *rreg;
char *reg_name;
int is_procreg = 0; /* Nonzero means argument should be processor reg. */
/* Check whether the register is in registers table. */
if (r < MAX_REG)
- reg = &crx_regtab[r];
+ rreg = &crx_regtab[r];
/* Check whether the register is in coprocessor registers table. */
- else if (r < MAX_COPREG)
- reg = &crx_copregtab[r-MAX_REG];
+ else if (r < (int) MAX_COPREG)
+ rreg = &crx_copregtab[r-MAX_REG];
/* Register not found. */
else
{
return 0;
}
- reg_name = reg->name;
+ reg_name = rreg->name;
/* Issue a error message when register is illegal. */
#define IMAGE_ERR \
reg_name, ins_parse); \
break;
- switch (reg->type)
+ switch (rreg->type)
{
case CRX_U_REGTYPE:
if (is_procreg || (instruction->flags & USER_REG))
- return reg->image;
+ return rreg->image;
else
IMAGE_ERR;
case CRX_CFG_REGTYPE:
if (is_procreg)
- return reg->image;
+ return rreg->image;
else
IMAGE_ERR;
case CRX_R_REGTYPE:
if (! is_procreg)
- return reg->image;
+ return rreg->image;
else
IMAGE_ERR;
case CRX_C_REGTYPE:
case CRX_CS_REGTYPE:
- return reg->image;
+ return rreg->image;
break;
default:
static long
getconstant (long x, int nbits)
{
- /* The following expression avoids overflow if
- 'nbits' is the number of bits in 'bfd_vma'. */
- return (x & ((((1 << (nbits - 1)) - 1) << 1) | 1));
+ return x & ((((1U << (nbits - 1)) - 1) << 1) | 1);
}
/* Print a constant value to 'output_opcode':
break;
}
- /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
- always filling the upper part of output_opcode[1]. If we mistakenly
+ /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
+ always filling the upper part of output_opcode[1]. If we mistakenly
write it to output_opcode[0], the constant prefix (that is, 'match')
will be overridden.
0 1 2 3
return i;
}
-/* Verify that the number NUM can be represented in BITS bits (that is,
- within its permitted range), based on the instruction's FLAGS.
+/* Verify that the number NUM can be represented in BITS bits (that is,
+ within its permitted range), based on the instruction's FLAGS.
If UPDATE is nonzero, update the value of NUM if necessary.
Return OP_LEGAL upon success, actual error type upon failure. */
static op_err
check_range (long *num, int bits, int unsigned flags, int update)
{
- long min, max;
+ uint32_t max;
int retval = OP_LEGAL;
int bin;
- long upper_64kb = 0xFFFF0000;
- long value = *num;
-
- /* For hosts witah longs bigger than 32-bits make sure that the top
- bits of a 32-bit negative value read in by the parser are set,
- so that the correct comparisons are made. */
- if (value & 0x80000000)
- value |= (-1L << 31);
+ uint32_t upper_64kb = 0xffff0000;
+ uint32_t value = *num;
/* Verify operand value is even. */
if (flags & OP_EVEN)
if (flags & OP_SHIFT)
{
+ /* All OP_SHIFT args are also OP_SIGNED, so we want to keep the
+ sign. However, right shift of a signed type with a negative
+ value is implementation defined. See ISO C 6.5.7. So we use
+ an unsigned type and sign extend afterwards. */
value >>= 1;
+ value = (value ^ 0x40000000) - 0x40000000;
if (update)
*num = value;
}
{
int is_dispu4 = 0;
- int mul = (instruction->flags & DISPUB4) ? 1
- : (instruction->flags & DISPUW4) ? 2
- : (instruction->flags & DISPUD4) ? 4 : 0;
-
+ uint32_t mul = (instruction->flags & DISPUB4 ? 1
+ : instruction->flags & DISPUW4 ? 2
+ : instruction->flags & DISPUD4 ? 4
+ : 0);
+
for (bin = 0; bin < cst4_maps; bin++)
{
- if (value == (mul * bin))
+ if (value == mul * bin)
{
is_dispu4 = 1;
if (update)
for (bin = 0; bin < cst4_maps; bin++)
{
- if (value == cst4_map[bin])
+ if (value == (uint32_t) cst4_map[bin])
{
is_cst4 = 1;
if (update)
}
else if (flags & OP_SIGNED)
{
- max = (1 << (bits - 1)) - 1;
- min = - (1 << (bits - 1));
- if ((value > max) || (value < min))
+ max = 1;
+ max = max << (bits - 1);
+ value += max;
+ max = ((max - 1) << 1) | 1;
+ if (value > max)
retval = OP_OUT_OF_RANGE;
}
else if (flags & OP_UNSIGNED)
{
- max = ((((1 << (bits - 1)) - 1) << 1) | 1);
- min = 0;
- if (((unsigned long) value > (unsigned long) max)
- || ((unsigned long) value < (unsigned long) min))
+ max = 1;
+ max = max << (bits - 1);
+ max = ((max - 1) << 1) | 1;
+ if (value > max)
retval = OP_OUT_OF_RANGE;
}
return retval;
/* Assemble a single instruction:
INSN is already parsed (that is, all operand values and types are set).
- For instruction to be assembled, we need to find an appropriate template in
+ For instruction to be assembled, we need to find an appropriate template in
the instruction table, meeting the following conditions:
1: Has the same number of operands.
2: Has the same operand types.
/* In some case, same mnemonic can appear with different instruction types.
For example, 'storb' is supported with 3 different types :
LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS.
- We assume that when reaching this point, the instruction type was
+ We assume that when reaching this point, the instruction type was
pre-determined. We need to make sure that the type stays the same
during a search for matching instruction. */
ins_type = CRX_INS_TYPE(instruction->flags);
{
/* Reverse the operand indices for certain opcodes:
Index 0 -->> 1
- Index 1 -->> 0
+ Index 1 -->> 0
Other index -->> stays the same. */
- int j = instruction->flags & REVERSE_MATCH ?
- i == 0 ? 1 :
- i == 1 ? 0 : i :
+ int j = instruction->flags & REVERSE_MATCH ?
+ i == 0 ? 1 :
+ i == 1 ? 0 : i :
i;
- /* Only check range - don't update the constant's value, since the
- current instruction may not be the last we try to match.
- The constant's value will be updated later, right before printing
+ /* Only check range - don't update the constant's value, since the
+ current instruction may not be the last we try to match.
+ The constant's value will be updated later, right before printing
it to the object file. */
- if ((insn->arg[j].X_op == O_constant)
- && (op_error = check_range (&insn->arg[j].constant, cur_size[j],
+ if ((insn->arg[j].X_op == O_constant)
+ && (op_error = check_range (&insn->arg[j].constant, cur_size[j],
cur_flags[j], 0)))
{
if (invalid_const == -1)
}
goto next_insn;
}
- /* For symbols, we make sure the relocation size (which was already
+ /* For symbols, we make sure the relocation size (which was already
determined) is sufficient. */
else if ((insn->arg[j].X_op == O_symbol)
- && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize
+ && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize
> cur_size[j]))
goto next_insn;
}
as_bad (_("Invalid CST4 operand value (arg %d)"), invalid_const);
break;
case OP_NOT_UPPER_64KB:
- as_bad (_("Operand value is not within upper 64 KB (arg %d)"),
+ as_bad (_("Operand value is not within upper 64 KB (arg %d)"),
invalid_const);
break;
default:
break;
}
}
-
+
return 0;
}
else
/* Make further checkings (such that couldn't be made earlier).
Warn the user if necessary. */
warn_if_needed (insn);
-
+
/* Check whether we need to adjust the instruction pointer. */
if (adjust_if_needed (insn))
- /* If instruction pointer was adjusted, we need to update
+ /* If instruction pointer was adjusted, we need to update
the size of the current template operands. */
GET_CURRENT_SIZE;
for (i = 0; i < insn->nargs; i++)
{
- int j = instruction->flags & REVERSE_MATCH ?
- i == 0 ? 1 :
- i == 1 ? 0 : i :
+ int j = instruction->flags & REVERSE_MATCH ?
+ i == 0 ? 1 :
+ i == 1 ? 0 : i :
i;
/* This time, update constant value before printing it. */
- if ((insn->arg[j].X_op == O_constant)
- && (check_range (&insn->arg[j].constant, cur_size[j],
+ if ((insn->arg[j].X_op == O_constant)
+ && (check_range (&insn->arg[j].constant, cur_size[j],
cur_flags[j], 1) != OP_LEGAL))
as_fatal (_("Illegal operand (arg %d)"), j+1);
}
for (i = 0; i < insn->nargs; i++)
{
cur_arg_num = i;
- print_operand (cur_size[i], instruction->operands[i].shift,
+ print_operand (cur_size[i], instruction->operands[i].shift,
&insn->arg[i]);
}
}
void
warn_if_needed (ins *insn)
{
- /* If the post-increment address mode is used and the load/store
- source register is the same as rbase, the result of the
+ /* If the post-increment address mode is used and the load/store
+ source register is the same as rbase, the result of the
instruction is undefined. */
if (IS_INSN_TYPE (LD_STOR_INS_INC))
{
/* Enough to verify that one of the arguments is a simple reg. */
if ((insn->arg[0].type == arg_r) || (insn->arg[1].type == arg_r))
if (insn->arg[0].r == insn->arg[1].r)
- as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
+ as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
insn->arg[0].r);
}
as_bad (_("`%s' has undefined result"), ins_parse);
}
- /* If the rptr register is specified as one of the registers to be loaded,
+ /* If the rptr register is specified as one of the registers to be loaded,
the final contents of rptr are undefined. Thus, we issue an error. */
if (instruction->flags & NO_RPTR)
{
if ((1 << getreg_image (insn->arg[0].r)) & insn->arg[1].constant)
- as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
+ as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
getreg_image (insn->arg[0].r));
}
}
-/* In some cases, we need to adjust the instruction pointer although a
+/* In some cases, we need to adjust the instruction pointer although a
match was already found. Here, we gather all these cases.
Returns 1 if instruction pointer was adjusted, otherwise 0. */
}
}
- /* Optimization: Omit a zero displacement in bit operations,
+ /* Optimization: Omit a zero displacement in bit operations,
saving 2-byte encoding space (e.g., 'cbitw $8, 0(r1)'). */
if (IS_INSN_TYPE (CSTBIT_INS))
{
{
if (((cr = get_copregister (reg_name)) == nullcopregister)
|| (crx_copregtab[cr-MAX_REG].type != CRX_CS_REGTYPE))
- as_fatal (_("Illegal register `%s' in cop-special-register list"),
+ as_fatal (_("Illegal register `%s' in cop-special-register list"),
reg_name);
mask_reg (getreg_image (cr - cs0), &mask);
}
else if (((r = get_register (reg_name)) == nullregister)
|| (crx_regtab[r].type != CRX_U_REGTYPE))
as_fatal (_("Illegal register `%s' in user register list"), reg_name);
-
- mask_reg (getreg_image (r - u0), &mask);
+
+ mask_reg (getreg_image (r - u0), &mask);
}
/* General purpose register r<N>. */
else
if (instruction == NULL)
{
as_bad (_("Unknown opcode: `%s'"), op);
+ param[-1] = c;
return;
}
/* Assemble the instruction - return upon failure. */
if (assemble_insn (op, &crx_ins) == 0)
- return;
+ {
+ param[-1] = c;
+ return;
+ }
/* Print the instruction. */
+ param[-1] = c;
print_insn (&crx_ins);
}
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