x86: drop VexImmExt

[deliverable/binutils-gdb.git] / gas / config / tc-i386.c

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 028e0626cb825508e3cdc4276511fa672efa8b3f..2ddbe195a9ea2688126acda6ea89077ccecf995f 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -432,7 +432,6 @@ const char extra_symbol_chars[] = "*%-([{}"
         && !defined (TE_GNU)                           \
         && !defined (TE_LINUX)                         \
         && !defined (TE_NACL)                          \
-        && !defined (TE_NETWARE)                       \
         && !defined (TE_FreeBSD)                       \
         && !defined (TE_DragonFly)                     \
         && !defined (TE_NetBSD)))
@@ -1028,6 +1027,8 @@ static const arch_entry cpu_arch[] =
     CPU_PCONFIG_FLAGS, 0 },
   { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
     CPU_WAITPKG_FLAGS, 0 },
+  { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
+    CPU_CLDEMOTE_FLAGS, 0 },
 };
 
 static const noarch_entry cpu_noarch[] =
@@ -6566,22 +6567,13 @@ build_modrm_byte (void)
   unsigned int source, dest;
   int vex_3_sources;
 
-  /* The first operand of instructions with VEX prefix and 3 sources
-     must be VEX_Imm4.  */
   vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
   if (vex_3_sources)
     {
       unsigned int nds, reg_slot;
       expressionS *exp;
 
-      if (i.tm.opcode_modifier.veximmext
-          && i.tm.opcode_modifier.immext)
-        {
-          dest = i.operands - 2;
-          gas_assert (dest == 3);
-        }
-      else
-        dest = i.operands - 1;
+      dest = i.operands - 1;
       nds = dest - 1;
 
       /* There are 2 kinds of instructions:
@@ -6590,16 +6582,12 @@ build_modrm_byte (void)
          VexW0 or VexW1.  The destination must be either XMM, YMM or
         ZMM register.
          2. 4 operands: 4 register operands or 3 register operands
-         plus 1 memory operand, VexXDS, and VexImmExt  */
+        plus 1 memory operand, with VexXDS.  */
       gas_assert ((i.reg_operands == 4
                    || (i.reg_operands == 3 && i.mem_operands == 1))
                   && i.tm.opcode_modifier.vexvvvv == VEXXDS
-                  && (i.tm.opcode_modifier.veximmext
-                      || (i.imm_operands == 1
-                          && i.types[0].bitfield.vec_imm4
-                          && (i.tm.opcode_modifier.vexw == VEXW0
-                              || i.tm.opcode_modifier.vexw == VEXW1)
-                          && i.tm.operand_types[dest].bitfield.regsimd)));
+                 && i.tm.opcode_modifier.vexw
+                 && i.tm.operand_types[dest].bitfield.regsimd);
 
       if (i.imm_operands == 0)
         {
@@ -6622,15 +6610,6 @@ build_modrm_byte (void)
               reg_slot = 0;
             }
 
-          /* FMA swaps REG and NDS.  */
-          if (i.tm.cpu_flags.bitfield.cpufma)
-            {
-              unsigned int tmp;
-              tmp = reg_slot;
-              reg_slot = nds;
-              nds = tmp;
-            }
-
           gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
           exp->X_op = O_constant;
           exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
@@ -6640,6 +6619,8 @@ build_modrm_byte (void)
         {
           unsigned int imm_slot;
 
+         gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
+
           if (i.tm.opcode_modifier.vexw == VEXW0)
             {
               /* If VexW0 is set, the third operand is the source and