static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
-static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
enum operand_type
{
return 0;
}
- /* Only check VEX_Imm4, which must be the first operand. */
- if (t->operand_types[0].bitfield.vec_imm4)
+ /* Check the special Imm4 cases; must be the first operand. */
+ if (t->cpu_flags.bitfield.cpuxop && t->operands == 5)
{
if (i.op[0].imms->X_op != O_constant
|| !fits_in_imm4 (i.op[0].imms->X_add_number))
return 1;
}
- /* Turn off Imm8 so that update_imm won't complain. */
- i.types[0] = vec_imm4;
+ /* Turn off Imm<N> so that update_imm won't complain. */
+ operand_type_set (&i.types[0], 0);
}
return 0;
/* There are 2 kinds of instructions:
1. 5 operands: 4 register operands or 3 register operands
- plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
+ plus 1 memory operand plus one Imm4 operand, VexXDS, and
VexW0 or VexW1. The destination must be either XMM, YMM or
ZMM register.
2. 4 operands: 4 register operands or 3 register operands
}
else
{
- unsigned int imm_slot;
+ gas_assert (i.imm_operands == 1);
+ gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number));
+ gas_assert (!i.tm.opcode_modifier.immext);
- gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
-
- if (i.tm.opcode_modifier.immext)
- {
- /* When ImmExt is set, the immediate byte is the last
- operand. */
- imm_slot = i.operands - 1;
- source--;
- reg_slot--;
- }
- else
- {
- imm_slot = 0;
-
- /* Turn on Imm8 so that output_imm will generate it. */
- i.types[imm_slot].bitfield.imm8 = 1;
- }
+ /* Turn on Imm8 again so that output_imm will generate it. */
+ i.types[0].bitfield.imm8 = 1;
gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
- i.op[imm_slot].imms->X_add_number
+ i.op[0].imms->X_add_number
|= register_number (i.op[reg_slot].regs) << 4;
gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
}