gas/

[deliverable/binutils-gdb.git] / gas / config / tc-i386.c

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index fc1eeaf2a29a3a290e0afb4f6f138de519ea2d3f..5ac7e0c88dc1ee3c2b3e3ebdbe972b653360ccdd 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1,6 +1,6 @@
 /* i386.c -- Assemble code for the Intel 80386
    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2001, 2002
+   2000, 2001, 2002, 2003
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -30,6 +30,7 @@
 #include "safe-ctype.h"
 #include "subsegs.h"
 #include "dwarf2dbg.h"
+#include "dw2gencfi.h"
 #include "opcode/i386.h"
 
 #ifndef REGISTER_WARNINGS
@@ -207,7 +208,7 @@ const char comment_chars[] = "#/";
    #NO_APP at the beginning of its output.
    Also note that comments started like this one will always work if
    '/' isn't otherwise defined.  */
-const char line_comment_chars[] = "";
+const char line_comment_chars[] = "#";
 
 #else
 /* Putting '/' here makes it impossible to use the divide operator.
@@ -215,7 +216,7 @@ const char line_comment_chars[] = "";
 const char comment_chars[] = "#";
 #define PREFIX_SEPARATOR '/'
 
-const char line_comment_chars[] = "/";
+const char line_comment_chars[] = "/#";
 #endif
 
 const char line_separator_chars[] = ";";
@@ -302,6 +303,9 @@ static int allow_naked_reg = 0;
    frame as in 32 bit mode.  */
 static char stackop_size = '\0';
 
+/* Non-zero to optimize code alignment.  */
+int optimize_align_code = 1;
+
 /* Non-zero to quieten some warnings.  */
 static int quiet_warnings = 0;
 
@@ -318,6 +322,12 @@ static unsigned int no_cond_jump_promotion = 0;
 /* Pre-defined "_GLOBAL_OFFSET_TABLE_".  */
 symbolS *GOT_symbol;
 
+/* The dwarf2 return column, adjusted for 32 or 64 bit.  */
+unsigned int x86_dwarf2_return_column;
+
+/* The dwarf2 data alignment, adjusted for 32 or 64 bit.  */
+int x86_cie_data_alignment;
+
 /* Interface to relax_segment.
    There are 3 major relax states for 386 jump insns because the
    different types of jumps add different sizes to frags when we're
@@ -986,6 +996,17 @@ md_begin ()
       record_alignment (bss_section, 2);
     }
 #endif
+
+  if (flag_code == CODE_64BIT)
+    {
+      x86_dwarf2_return_column = 16;
+      x86_cie_data_alignment = -8;
+    }
+  else
+    {
+      x86_dwarf2_return_column = 8;
+      x86_cie_data_alignment = -4;
+    }
 }
 
 void
@@ -1392,6 +1413,21 @@ md_assemble (line)
 
   if (i.tm.opcode_modifier & ImmExt)
     {
+      if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
+       {
+          /* These Intel Precott New Instructions have the fixed
+            operands with an opcode suffix which is coded in the same
+            place as an 8-bit immediate field would be. Here we check
+            those operands and remove them afterwards.  */
+         unsigned int x;
+
+         for (x = 0; x < i.operands; x++) 
+           if (i.op[x].regs->reg_num != x)
+             as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
+                       i.op[x].regs->reg_name, x + 1, i.tm.name);
+         i.operands = 0;
+       }
+
       /* These AMD 3DNow! and Intel Katmai New Instructions have an
         opcode suffix which is coded in the same place as an 8-bit
         immediate field would be.  Here we fake an 8-bit immediate
@@ -4647,7 +4683,7 @@ md_apply_fix3 (fixP, valP, seg)
          if ((sym_seg == seg
               || (symbol_section_p (fixP->fx_addsy)
                   && sym_seg != absolute_section))
-             && !S_FORCE_RELOC (fixP->fx_addsy))
+             && !generic_force_reloc (fixP))
            {
              /* Yes, we add the values in twice.  This is because
                 bfd_install_relocation subtracts them out again.  I think
@@ -4871,9 +4907,9 @@ parse_register (reg_string, end_op)
 }
 \f
 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
-const char *md_shortopts = "kVQ:sq";
+const char *md_shortopts = "kVQ:sqn";
 #else
-const char *md_shortopts = "q";
+const char *md_shortopts = "qn";
 #endif
 
 struct option md_longopts[] = {
@@ -4894,6 +4930,10 @@ md_parse_option (c, arg)
 {
   switch (c)
     {
+    case 'n':
+      optimize_align_code = 0;
+      break;
+
     case 'q':
       quiet_warnings = 1;
       break;
@@ -4955,10 +4995,12 @@ md_show_usage (stream)
   -Q                      ignored\n\
   -V                      print assembler version number\n\
   -k                      ignored\n\
+  -n                      Do not optimize code alignment\n\
   -q                      quieten some warnings\n\
   -s                      ignored\n"));
 #else
   fprintf (stream, _("\
+  -n                      Do not optimize code alignment\n\
   -q                      quieten some warnings\n"));
 #endif
 }
@@ -5146,17 +5188,6 @@ i386_validate_fix (fixp)
     }
 }
 
-bfd_boolean
-i386_force_relocation (fixp)
-     fixS *fixp;
-{
-  if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
-      || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
-    return 1;
-
-  return S_FORCE_RELOC (fixp->fx_addsy);
-}
-
 arelent *
 tc_gen_reloc (section, fixp)
      asection *section ATTRIBUTE_UNUSED;
@@ -6310,3 +6341,55 @@ intel_putback_token ()
   prev_token.reg = NULL;
   prev_token.str = NULL;
 }
+
+int
+tc_x86_regname_to_dw2regnum (const char *regname)
+{
+  unsigned int regnum;
+  unsigned int regnames_count;
+  char *regnames_32[] =
+    {
+      "eax", "ecx", "edx", "ebx",
+      "esp", "ebp", "esi", "edi",
+      "eip"
+    };
+  char *regnames_64[] =
+    {
+      "rax", "rbx", "rcx", "rdx",
+      "rdi", "rsi", "rbp", "rsp",
+      "r8", "r9", "r10", "r11",
+      "r12", "r13", "r14", "r15",
+      "rip"
+    };
+  char **regnames;
+
+  if (flag_code == CODE_64BIT)
+    {
+      regnames = regnames_64;
+      regnames_count = sizeof (regnames_64);
+    }
+  else
+    {
+      regnames = regnames_32;
+      regnames_count = sizeof (regnames_32);
+    }
+
+  for (regnum = 0; regnum < regnames_count; regnum++)
+    if (strcmp (regname, regnames[regnum]) == 0)
+      return regnum;
+
+  return -1;
+}
+
+void
+tc_x86_frame_initial_instructions (void)
+{
+  static unsigned int sp_regno;
+
+  if (!sp_regno)
+    sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
+                                           ? "rsp" : "esp");
+
+  cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
+  cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
+}