if (i.tm.opcode_modifier & ImmExt)
{
+ expressionS *exp;
+
+ if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
+ {
+ /* These Intel Precott New Instructions have the fixed
+ operands with an opcode suffix which is coded in the same
+ place as an 8-bit immediate field would be. Here we check
+ those operands and remove them afterwards. */
+ unsigned int x;
+
+ for (x = 0; x < i.operands; x++)
+ if (i.op[x].regs->reg_num != x)
+ as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
+ i.op[x].regs->reg_name, x + 1, i.tm.name);
+ i.operands = 0;
+ }
+
/* These AMD 3DNow! and Intel Katmai New Instructions have an
opcode suffix which is coded in the same place as an 8-bit
immediate field would be. Here we fake an 8-bit immediate
operand from the opcode suffix stored in tm.extension_opcode. */
- expressionS *exp;
-
assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
exp = &im_expressions[i.imm_operands++];
/* Add the displacement expression. */
if (*s != '\0')
- ret = i386_displacement (s, s + strlen (s))
- && i386_index_check (s);
+ ret = i386_displacement (s, s + strlen (s));
+ if (ret)
+ ret = i386_index_check (operand_string);
}
}
if (flag_code == CODE_64BIT)
{
regnames = regnames_64;
- regnames_count = sizeof (regnames_64);
+ regnames_count = ARRAY_SIZE (regnames_64);
}
else
{
regnames = regnames_32;
- regnames_count = sizeof (regnames_32);
+ regnames_count = ARRAY_SIZE (regnames_32);
}
for (regnum = 0; regnum < regnames_count; regnum++)