#include "elf/x86-64.h"
#include "opcodes/i386-init.h"
-#ifdef TE_LINUX
-/* Default to compress debug sections for Linux. */
-enum compressed_debug_section_type flag_compress_debug
- = COMPRESS_DEBUG_ZLIB;
-#endif
-
#ifndef REGISTER_WARNINGS
#define REGISTER_WARNINGS 1
#endif
static int use_big_obj = 0;
#endif
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+/* 1 if generating code for a shared library. */
+static int shared = 0;
+#endif
+
/* 1 for intel syntax,
0 if att syntax. */
static int intel_syntax = 0;
CPU_L1OM_FLAGS, 0, 0 },
{ STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
CPU_K1OM_FLAGS, 0, 0 },
+ { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
+ CPU_IAMCU_FLAGS, 0, 0 },
{ STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
CPU_K6_FLAGS, 0, 0 },
{ STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
{ STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
CPU_BDVER4_FLAGS, 0, 0 },
{ STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
- CPU_ZNVER1_FLAGS, 0, 0 },
+ CPU_ZNVER1_FLAGS, 0, 0 },
{ STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
CPU_BTVER1_FLAGS, 0, 0 },
{ STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
CPU_AVX512VBMI_FLAGS, 0, 0 },
{ STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
CPU_CLZERO_FLAGS, 0, 0 },
+ { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
+ CPU_MWAITX_FLAGS, 0, 0 },
};
#ifdef I386COFF
case PROCESSOR_I486:
case PROCESSOR_PENTIUM:
case PROCESSOR_PENTIUMPRO:
+ case PROCESSOR_IAMCU:
case PROCESSOR_GENERIC32:
patt = f32_patt;
break;
case PROCESSOR_I386:
case PROCESSOR_I486:
case PROCESSOR_PENTIUM:
+ case PROCESSOR_IAMCU:
case PROCESSOR_K6:
case PROCESSOR_ATHLON:
case PROCESSOR_K8:
return x;
}
+static int
+valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
+{
+ if (cpu_arch_isa == PROCESSOR_IAMCU)
+ {
+ static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
+ i386_cpu_flags compat_flags;
+ compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
+ return cpu_flags_all_zero (&compat_flags);
+ }
+ else
+ return 1;
+}
+
#define CPU_FLAGS_ARCH_MATCH 0x1
#define CPU_FLAGS_64BIT_MATCH 0x2
#define CPU_FLAGS_AES_MATCH 0x4
{
return (match_reg_size (t, j)
&& !((i.types[j].bitfield.unspecified
+ && !i.broadcast
&& !t->operand_types[j].bitfield.unspecified)
|| (i.types[j].bitfield.fword
&& !t->operand_types[j].bitfield.fword)
SKIP_WHITESPACE ();
if (!is_end_of_line[(unsigned char) *input_line_pointer])
{
- char *string = input_line_pointer;
- int e = get_symbol_end ();
+ char *string;
+ int e = get_symbol_name (&string);
if (strcmp (string, "prefix") == 0)
ask_naked_reg = 1;
ask_naked_reg = -1;
else
as_bad (_("bad argument to syntax directive."));
- *input_line_pointer = e;
+ (void) restore_line_pointer (e);
}
demand_empty_rest_of_line ();
if (!is_end_of_line[(unsigned char) *input_line_pointer])
{
- char *string = input_line_pointer;
- int e = get_symbol_end ();
+ char *string;
+ int e = get_symbol_name (&string);
if (strcmp (string, "none") == 0)
*kind = check_none;
*kind = check_error;
else
as_bad (_("bad argument to %s_check directive."), str);
- *input_line_pointer = e;
+ (void) restore_line_pointer (e);
}
else
as_bad (_("missing argument for %s_check directive"), str);
arch = default_arch;
}
+ /* If we are targeting Intel MCU, we must enable it. */
+ if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
+ || new_flag.bitfield.cpuiamcu)
+ return;
+
/* If we are targeting Intel L1OM, we must enable it. */
if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
|| new_flag.bitfield.cpul1om)
if (!is_end_of_line[(unsigned char) *input_line_pointer])
{
- char *string = input_line_pointer;
- int e = get_symbol_end ();
+ char *string;
+ int e = get_symbol_name (&string);
unsigned int j;
i386_cpu_flags flags;
else
flags = cpu_flags_and_not (cpu_arch_flags,
cpu_arch[j].flags);
- if (!cpu_flags_equal (&flags, &cpu_arch_flags))
+
+ if (!valid_iamcu_cpu_flags (&flags))
+ as_fatal (_("`%s' isn't valid for Intel MCU"),
+ cpu_arch[j].name);
+ else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
{
if (cpu_sub_arch_name)
{
cpu_arch_flags = flags;
cpu_arch_isa_flags = flags;
}
- *input_line_pointer = e;
+ (void) restore_line_pointer (e);
demand_empty_rest_of_line ();
return;
}
if (*input_line_pointer == ','
&& !is_end_of_line[(unsigned char) input_line_pointer[1]])
{
- char *string = ++input_line_pointer;
- int e = get_symbol_end ();
+ char *string;
+ char e;
+
+ ++input_line_pointer;
+ e = get_symbol_name (&string);
if (strcmp (string, "nojumps") == 0)
no_cond_jump_promotion = 1;
else
as_bad (_("no such architecture modifier: `%s'"), string);
- *input_line_pointer = e;
+ (void) restore_line_pointer (e);
}
demand_empty_rest_of_line ();
as_fatal (_("Intel K1OM is 64bit ELF only"));
return bfd_arch_k1om;
}
+ else if (cpu_arch_isa == PROCESSOR_IAMCU)
+ {
+ if (OUTPUT_FLAVOR != bfd_target_elf_flavour
+ || flag_code == CODE_64BIT)
+ as_fatal (_("Intel MCU is 32bit ELF only"));
+ return bfd_arch_iamcu;
+ }
else
return bfd_arch_i386;
}
else
return bfd_mach_x64_32;
}
- else if (!strcmp (default_arch, "i386"))
- return bfd_mach_i386_i386;
+ else if (!strcmp (default_arch, "i386")
+ || !strcmp (default_arch, "iamcu"))
+ {
+ if (cpu_arch_isa == PROCESSOR_IAMCU)
+ {
+ if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+ as_fatal (_("Intel MCU is 32bit ELF only"));
+ return bfd_mach_i386_iamcu;
+ }
+ else
+ return bfd_mach_i386_i386;
+ }
else
as_fatal (_("unknown architecture"));
}
i.operands = 0;
}
+ if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
+ {
+ /* MONITORX/MWAITX instructions have fixed operands with an opcode
+ suffix which is coded in the same place as an 8-bit immediate
+ field would be.
+ Here we check those operands and remove them afterwards. */
+ unsigned int x;
+
+ if (i.operands != 3)
+ abort();
+
+ for (x = 0; x < 2; x++)
+ if (register_number (i.op[x].regs) != x)
+ goto bad_register_operand;
+
+ /* Check for third operand for mwaitx/monitorx insn. */
+ if (register_number (i.op[x].regs)
+ != (x + (i.tm.extension_opcode == 0xfb)))
+ {
+bad_register_operand:
+ as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
+ register_prefix, i.op[x].regs->reg_name, x+1,
+ i.tm.name);
+ }
+
+ i.operands = 0;
+ }
+
/* These AMD 3DNow! and SSE2 instructions have an opcode suffix
which is coded in the same place as an 8-bit immediate field
would be. Here we fake an 8-bit immediate operand from the
/* Skip optional white space before operand. */
if (is_space_char (*l))
++l;
- if (!is_operand_char (*l) && *l != END_OF_INSN)
+ if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
{
as_bad (_("invalid character %s before operand %d"),
output_invalid (*l),
i.operands + 1);
return NULL;
}
- token_start = l; /* after white space */
+ token_start = l; /* After white space. */
paren_not_balanced = 0;
while (paren_not_balanced || *l != ',')
{
else
break; /* we are done */
}
- else if (!is_operand_char (*l) && !is_space_char (*l))
+ else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
{
as_bad (_("invalid character %s in operand %d"),
output_invalid (*l),
}
else if (is_digit_char (*op_string)
|| is_identifier_char (*op_string)
+ || *op_string == '"'
|| *op_string == '(')
{
/* This is a memory reference of some sort. */
return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
}
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+static int
+elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
+{
+ /* STT_GNU_IFUNC symbol must go through PLT. */
+ if ((symbol_get_bfdsym (fr_symbol)->flags
+ & BSF_GNU_INDIRECT_FUNCTION) != 0)
+ return 0;
+
+ if (!S_IS_EXTERNAL (fr_symbol))
+ /* Symbol may be weak or local. */
+ return !S_IS_WEAK (fr_symbol);
+
+ /* Global symbols with non-default visibility can't be preempted. */
+ if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
+ return 1;
+
+ if (fr_var != NO_RELOC)
+ switch ((enum bfd_reloc_code_real) fr_var)
+ {
+ case BFD_RELOC_386_PLT32:
+ case BFD_RELOC_X86_64_PLT32:
+ /* Symbol with PLT relocatin may be preempted. */
+ return 0;
+ default:
+ abort ();
+ }
+
+ /* Global symbols with default visibility in a shared library may be
+ preempted by another definition. */
+ return !shared;
+}
+#endif
+
/* md_estimate_size_before_relax()
Called just before relax() for rs_machine_dependent frags. The x86
if (S_GET_SEGMENT (fragP->fr_symbol) != segment
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
|| (IS_ELF
- && (S_IS_EXTERNAL (fragP->fr_symbol)
- || S_IS_WEAK (fragP->fr_symbol)
- || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
- & BSF_GNU_INDIRECT_FUNCTION))))
+ && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
+ fragP->fr_var))
#endif
#if defined (OBJ_COFF) && defined (TE_PE)
|| (OUTPUT_FLAVOR == bfd_target_coff_flavour
symbolS *symbolP;
input_line_pointer = reg_string;
- c = get_symbol_end ();
+ c = get_symbol_name (®_string);
symbolP = symbol_find (reg_string);
if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
{
#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
+#define OPTION_MSHARED (OPTION_MD_BASE + 21)
+#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
+#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
struct option md_longopts[] =
{
#endif
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
{"x32", no_argument, NULL, OPTION_X32},
+ {"mshared", no_argument, NULL, OPTION_MSHARED},
#endif
{"divide", no_argument, NULL, OPTION_DIVIDE},
{"march", required_argument, NULL, OPTION_MARCH},
#endif
{"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
{"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
+ {"mamd64", no_argument, NULL, OPTION_MAMD64},
+ {"mintel64", no_argument, NULL, OPTION_MINTEL64},
{NULL, no_argument, NULL, 0}
};
size_t md_longopts_size = sizeof (md_longopts);
/* -s: On i386 Solaris, this tells the native assembler to use
.stab instead of .stab.excl. We always use .stab anyhow. */
break;
+
+ case OPTION_MSHARED:
+ shared = 1;
+ break;
#endif
#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
|| defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
else
flags = cpu_flags_and_not (cpu_arch_flags,
cpu_arch[j].flags);
- if (!cpu_flags_equal (&flags, &cpu_arch_flags))
+
+ if (!valid_iamcu_cpu_flags (&flags))
+ as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
+ else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
{
if (cpu_sub_arch_name)
{
as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
break;
+ case OPTION_MAMD64:
+ cpu_arch_flags.bitfield.cpuamd64 = 1;
+ cpu_arch_flags.bitfield.cpuintel64 = 0;
+ cpu_arch_isa_flags.bitfield.cpuamd64 = 1;
+ cpu_arch_isa_flags.bitfield.cpuintel64 = 0;
+ break;
+
+ case OPTION_MINTEL64:
+ cpu_arch_flags.bitfield.cpuamd64 = 0;
+ cpu_arch_flags.bitfield.cpuintel64 = 1;
+ cpu_arch_isa_flags.bitfield.cpuamd64 = 0;
+ cpu_arch_isa_flags.bitfield.cpuintel64 = 1;
+ break;
+
default:
return 0;
}
-mold-gcc support old (<= 2.8.1) versions of gcc\n"));
fprintf (stream, _("\
-madd-bnd-prefix add BND prefix for all valid branches\n"));
+ fprintf (stream, _("\
+ -mshared disable branch optimization for shared code\n"));
# if defined (TE_PE) || defined (TE_PEP)
fprintf (stream, _("\
-mbig-obj generate big object files\n"));
fprintf (stream, _("\
-momit-lock-prefix=[no|yes]\n\
strip all lock prefixes\n"));
+ fprintf (stream, _("\
+ -mamd64 accept only AMD64 ISA\n"));
+ fprintf (stream, _("\
+ -mintel64 accept only Intel64 ISA\n"));
}
#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
}
else if (!strcmp (default_arch, "i386"))
update_code_flag (CODE_32BIT, 1);
+ else if (!strcmp (default_arch, "iamcu"))
+ {
+ update_code_flag (CODE_32BIT, 1);
+ if (cpu_arch_isa == PROCESSOR_UNKNOWN)
+ {
+ static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
+ cpu_arch_name = "iamcu";
+ cpu_sub_arch_name = NULL;
+ cpu_arch_flags = iamcu_flags;
+ cpu_arch_isa = PROCESSOR_IAMCU;
+ cpu_arch_isa_flags = iamcu_flags;
+ if (!cpu_arch_tune_set)
+ {
+ cpu_arch_tune = cpu_arch_isa;
+ cpu_arch_tune_flags = cpu_arch_isa_flags;
+ }
+ }
+ else
+ as_fatal (_("Intel MCU doesn't support `%s' architecture"),
+ cpu_arch_name);
+ }
else
as_fatal (_("unknown architecture"));
as_fatal (_("Intel L1OM is 64bit only"));
return ELF_TARGET_L1OM_FORMAT;
}
- if (cpu_arch_isa == PROCESSOR_K1OM)
+ else if (cpu_arch_isa == PROCESSOR_K1OM)
{
if (x86_elf_abi != X86_64_ABI)
as_fatal (_("Intel K1OM is 64bit only"));
return ELF_TARGET_K1OM_FORMAT;
}
+ else if (cpu_arch_isa == PROCESSOR_IAMCU)
+ {
+ if (x86_elf_abi != I386_ABI)
+ as_fatal (_("Intel MCU is 32bit only"));
+ return ELF_TARGET_IAMCU_FORMAT;
+ }
else
return format;
}
}
#endif /* OBJ_MAYBE_ more than one */
-
-#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
-void
-i386_elf_emit_arch_note (void)
-{
- if (IS_ELF && cpu_arch_name != NULL)
- {
- char *p;
- asection *seg = now_seg;
- subsegT subseg = now_subseg;
- Elf_Internal_Note i_note;
- Elf_External_Note e_note;
- asection *note_secp;
- int len;
-
- /* Create the .note section. */
- note_secp = subseg_new (".note", 0);
- bfd_set_section_flags (stdoutput,
- note_secp,
- SEC_HAS_CONTENTS | SEC_READONLY);
-
- /* Process the arch string. */
- len = strlen (cpu_arch_name);
-
- i_note.namesz = len + 1;
- i_note.descsz = 0;
- i_note.type = NT_ARCH;
- p = frag_more (sizeof (e_note.namesz));
- md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
- p = frag_more (sizeof (e_note.descsz));
- md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
- p = frag_more (sizeof (e_note.type));
- md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
- p = frag_more (len + 1);
- strcpy (p, cpu_arch_name);
-
- frag_align (2, 0, 0);
-
- subseg_set (seg, subseg);
- }
-}
-#endif
\f
symbolS *
md_undefined_symbol (char *name)
projects / deliverable / binutils-gdb.git / blobdiff