/* tc-i386.c -- Assemble code for the Intel 80386
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
#endif
static void signed_cons (int);
static char *output_invalid (int c);
+static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
+ const char *);
+static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
+ const char *);
static int i386_att_operand (char *);
static int i386_intel_operand (char *, int);
+static int i386_intel_simplify (expressionS *);
+static int i386_intel_parse_name (const char *, expressionS *);
static const reg_entry *parse_register (char *, char **);
static char *parse_insn (char *, char *);
static char *parse_operands (char *, const char *);
static void swap_2_operands (int, int);
static void optimize_imm (void);
static void optimize_disp (void);
-static int match_template (void);
+static const template *match_template (void);
static int check_string (void);
static int process_suffix (void);
static int check_byte_reg (void);
sib_byte sib;
drex_byte drex;
vex_prefix vex;
+
+ /* Swap operand in encoding. */
+ unsigned int swap_operand : 1;
};
typedef struct _i386_insn i386_insn;
static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
/* Current operand we are working on. */
-static int this_operand;
+static int this_operand = -1;
/* We support four different modes. FLAG_CODE variable is used to distinguish
these. */
CPU_CORE2_FLAGS },
{ "core2", PROCESSOR_CORE2,
CPU_CORE2_FLAGS },
+ { "corei7", PROCESSOR_COREI7,
+ CPU_COREI7_FLAGS },
{ "k6", PROCESSOR_K6,
CPU_K6_FLAGS },
{ "k6_2", PROCESSOR_K6,
CPU_MOVBE_FLAGS },
{ ".ept", PROCESSOR_UNKNOWN,
CPU_EPT_FLAGS },
+ { ".clflush", PROCESSOR_UNKNOWN,
+ CPU_CLFLUSH_FLAGS },
+ { ".syscall", PROCESSOR_UNKNOWN,
+ CPU_SYSCALL_FLAGS },
+ { ".rdtscp", PROCESSOR_UNKNOWN,
+ CPU_RDTSCP_FLAGS },
{ ".3dnow", PROCESSOR_UNKNOWN,
CPU_3DNOW_FLAGS },
{ ".3dnowa", PROCESSOR_UNKNOWN,
1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
PROCESSOR_GENERIC32, f32_patt will be used.
2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
- PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
- alt_long_patt will be used.
+ PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
+ PROCESSOR_GENERIC64, alt_long_patt will be used.
3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
PROCESSOR_AMDFAM10, alt_short_patt will be used.
case PROCESSOR_NOCONA:
case PROCESSOR_CORE:
case PROCESSOR_CORE2:
+ case PROCESSOR_COREI7:
case PROCESSOR_GENERIC64:
patt = alt_long_patt;
break;
case PROCESSOR_NOCONA:
case PROCESSOR_CORE:
case PROCESSOR_CORE2:
+ case PROCESSOR_COREI7:
if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
patt = alt_long_patt;
else
#define CPU_FLAGS_ARCH_MATCH 0x1
#define CPU_FLAGS_64BIT_MATCH 0x2
#define CPU_FLAGS_AES_MATCH 0x4
-#define CPU_FLAGS_AVX_MATCH 0x8
+#define CPU_FLAGS_PCLMUL_MATCH 0x8
+#define CPU_FLAGS_AVX_MATCH 0x10
#define CPU_FLAGS_32BIT_MATCH \
- (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH | CPU_FLAGS_AVX_MATCH)
+ (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
+ | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
#define CPU_FLAGS_PERFECT_MATCH \
(CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
{
if (x.bitfield.cpuavx)
{
- /* We only need to check AES/SSE2AVX with AVX. */
+ /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
if (cpu.bitfield.cpuavx)
{
/* Check SSE2AVX. */
/* Check AES. */
if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
match |= CPU_FLAGS_AES_MATCH;
+ /* Check PCLMUL. */
+ if (!x.bitfield.cpupclmul
+ || cpu.bitfield.cpupclmul)
+ match |= CPU_FLAGS_PCLMUL_MATCH;
}
}
else
static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
-static const i386_operand_type vex_imm4 = OPERAND_TYPE_VEX_IMM4;
enum operand_type
{
#endif
} /* fits_in_unsigned_long() */
-static INLINE int
-fits_in_imm4 (offsetT num)
-{
- return (num & 0xf) == num;
-}
-
static i386_operand_type
smallest_imm_type (offsetT num)
{
else
allow_naked_reg = (ask_naked_reg < 0);
+ expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
+
identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
identifier_chars['$'] = intel_syntax ? '$' : 0;
register_prefix = allow_naked_reg ? "" : "%";
{ OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
{ OPERAND_TYPE_REGMMX, "rMMX" },
{ OPERAND_TYPE_REGXMM, "rXMM" },
+ { OPERAND_TYPE_REGYMM, "rYMM" },
{ OPERAND_TYPE_ESSEG, "es" },
- { OPERAND_TYPE_VEX_IMM4, "VEX i4" },
};
static void
for (j = 0; j < ARRAY_SIZE (type_names); j++)
{
a = operand_type_and (t, type_names[j].mask);
- if (!UINTS_ALL_ZERO (a))
+ if (!operand_type_all_zero (&a))
fprintf (stdout, "%s, ", type_names[j].name);
}
fflush (stdout);
sign > 0 ? "signed" : "unsigned", size);
}
- abort ();
- return BFD_RELOC_NONE;
+ return NO_RELOC;
}
/* Here we decide which fixups can be adjusted to make them relative to
|| fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
return 0;
+
+ if (fixP->fx_addsy != NULL
+ && symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_GNU_INDIRECT_FUNCTION)
+ return 0;
#endif
return 1;
}
/* Build the VEX prefix. */
static void
-build_vex_prefix (void)
+build_vex_prefix (const template *t)
{
unsigned int register_specifier;
unsigned int implied_prefix;
else
register_specifier = 0xf;
+ /* Use 2-byte VEX prefix by swappping destination and source
+ operand. */
+ if (!i.swap_operand
+ && i.operands == i.reg_operands
+ && i.tm.opcode_modifier.vex0f
+ && i.tm.opcode_modifier.s
+ && i.rex == REX_B)
+ {
+ unsigned int xchg = i.operands - 1;
+ union i386_op temp_op;
+ i386_operand_type temp_type;
+
+ temp_type = i.types[xchg];
+ i.types[xchg] = i.types[0];
+ i.types[0] = temp_type;
+ temp_op = i.op[xchg];
+ i.op[xchg] = i.op[0];
+ i.op[0] = temp_op;
+
+ assert (i.rm.mode == 3);
+
+ i.rex = REX_R;
+ xchg = i.rm.regmem;
+ i.rm.regmem = i.rm.reg;
+ i.rm.reg = xchg;
+
+ /* Use the next insn. */
+ i.tm = t[1];
+ }
+
vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
switch ((i.tm.base_opcode >> 8) & 0xff)
{
unsigned int j;
char mnemonic[MAX_MNEM_SIZE];
+ const template *t;
/* Initialize globals. */
memset (&i, '\0', sizeof (i));
return;
line = parse_operands (line, mnemonic);
+ this_operand = -1;
if (line == NULL)
return;
making sure the overlap of the given operands types is consistent
with the template operand types. */
- if (!match_template ())
+ if (!(t = match_template ()))
return;
if (sse_check != sse_check_none
}
if (i.tm.opcode_modifier.vex)
- build_vex_prefix ();
+ build_vex_prefix (t);
/* Handle conversion of 'int $3' --> special int3 insn. */
if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
char *mnem_p;
int supported;
const template *t;
+ char *dot_p = NULL;
/* Non-zero if we found a prefix only acceptable with string insns. */
const char *expecting_string_instruction = NULL;
mnem_p = mnemonic;
while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
{
+ if (*mnem_p == '.')
+ dot_p = mnem_p;
mnem_p++;
if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
{
if (!current_templates)
{
+ /* Check if we should swap operand in encoding. */
+ if (mnem_p - 2 == dot_p && dot_p[1] == 's')
+ i.swap_operand = 1;
+ else
+ goto check_suffix;
+ mnem_p = dot_p;
+ *dot_p = '\0';
+ current_templates = hash_find (op_hash, mnemonic);
+ }
+
+ if (!current_templates)
+ {
+check_suffix:
/* See if we can get a match by trimming off a suffix. */
switch (mnem_p[-1])
{
if (supported != CPU_FLAGS_PERFECT_MATCH)
{
as_bad (_("`%s' is not supported on `%s%s'"),
- current_templates->start->name, cpu_arch_name,
+ current_templates->start->name,
+ cpu_arch_name ? cpu_arch_name : default_arch,
cpu_sub_arch_name ? cpu_sub_arch_name : "");
return NULL;
}
}
}
-/* Check if operands are valid for the instrucrtion. Update VEX
- operand types. */
-
-static int
-VEX_check_operands (const template *t)
-{
- if (!t->opcode_modifier.vex)
- return 0;
-
- /* Only check VEX_Imm4, which must be the first operand. */
- if (t->operand_types[0].bitfield.vex_imm4)
- {
- if (i.op[0].imms->X_op != O_constant
- || !fits_in_imm4 (i.op[0].imms->X_add_number))
- return 1;
-
- /* Turn off Imm8 so that update_imm won't complain. */
- i.types[0] = vex_imm4;
- }
-
- return 0;
-}
-
-static int
+static const template *
match_template (void)
{
/* Points to template once we've found it. */
&& operand_type_equal (&i.types [0], &acc32)
&& operand_type_equal (&i.types [1], &acc32))
continue;
+ if (i.swap_operand)
+ {
+ /* If we swap operand in encoding, we either match
+ the next one or reverse direction of operands. */
+ if (t->opcode_modifier.s)
+ continue;
+ else if (t->opcode_modifier.d)
+ goto check_reverse;
+ }
+
case 3:
+ /* If we swap operand in encoding, we match the next one. */
+ if (i.swap_operand && t->opcode_modifier.s)
+ continue;
case 4:
case 5:
overlap1 = operand_type_and (i.types[1], operand_types[1]);
if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
continue;
+check_reverse:
/* Try reversing direction of operands. */
overlap0 = operand_type_and (i.types[0], operand_types[1]);
overlap1 = operand_type_and (i.types[1], operand_types[0]);
continue;
}
- /* Check if VEX operands are valid. */
- if (VEX_check_operands (t))
- continue;
-
/* We've found a match; break out of loop. */
break;
}
else
as_bad (_("suffix or operands invalid for `%s'"),
current_templates->start->name);
- return 0;
+ return NULL;
}
if (!quiet_warnings)
i.tm.operand_types[1] = operand_types[0];
}
- return 1;
+ return t;
}
static int
{
/* Reversed arguments on faddp, fsubp, etc. */
as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
- register_prefix, i.op[1].regs->reg_name,
- register_prefix, i.op[0].regs->reg_name);
+ register_prefix, i.op[!intel_syntax].regs->reg_name,
+ register_prefix, i.op[intel_syntax].regs->reg_name);
}
else
{
{
unsigned int nds, reg;
- if (i.tm.opcode_modifier.veximmext
- && i.tm.opcode_modifier.immext)
- {
- dest = i.operands - 2;
- assert (dest == 3);
- }
- else
- dest = i.operands - 1;
+ dest = i.operands - 1;
nds = dest - 1;
-
- /* There are 2 kinds of instructions:
- 1. 5 operands: one immediate operand and 4 register
- operands or 3 register operands plus 1 memory operand.
- It must have VexNDS and VexW0 or VexW1. The destination
- must be either XMM or YMM register.
- 2. 4 operands: 4 register operands or 3 register operands
- plus 1 memory operand. It must have VexNDS and VexImmExt. */
- if (!((i.reg_operands == 4
- || (i.reg_operands == 3 && i.mem_operands == 1))
- && i.tm.opcode_modifier.vexnds
- && (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
- || operand_type_equal (&i.tm.operand_types[dest], ®ymm))
- && ((dest == 4
- && i.imm_operands == 1
- && i.types[0].bitfield.vex_imm4
- && (i.tm.opcode_modifier.vexw0
- || i.tm.opcode_modifier.vexw1))
- || (dest == 3
- && (i.imm_operands == 0
- || (i.imm_operands == 1
- && i.tm.opcode_modifier.immext))
- && i.tm.opcode_modifier.veximmext))))
- abort ();
-
- if (i.imm_operands == 0)
- {
- /* When there is no immediate operand, generate an 8bit
- immediate operand to encode the first operand. */
- expressionS *exp = &im_expressions[i.imm_operands++];
- i.op[i.operands].imms = exp;
- i.types[i.operands] = imm8;
- i.operands++;
- /* If VexW1 is set, the first operand is the source and
- the second operand is encoded in the immediate operand. */
- if (i.tm.opcode_modifier.vexw1)
- {
- source = 0;
- reg = 1;
- }
- else
- {
- source = 1;
- reg = 0;
- }
-
- /* FMA swaps REG and NDS. */
- if (i.tm.cpu_flags.bitfield.cpufma)
- {
- unsigned int tmp;
- tmp = reg;
- reg = nds;
- nds = tmp;
- }
-
- assert (operand_type_equal (&i.tm.operand_types[reg], ®xmm)
+ source = 1;
+ reg = 0;
+
+ /* This instruction must have 4 operands: 4 register operands
+ or 3 register operands plus 1 memory operand. It must have
+ VexNDS and VexImmExt. */
+ assert (i.operands == 4
+ && (i.reg_operands == 4
+ || (i.reg_operands == 3 && i.mem_operands == 1))
+ && i.tm.opcode_modifier.vexnds
+ && i.tm.opcode_modifier.veximmext
+ && (operand_type_equal (&i.tm.operand_types[dest],
+ ®xmm)
+ || operand_type_equal (&i.tm.operand_types[dest],
+ ®ymm))
+ && (operand_type_equal (&i.tm.operand_types[nds],
+ ®xmm)
+ || operand_type_equal (&i.tm.operand_types[nds],
+ ®ymm))
+ && (operand_type_equal (&i.tm.operand_types[reg],
+ ®xmm)
|| operand_type_equal (&i.tm.operand_types[reg],
- ®ymm));
- exp->X_op = O_constant;
- exp->X_add_number
- = ((i.op[reg].regs->reg_num
- + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
- }
- else
- {
- unsigned int imm;
-
- if (i.tm.opcode_modifier.vexw0)
- {
- /* If VexW0 is set, the third operand is the source and
- the second operand is encoded in the immediate
- operand. */
- source = 2;
- reg = 1;
- }
- else
- {
- /* VexW1 is set, the second operand is the source and
- the third operand is encoded in the immediate
- operand. */
- source = 1;
- reg = 2;
- }
-
- if (i.tm.opcode_modifier.immext)
- {
- /* When ImmExt is set, the immdiate byte is the last
- operand. */
- imm = i.operands - 1;
- source--;
- reg--;
- }
- else
- {
- imm = 0;
+ ®ymm)));
- /* Turn on Imm8 so that output_imm will generate it. */
- i.types[imm].bitfield.imm8 = 1;
- }
-
- assert (operand_type_equal (&i.tm.operand_types[reg], ®xmm)
- || operand_type_equal (&i.tm.operand_types[reg],
- ®ymm));
- i.op[imm].imms->X_add_number
- |= ((i.op[reg].regs->reg_num
- + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
- }
+ /* Generate an 8bit immediate operand to encode the register
+ operand. */
+ expressionS *exp = &im_expressions[i.imm_operands++];
+ i.op[i.operands].imms = exp;
+ i.types[i.operands] = imm8;
+ i.operands++;
+ exp->X_op = O_constant;
+ exp->X_add_number
+ = ((i.op[0].regs->reg_num
+ + ((i.op[0].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
- assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
- || operand_type_equal (&i.tm.operand_types[nds], ®ymm));
i.vex.register_specifier = i.op[nds].regs;
}
else
{
/* For instructions with VexNDS, the register-only
source operand must be XMM or YMM register. It is
- encoded in VEX prefix. */
+ encoded in VEX prefix. We need to clear RegMem bit
+ before calling operand_type_equal. */
+ i386_operand_type op = i.tm.operand_types[dest];
+ op.bitfield.regmem = 0;
if ((dest + 1) >= i.operands
- || (!operand_type_equal (&i.tm.operand_types[dest],
- ®xmm)
- && !operand_type_equal (&i.tm.operand_types[dest],
- ®ymm)))
+ || (!operand_type_equal (&op, ®xmm)
+ && !operand_type_equal (&op, ®ymm)))
abort ();
i.vex.register_specifier = i.op[dest].regs;
dest++;
void
x86_cons (expressionS *exp, int size)
{
+ intel_syntax = -intel_syntax;
+
if (size == 4 || (object_64bit && size == 8))
{
/* Handle @GOTOFF and the like in an expression. */
}
else
expression (exp);
+
+ intel_syntax = -intel_syntax;
+
+ if (intel_syntax)
+ i386_intel_simplify (exp);
}
#endif
input_line_pointer = save_input_line_pointer;
if (gotfree_input_line)
- free (gotfree_input_line);
+ {
+ free (gotfree_input_line);
+
+ if (exp->X_op == O_constant || exp->X_op == O_register)
+ exp->X_op = O_illegal;
+ }
+
+ return i386_finalize_immediate (exp_seg, exp, types, imm_start);
+}
- if (exp->X_op == O_absent
- || exp->X_op == O_illegal
- || exp->X_op == O_big
- || (gotfree_input_line
- && (exp->X_op == O_constant
- || exp->X_op == O_register)))
+static int
+i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
+ i386_operand_type types, const char *imm_start)
+{
+ if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
{
as_bad (_("missing or invalid immediate expression `%s'"),
imm_start);
#endif
input_line_pointer = save_input_line_pointer;
if (gotfree_input_line)
- free (gotfree_input_line);
- ret = 1;
+ {
+ free (gotfree_input_line);
+
+ if (exp->X_op == O_constant || exp->X_op == O_register)
+ exp->X_op = O_illegal;
+ }
+
+ ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
+
+ RESTORE_END_STRING (disp_end);
+
+ return ret;
+}
+
+static int
+i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
+ i386_operand_type types, const char *disp_start)
+{
+ i386_operand_type bigdisp;
+ int ret = 1;
/* We do this to make sure that the section symbol is in
the symbol table. We will ultimately change the relocation
else if (exp->X_op == O_absent
|| exp->X_op == O_illegal
- || exp->X_op == O_big
- || (gotfree_input_line
- && (exp->X_op == O_constant
- || exp->X_op == O_register)))
+ || exp->X_op == O_big)
{
inv_disp:
as_bad (_("missing or invalid displacement expression `%s'"),
}
#endif
- RESTORE_END_STRING (disp_end);
-
/* Check if this is a displacement only operand. */
bigdisp = i.types[this_operand];
bigdisp.bitfield.disp8 = 0;
}
input_line_pointer = end;
*end = 0;
- return 0;
+ return intel_syntax ? i386_intel_parse_name (name, e) : 0;
}
void
md_operand (expressionS *e)
{
- if (*input_line_pointer == REGISTER_PREFIX)
- {
- char *end;
- const reg_entry *r = parse_real_register (input_line_pointer, &end);
+ char *end;
+ const reg_entry *r;
+ switch (*input_line_pointer)
+ {
+ case REGISTER_PREFIX:
+ r = parse_real_register (input_line_pointer, &end);
if (r)
{
e->X_op = O_register;
e->X_add_number = r - i386_regtab;
input_line_pointer = end;
}
+ break;
+
+ case '[':
+ assert (intel_syntax);
+ end = input_line_pointer++;
+ expression (e);
+ if (*input_line_pointer == ']')
+ {
+ ++input_line_pointer;
+ e->X_op_symbol = make_expr_symbol (e);
+ e->X_add_symbol = NULL;
+ e->X_add_number = 0;
+ e->X_op = O_index;
+ }
+ else
+ {
+ e->X_op = O_absent;
+ input_line_pointer = end;
+ }
+ break;
}
}
generate code for CPU and EXTENSION, CPU is one of:\n\
i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
- core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
+ core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
generic32, generic64\n\
EXTENSION is combination of:\n\
mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
- 3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
+ clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
+ sse5, svme, abm, padlock\n"));
fprintf (stream, _("\
-mtune=CPU optimize for CPU, CPU is one of:\n\
i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
- core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
+ core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
generic32, generic64\n"));
fprintf (stream, _("\
-msse2avx encode SSE instructions with VEX prefix\n"));
cpu_arch_isa_flags.bitfield.cpui486 = 1;
cpu_arch_isa_flags.bitfield.cpui586 = 1;
cpu_arch_isa_flags.bitfield.cpui686 = 1;
- cpu_arch_isa_flags.bitfield.cpup4 = 1;
+ cpu_arch_isa_flags.bitfield.cpuclflush = 1;
cpu_arch_isa_flags.bitfield.cpummx= 1;
cpu_arch_isa_flags.bitfield.cpusse = 1;
cpu_arch_isa_flags.bitfield.cpusse2 = 1;
cpu_arch_tune_flags.bitfield.cpui486 = 1;
cpu_arch_tune_flags.bitfield.cpui586 = 1;
cpu_arch_tune_flags.bitfield.cpui686 = 1;
- cpu_arch_tune_flags.bitfield.cpup4 = 1;
+ cpu_arch_tune_flags.bitfield.cpuclflush = 1;
cpu_arch_tune_flags.bitfield.cpummx= 1;
cpu_arch_tune_flags.bitfield.cpusse = 1;
cpu_arch_tune_flags.bitfield.cpusse2 = 1;
return rel;
}
-\f
-/* Parse operands using Intel syntax. This implements a recursive descent
- parser based on the BNF grammar published in Appendix B of the MASM 6.1
- Programmer's Guide.
-
- FIXME: We do not recognize the full operand grammar defined in the MASM
- documentation. In particular, all the structure/union and
- high-level macro operands are missing.
-
- Uppercase words are terminals, lower case words are non-terminals.
- Objects surrounded by double brackets '[[' ']]' are optional. Vertical
- bars '|' denote choices. Most grammar productions are implemented in
- functions called 'intel_<production>'.
-
- Initial production is 'expr'.
-
- addOp + | -
-
- alpha [a-zA-Z]
-
- binOp & | AND | \| | OR | ^ | XOR
-
- byteRegister AL | AH | BL | BH | CL | CH | DL | DH
-
- constant digits [[ radixOverride ]]
-
- dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
-
- digits decdigit
- | digits decdigit
- | digits hexdigit
-
- decdigit [0-9]
-
- e04 e04 addOp e05
- | e05
-
- e05 e05 binOp e06
- | e06
-
- e06 e06 mulOp e09
- | e09
-
- e09 OFFSET e10
- | SHORT e10
- | + e10
- | - e10
- | ~ e10
- | NOT e10
- | e09 PTR e10
- | e09 : e10
- | e10
-
- e10 e10 [ expr ]
- | e11
+#include "tc-i386-intel.c"
- e11 ( expr )
- | [ expr ]
- | constant
- | dataType
- | id
- | $
- | register
-
- => expr expr cmpOp e04
- | e04
-
- gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
- | BP | EBP | SP | ESP | DI | EDI | SI | ESI
-
- hexdigit a | b | c | d | e | f
- | A | B | C | D | E | F
-
- id alpha
- | id alpha
- | id decdigit
-
- mulOp * | / | % | MOD | << | SHL | >> | SHR
-
- quote " | '
-
- register specialRegister
- | gpRegister
- | byteRegister
-
- segmentRegister CS | DS | ES | FS | GS | SS
-
- specialRegister CR0 | CR2 | CR3 | CR4
- | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
- | TR3 | TR4 | TR5 | TR6 | TR7
-
- We simplify the grammar in obvious places (e.g., register parsing is
- done by calling parse_register) and eliminate immediate left recursion
- to implement a recursive-descent parser.
-
- expr e04 expr'
-
- expr' cmpOp e04 expr'
- | Empty
-
- e04 e05 e04'
-
- e04' addOp e05 e04'
- | Empty
-
- e05 e06 e05'
+void
+tc_x86_parse_to_dw2regnum (expressionS *exp)
+{
+ int saved_naked_reg;
+ char saved_register_dot;
- e05' binOp e06 e05'
- | Empty
+ saved_naked_reg = allow_naked_reg;
+ allow_naked_reg = 1;
+ saved_register_dot = register_chars['.'];
+ register_chars['.'] = '.';
+ allow_pseudo_reg = 1;
+ expression_and_evaluate (exp);
+ allow_pseudo_reg = 0;
+ register_chars['.'] = saved_register_dot;
+ allow_naked_reg = saved_naked_reg;
- e06 e09 e06'
+ if (exp->X_op == O_register && exp->X_add_number >= 0)
+ {
+ if ((addressT) exp->X_add_number < i386_regtab_size)
+ {
+ exp->X_op = O_constant;
+ exp->X_add_number = i386_regtab[exp->X_add_number]
+ .dw2_regnum[flag_code >> 1];
+ }
+ else
+ exp->X_op = O_illegal;
+ }
+}
- e06' mulOp e09 e06'
- | Empty
+void
+tc_x86_frame_initial_instructions (void)
+{
+ static unsigned int sp_regno[2];
- e09 OFFSET e10 e09'
- | SHORT e10'
- | + e10'
- | - e10'
- | ~ e10'
- | NOT e10'
- | e10 e09'
+ if (!sp_regno[flag_code >> 1])
+ {
+ char *saved_input = input_line_pointer;
+ char sp[][4] = {"esp", "rsp"};
+ expressionS exp;
- e09' PTR e10 e09'
- | : e10 e09'
- | Empty
+ input_line_pointer = sp[flag_code >> 1];
+ tc_x86_parse_to_dw2regnum (&exp);
+ assert (exp.X_op == O_constant);
+ sp_regno[flag_code >> 1] = exp.X_add_number;
+ input_line_pointer = saved_input;
+ }
- e10 e11 e10'
+ cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
+ cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
+}
- e10' [ expr ] e10'
- | Empty
+int
+i386_elf_section_type (const char *str, size_t len)
+{
+ if (flag_code == CODE_64BIT
+ && len == sizeof ("unwind") - 1
+ && strncmp (str, "unwind", 6) == 0)
+ return SHT_X86_64_UNWIND;
- e11 ( expr )
- | [ expr ]
- | BYTE
- | WORD
- | DWORD
- | FWORD
- | QWORD
- | TBYTE
- | OWORD
- | XMMWORD
- | YMMWORD
- | .
- | $
- | register
- | id
- | constant */
+ return -1;
+}
-/* Parsing structure for the intel syntax parser. Used to implement the
- semantic actions for the operand grammar. */
-struct intel_parser_s
- {
- char *op_string; /* The string being parsed. */
- int got_a_float; /* Whether the operand is a float. */
- int op_modifier; /* Operand modifier. */
- int is_mem; /* 1 if operand is memory reference. */
- int in_offset; /* >=1 if parsing operand of offset. */
- int in_bracket; /* >=1 if parsing operand in brackets. */
- const reg_entry *reg; /* Last register reference found. */
- char *disp; /* Displacement string being built. */
- char *next_operand; /* Resume point when splitting operands. */
- };
+#ifdef TE_SOLARIS
+void
+i386_solaris_fix_up_eh_frame (segT sec)
+{
+ if (flag_code == CODE_64BIT)
+ elf_section_type (sec) = SHT_X86_64_UNWIND;
+}
+#endif
-static struct intel_parser_s intel_parser;
+#ifdef TE_PE
+void
+tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
+{
+ expressionS expr;
-/* Token structure for parsing intel syntax. */
-struct intel_token
- {
- int code; /* Token code. */
- const reg_entry *reg; /* Register entry for register tokens. */
- char *str; /* String representation. */
- };
+ expr.X_op = O_secrel;
+ expr.X_add_symbol = symbol;
+ expr.X_add_number = 0;
+ emit_expr (&expr, size);
+}
+#endif
-static struct intel_token cur_token, prev_token;
-
-/* Token codes for the intel parser. Since T_SHORT is already used
- by COFF, undefine it first to prevent a warning. */
-#define T_NIL -1
-#define T_CONST 1
-#define T_REG 2
-#define T_BYTE 3
-#define T_WORD 4
-#define T_DWORD 5
-#define T_FWORD 6
-#define T_QWORD 7
-#define T_TBYTE 8
-#define T_XMMWORD 9
-#undef T_SHORT
-#define T_SHORT 10
-#define T_OFFSET 11
-#define T_PTR 12
-#define T_ID 13
-#define T_SHL 14
-#define T_SHR 15
-#define T_YMMWORD 16
-
-/* Prototypes for intel parser functions. */
-static int intel_match_token (int);
-static void intel_putback_token (void);
-static void intel_get_token (void);
-static int intel_expr (void);
-static int intel_e04 (void);
-static int intel_e05 (void);
-static int intel_e06 (void);
-static int intel_e09 (void);
-static int intel_e10 (void);
-static int intel_e11 (void);
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
-static int
-i386_intel_operand (char *operand_string, int got_a_float)
+bfd_vma
+x86_64_section_letter (int letter, char **ptr_msg)
{
- int ret;
- char *p;
- const reg_entry *final_base = i.base_reg;
- const reg_entry *final_index = i.index_reg;
-
- p = intel_parser.op_string = xstrdup (operand_string);
- intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
-
- for (;;)
+ if (flag_code == CODE_64BIT)
{
- /* Initialize token holders. */
- cur_token.code = prev_token.code = T_NIL;
- cur_token.reg = prev_token.reg = NULL;
- cur_token.str = prev_token.str = NULL;
-
- /* Initialize parser structure. */
- intel_parser.got_a_float = got_a_float;
- intel_parser.op_modifier = 0;
- intel_parser.is_mem = 0;
- intel_parser.in_offset = 0;
- intel_parser.in_bracket = 0;
- intel_parser.reg = NULL;
- intel_parser.disp[0] = '\0';
- intel_parser.next_operand = NULL;
-
- i.base_reg = NULL;
- i.index_reg = NULL;
-
- /* Read the first token and start the parser. */
- intel_get_token ();
- ret = intel_expr ();
+ if (letter == 'l')
+ return SHF_X86_64_LARGE;
- if (!ret)
- break;
+ *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
+ }
+ else
+ *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
+ return -1;
+}
- if (cur_token.code != T_NIL)
- {
- as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
- current_templates->start->name, cur_token.str);
- ret = 0;
- }
- /* If we found a memory reference, hand it over to i386_displacement
- to fill in the rest of the operand fields. */
- else if (intel_parser.is_mem)
- {
- if ((i.mem_operands == 1
- && !current_templates->start->opcode_modifier.isstring)
- || i.mem_operands == 2)
- {
- as_bad (_("too many memory references for '%s'"),
- current_templates->start->name);
- ret = 0;
- }
- else
- {
- char *s = intel_parser.disp;
-
- if (!quiet_warnings && intel_parser.is_mem < 0)
- /* See the comments in intel_bracket_expr. */
- as_warn (_("Treating `%s' as memory reference"), operand_string);
-
- /* Add the displacement expression. */
- if (*s != '\0')
- ret = i386_displacement (s, s + strlen (s));
- if (ret)
- {
- /* Swap base and index in 16-bit memory operands like
- [si+bx]. Since i386_index_check is also used in AT&T
- mode we have to do that here. */
- if (i.base_reg
- && i.index_reg
- && i.base_reg->reg_type.bitfield.reg16
- && i.index_reg->reg_type.bitfield.reg16
- && i.base_reg->reg_num >= 6
- && i.index_reg->reg_num < 6)
- {
- const reg_entry *base = i.index_reg;
-
- i.index_reg = i.base_reg;
- i.base_reg = base;
- }
- ret = i386_index_check (operand_string);
- }
- if (ret)
- {
- i.types[this_operand].bitfield.mem = 1;
- i.mem_operands++;
- }
- }
- }
-
- /* Constant and OFFSET expressions are handled by i386_immediate. */
- else if ((intel_parser.op_modifier & (1 << T_OFFSET))
- || intel_parser.reg == NULL)
- {
- if (i.mem_operands < 2 && i.seg[i.mem_operands])
- {
- if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
- as_warn (_("Segment override ignored"));
- i.seg[i.mem_operands] = NULL;
- }
- ret = i386_immediate (intel_parser.disp);
- }
-
- if (!final_base && !final_index)
- {
- final_base = i.base_reg;
- final_index = i.index_reg;
- }
-
- if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
- ret = 0;
- if (!ret || !intel_parser.next_operand)
- break;
- intel_parser.op_string = intel_parser.next_operand;
- this_operand = i.operands++;
- i.types[this_operand].bitfield.unspecified = 1;
- }
-
- free (p);
- free (intel_parser.disp);
-
- if (final_base || final_index)
- {
- i.base_reg = final_base;
- i.index_reg = final_index;
- }
-
- return ret;
-}
-
-#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
-
-/* expr e04 expr'
-
- expr' cmpOp e04 expr'
- | Empty */
-static int
-intel_expr (void)
-{
- /* XXX Implement the comparison operators. */
- return intel_e04 ();
-}
-
-/* e04 e05 e04'
-
- e04' addOp e05 e04'
- | Empty */
-static int
-intel_e04 (void)
-{
- int nregs = -1;
-
- for (;;)
- {
- if (!intel_e05())
- return 0;
-
- if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
- i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
-
- if (cur_token.code == '+')
- nregs = -1;
- else if (cur_token.code == '-')
- nregs = NUM_ADDRESS_REGS;
- else
- return 1;
-
- strcat (intel_parser.disp, cur_token.str);
- intel_match_token (cur_token.code);
- }
-}
-
-/* e05 e06 e05'
-
- e05' binOp e06 e05'
- | Empty */
-static int
-intel_e05 (void)
-{
- int nregs = ~NUM_ADDRESS_REGS;
-
- for (;;)
- {
- if (!intel_e06())
- return 0;
-
- if (cur_token.code == '&'
- || cur_token.code == '|'
- || cur_token.code == '^')
- {
- char str[2];
-
- str[0] = cur_token.code;
- str[1] = 0;
- strcat (intel_parser.disp, str);
- }
- else
- break;
-
- intel_match_token (cur_token.code);
-
- if (nregs < 0)
- nregs = ~nregs;
- }
- if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
- i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
- return 1;
-}
-
-/* e06 e09 e06'
-
- e06' mulOp e09 e06'
- | Empty */
-static int
-intel_e06 (void)
-{
- int nregs = ~NUM_ADDRESS_REGS;
-
- for (;;)
- {
- if (!intel_e09())
- return 0;
-
- if (cur_token.code == '*'
- || cur_token.code == '/'
- || cur_token.code == '%')
- {
- char str[2];
-
- str[0] = cur_token.code;
- str[1] = 0;
- strcat (intel_parser.disp, str);
- }
- else if (cur_token.code == T_SHL)
- strcat (intel_parser.disp, "<<");
- else if (cur_token.code == T_SHR)
- strcat (intel_parser.disp, ">>");
- else
- break;
-
- intel_match_token (cur_token.code);
-
- if (nregs < 0)
- nregs = ~nregs;
- }
- if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
- i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
- return 1;
-}
-
-/* e09 OFFSET e09
- | SHORT e09
- | + e09
- | - e09
- | ~ e09
- | NOT e09
- | e10 e09'
-
- e09' PTR e10 e09'
- | : e10 e09'
- | Empty */
-static int
-intel_e09 (void)
-{
- int nregs = ~NUM_ADDRESS_REGS;
- int in_offset = 0;
-
- for (;;)
- {
- /* Don't consume constants here. */
- if (cur_token.code == '+' || cur_token.code == '-')
- {
- /* Need to look one token ahead - if the next token
- is a constant, the current token is its sign. */
- int next_code;
-
- intel_match_token (cur_token.code);
- next_code = cur_token.code;
- intel_putback_token ();
- if (next_code == T_CONST)
- break;
- }
-
- /* e09 OFFSET e09 */
- if (cur_token.code == T_OFFSET)
- {
- if (!in_offset++)
- ++intel_parser.in_offset;
- }
-
- /* e09 SHORT e09 */
- else if (cur_token.code == T_SHORT)
- intel_parser.op_modifier |= 1 << T_SHORT;
-
- /* e09 + e09 */
- else if (cur_token.code == '+')
- strcat (intel_parser.disp, "+");
-
- /* e09 - e09
- | ~ e09
- | NOT e09 */
- else if (cur_token.code == '-' || cur_token.code == '~')
- {
- char str[2];
-
- if (nregs < 0)
- nregs = ~nregs;
- str[0] = cur_token.code;
- str[1] = 0;
- strcat (intel_parser.disp, str);
- }
-
- /* e09 e10 e09' */
- else
- break;
-
- intel_match_token (cur_token.code);
- }
-
- for (;;)
- {
- if (!intel_e10 ())
- return 0;
-
- /* e09' PTR e10 e09' */
- if (cur_token.code == T_PTR)
- {
- char suffix;
-
- if (prev_token.code == T_BYTE)
- {
- suffix = BYTE_MNEM_SUFFIX;
- i.types[this_operand].bitfield.byte = 1;
- }
-
- else if (prev_token.code == T_WORD)
- {
- if ((current_templates->start->name[0] == 'l'
- && current_templates->start->name[2] == 's'
- && current_templates->start->name[3] == 0)
- || current_templates->start->base_opcode == 0x62 /* bound */)
- suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
- else if (intel_parser.got_a_float == 2) /* "fi..." */
- suffix = SHORT_MNEM_SUFFIX;
- else
- suffix = WORD_MNEM_SUFFIX;
- i.types[this_operand].bitfield.word = 1;
- }
-
- else if (prev_token.code == T_DWORD)
- {
- if ((current_templates->start->name[0] == 'l'
- && current_templates->start->name[2] == 's'
- && current_templates->start->name[3] == 0)
- || current_templates->start->base_opcode == 0x62 /* bound */)
- suffix = WORD_MNEM_SUFFIX;
- else if (flag_code == CODE_16BIT
- && (current_templates->start->opcode_modifier.jump
- || current_templates->start->opcode_modifier.jumpdword))
- suffix = LONG_DOUBLE_MNEM_SUFFIX;
- else if (intel_parser.got_a_float == 1) /* "f..." */
- suffix = SHORT_MNEM_SUFFIX;
- else
- suffix = LONG_MNEM_SUFFIX;
- i.types[this_operand].bitfield.dword = 1;
- }
-
- else if (prev_token.code == T_FWORD)
- {
- if (current_templates->start->name[0] == 'l'
- && current_templates->start->name[2] == 's'
- && current_templates->start->name[3] == 0)
- suffix = LONG_MNEM_SUFFIX;
- else if (!intel_parser.got_a_float)
- {
- if (flag_code == CODE_16BIT)
- add_prefix (DATA_PREFIX_OPCODE);
- suffix = LONG_DOUBLE_MNEM_SUFFIX;
- }
- else
- suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
- i.types[this_operand].bitfield.fword = 1;
- }
-
- else if (prev_token.code == T_QWORD)
- {
- if (current_templates->start->base_opcode == 0x62 /* bound */
- || intel_parser.got_a_float == 1) /* "f..." */
- suffix = LONG_MNEM_SUFFIX;
- else
- suffix = QWORD_MNEM_SUFFIX;
- i.types[this_operand].bitfield.qword = 1;
- }
-
- else if (prev_token.code == T_TBYTE)
- {
- if (intel_parser.got_a_float == 1)
- suffix = LONG_DOUBLE_MNEM_SUFFIX;
- else
- suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
- }
-
- else if (prev_token.code == T_XMMWORD)
- {
- suffix = XMMWORD_MNEM_SUFFIX;
- i.types[this_operand].bitfield.xmmword = 1;
- }
-
- else if (prev_token.code == T_YMMWORD)
- {
- suffix = YMMWORD_MNEM_SUFFIX;
- i.types[this_operand].bitfield.ymmword = 1;
- }
-
- else
- {
- as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
- return 0;
- }
-
- i.types[this_operand].bitfield.unspecified = 0;
-
- /* Operands for jump/call using 'ptr' notation denote absolute
- addresses. */
- if (current_templates->start->opcode_modifier.jump
- || current_templates->start->opcode_modifier.jumpdword)
- i.types[this_operand].bitfield.jumpabsolute = 1;
-
- if (current_templates->start->base_opcode == 0x8d /* lea */)
- ;
- else if (!i.suffix)
- i.suffix = suffix;
- else if (i.suffix != suffix)
- {
- as_bad (_("Conflicting operand modifiers"));
- return 0;
- }
-
- }
-
- /* e09' : e10 e09' */
- else if (cur_token.code == ':')
- {
- if (prev_token.code != T_REG)
- {
- /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
- segment/group identifier (which we don't have), using comma
- as the operand separator there is even less consistent, since
- there all branches only have a single operand. */
- if (this_operand != 0
- || intel_parser.in_offset
- || intel_parser.in_bracket
- || (!current_templates->start->opcode_modifier.jump
- && !current_templates->start->opcode_modifier.jumpdword
- && !current_templates->start->opcode_modifier.jumpintersegment
- && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
- return intel_match_token (T_NIL);
- /* Remember the start of the 2nd operand and terminate 1st
- operand here.
- XXX This isn't right, yet (when SSSS:OOOO is right operand of
- another expression), but it gets at least the simplest case
- (a plain number or symbol on the left side) right. */
- intel_parser.next_operand = intel_parser.op_string;
- *--intel_parser.op_string = '\0';
- return intel_match_token (':');
- }
- }
-
- /* e09' Empty */
- else
- break;
-
- intel_match_token (cur_token.code);
-
- }
-
- if (in_offset)
- {
- --intel_parser.in_offset;
- if (nregs < 0)
- nregs = ~nregs;
- if (NUM_ADDRESS_REGS > nregs)
- {
- as_bad (_("Invalid operand to `OFFSET'"));
- return 0;
- }
- intel_parser.op_modifier |= 1 << T_OFFSET;
- }
-
- if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
- i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
- return 1;
-}
-
-static int
-intel_bracket_expr (void)
-{
- int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
- const char *start = intel_parser.op_string;
- int len;
-
- if (i.op[this_operand].regs)
- return intel_match_token (T_NIL);
-
- intel_match_token ('[');
-
- /* Mark as a memory operand only if it's not already known to be an
- offset expression. If it's an offset expression, we need to keep
- the brace in. */
- if (!intel_parser.in_offset)
- {
- ++intel_parser.in_bracket;
-
- /* Operands for jump/call inside brackets denote absolute addresses. */
- if (current_templates->start->opcode_modifier.jump
- || current_templates->start->opcode_modifier.jumpdword)
- i.types[this_operand].bitfield.jumpabsolute = 1;
-
- /* Unfortunately gas always diverged from MASM in a respect that can't
- be easily fixed without risking to break code sequences likely to be
- encountered (the testsuite even check for this): MASM doesn't consider
- an expression inside brackets unconditionally as a memory reference.
- When that is e.g. a constant, an offset expression, or the sum of the
- two, this is still taken as a constant load. gas, however, always
- treated these as memory references. As a compromise, we'll try to make
- offset expressions inside brackets work the MASM way (since that's
- less likely to be found in real world code), but make constants alone
- continue to work the traditional gas way. In either case, issue a
- warning. */
- intel_parser.op_modifier &= ~was_offset;
- }
- else
- strcat (intel_parser.disp, "[");
-
- /* Add a '+' to the displacement string if necessary. */
- if (*intel_parser.disp != '\0'
- && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
- strcat (intel_parser.disp, "+");
-
- if (intel_expr ()
- && (len = intel_parser.op_string - start - 1,
- intel_match_token (']')))
- {
- /* Preserve brackets when the operand is an offset expression. */
- if (intel_parser.in_offset)
- strcat (intel_parser.disp, "]");
- else
- {
- --intel_parser.in_bracket;
- if (i.base_reg || i.index_reg)
- intel_parser.is_mem = 1;
- if (!intel_parser.is_mem)
- {
- if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
- /* Defer the warning until all of the operand was parsed. */
- intel_parser.is_mem = -1;
- else if (!quiet_warnings)
- as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
- len, start, len, start);
- }
- }
- intel_parser.op_modifier |= was_offset;
-
- return 1;
- }
- return 0;
-}
-
-/* e10 e11 e10'
-
- e10' [ expr ] e10'
- | Empty */
-static int
-intel_e10 (void)
-{
- if (!intel_e11 ())
- return 0;
-
- while (cur_token.code == '[')
- {
- if (!intel_bracket_expr ())
- return 0;
- }
-
- return 1;
-}
-
-/* e11 ( expr )
- | [ expr ]
- | BYTE
- | WORD
- | DWORD
- | FWORD
- | QWORD
- | TBYTE
- | OWORD
- | XMMWORD
- | YMMWORD
- | $
- | .
- | register
- | id
- | constant */
-static int
-intel_e11 (void)
-{
- switch (cur_token.code)
- {
- /* e11 ( expr ) */
- case '(':
- intel_match_token ('(');
- strcat (intel_parser.disp, "(");
-
- if (intel_expr () && intel_match_token (')'))
- {
- strcat (intel_parser.disp, ")");
- return 1;
- }
- return 0;
-
- /* e11 [ expr ] */
- case '[':
- return intel_bracket_expr ();
-
- /* e11 $
- | . */
- case '.':
- strcat (intel_parser.disp, cur_token.str);
- intel_match_token (cur_token.code);
-
- /* Mark as a memory operand only if it's not already known to be an
- offset expression. */
- if (!intel_parser.in_offset)
- intel_parser.is_mem = 1;
-
- return 1;
-
- /* e11 register */
- case T_REG:
- {
- const reg_entry *reg = intel_parser.reg = cur_token.reg;
-
- intel_match_token (T_REG);
-
- /* Check for segment change. */
- if (cur_token.code == ':')
- {
- if (!reg->reg_type.bitfield.sreg2
- && !reg->reg_type.bitfield.sreg3)
- {
- as_bad (_("`%s' is not a valid segment register"),
- reg->reg_name);
- return 0;
- }
- else if (i.mem_operands >= 2)
- as_warn (_("Segment override ignored"));
- else if (i.seg[i.mem_operands])
- as_warn (_("Extra segment override ignored"));
- else
- {
- if (!intel_parser.in_offset)
- intel_parser.is_mem = 1;
- switch (reg->reg_num)
- {
- case 0:
- i.seg[i.mem_operands] = &es;
- break;
- case 1:
- i.seg[i.mem_operands] = &cs;
- break;
- case 2:
- i.seg[i.mem_operands] = &ss;
- break;
- case 3:
- i.seg[i.mem_operands] = &ds;
- break;
- case 4:
- i.seg[i.mem_operands] = &fs;
- break;
- case 5:
- i.seg[i.mem_operands] = &gs;
- break;
- }
- }
- }
-
- else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
- {
- as_bad (_("cannot use `FLAT' here"));
- return 0;
- }
-
- /* Not a segment register. Check for register scaling. */
- else if (cur_token.code == '*')
- {
- if (!intel_parser.in_bracket)
- {
- as_bad (_("Register scaling only allowed in memory operands"));
- return 0;
- }
-
- if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
- reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
- else if (i.index_reg)
- reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
-
- /* What follows must be a valid scale. */
- intel_match_token ('*');
- i.index_reg = reg;
- i.types[this_operand].bitfield.baseindex = 1;
-
- /* Set the scale after setting the register (otherwise,
- i386_scale will complain) */
- if (cur_token.code == '+' || cur_token.code == '-')
- {
- char *str, sign = cur_token.code;
- intel_match_token (cur_token.code);
- if (cur_token.code != T_CONST)
- {
- as_bad (_("Syntax error: Expecting a constant, got `%s'"),
- cur_token.str);
- return 0;
- }
- str = (char *) xmalloc (strlen (cur_token.str) + 2);
- strcpy (str + 1, cur_token.str);
- *str = sign;
- if (!i386_scale (str))
- return 0;
- free (str);
- }
- else if (!i386_scale (cur_token.str))
- return 0;
- intel_match_token (cur_token.code);
- }
-
- /* No scaling. If this is a memory operand, the register is either a
- base register (first occurrence) or an index register (second
- occurrence). */
- else if (intel_parser.in_bracket)
- {
-
- if (!i.base_reg)
- i.base_reg = reg;
- else if (!i.index_reg)
- i.index_reg = reg;
- else
- {
- as_bad (_("Too many register references in memory operand"));
- return 0;
- }
-
- i.types[this_operand].bitfield.baseindex = 1;
- }
-
- /* It's neither base nor index. */
- else if (!intel_parser.in_offset && !intel_parser.is_mem)
- {
- i386_operand_type temp = reg->reg_type;
- temp.bitfield.baseindex = 0;
- i.types[this_operand] = operand_type_or (i.types[this_operand],
- temp);
- i.types[this_operand].bitfield.unspecified = 0;
- i.op[this_operand].regs = reg;
- i.reg_operands++;
- }
- else
- {
- as_bad (_("Invalid use of register"));
- return 0;
- }
-
- /* Since registers are not part of the displacement string (except
- when we're parsing offset operands), we may need to remove any
- preceding '+' from the displacement string. */
- if (*intel_parser.disp != '\0'
- && !intel_parser.in_offset)
- {
- char *s = intel_parser.disp;
- s += strlen (s) - 1;
- if (*s == '+')
- *s = '\0';
- }
-
- return 1;
- }
-
- /* e11 BYTE
- | WORD
- | DWORD
- | FWORD
- | QWORD
- | TBYTE
- | OWORD
- | XMMWORD
- | YMMWORD */
- case T_BYTE:
- case T_WORD:
- case T_DWORD:
- case T_FWORD:
- case T_QWORD:
- case T_TBYTE:
- case T_XMMWORD:
- case T_YMMWORD:
- intel_match_token (cur_token.code);
-
- if (cur_token.code == T_PTR)
- return 1;
-
- /* It must have been an identifier. */
- intel_putback_token ();
- cur_token.code = T_ID;
- /* FALLTHRU */
-
- /* e11 id
- | constant */
- case T_ID:
- if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
- {
- symbolS *symbolP;
-
- /* The identifier represents a memory reference only if it's not
- preceded by an offset modifier and if it's not an equate. */
- symbolP = symbol_find(cur_token.str);
- if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
- intel_parser.is_mem = 1;
- }
- /* FALLTHRU */
-
- case T_CONST:
- case '-':
- case '+':
- {
- char *save_str, sign = 0;
-
- /* Allow constants that start with `+' or `-'. */
- if (cur_token.code == '-' || cur_token.code == '+')
- {
- sign = cur_token.code;
- intel_match_token (cur_token.code);
- if (cur_token.code != T_CONST)
- {
- as_bad (_("Syntax error: Expecting a constant, got `%s'"),
- cur_token.str);
- return 0;
- }
- }
-
- save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
- strcpy (save_str + !!sign, cur_token.str);
- if (sign)
- *save_str = sign;
-
- /* Get the next token to check for register scaling. */
- intel_match_token (cur_token.code);
-
- /* Check if this constant is a scaling factor for an
- index register. */
- if (cur_token.code == '*')
- {
- if (intel_match_token ('*') && cur_token.code == T_REG)
- {
- const reg_entry *reg = cur_token.reg;
-
- if (!intel_parser.in_bracket)
- {
- as_bad (_("Register scaling only allowed "
- "in memory operands"));
- return 0;
- }
-
- /* Disallow things like [1*si].
- sp and esp are invalid as index. */
- if (reg->reg_type.bitfield.reg16)
- reg = i386_regtab + REGNAM_AX + 4;
- else if (i.index_reg)
- reg = i386_regtab + REGNAM_EAX + 4;
-
- /* The constant is followed by `* reg', so it must be
- a valid scale. */
- i.index_reg = reg;
- i.types[this_operand].bitfield.baseindex = 1;
-
- /* Set the scale after setting the register (otherwise,
- i386_scale will complain) */
- if (!i386_scale (save_str))
- return 0;
- intel_match_token (T_REG);
-
- /* Since registers are not part of the displacement
- string, we may need to remove any preceding '+' from
- the displacement string. */
- if (*intel_parser.disp != '\0')
- {
- char *s = intel_parser.disp;
- s += strlen (s) - 1;
- if (*s == '+')
- *s = '\0';
- }
-
- free (save_str);
-
- return 1;
- }
-
- /* The constant was not used for register scaling. Since we have
- already consumed the token following `*' we now need to put it
- back in the stream. */
- intel_putback_token ();
- }
-
- /* Add the constant to the displacement string. */
- strcat (intel_parser.disp, save_str);
- free (save_str);
-
- return 1;
- }
- }
-
- as_bad (_("Unrecognized token '%s'"), cur_token.str);
- return 0;
-}
-
-/* Match the given token against cur_token. If they match, read the next
- token from the operand string. */
-static int
-intel_match_token (int code)
-{
- if (cur_token.code == code)
- {
- intel_get_token ();
- return 1;
- }
- else
- {
- as_bad (_("Unexpected token `%s'"), cur_token.str);
- return 0;
- }
-}
-
-/* Read a new token from intel_parser.op_string and store it in cur_token. */
-static void
-intel_get_token (void)
-{
- char *end_op;
- const reg_entry *reg;
- struct intel_token new_token;
-
- new_token.code = T_NIL;
- new_token.reg = NULL;
- new_token.str = NULL;
-
- /* Free the memory allocated to the previous token and move
- cur_token to prev_token. */
- if (prev_token.str)
- free (prev_token.str);
-
- prev_token = cur_token;
-
- /* Skip whitespace. */
- while (is_space_char (*intel_parser.op_string))
- intel_parser.op_string++;
-
- /* Return an empty token if we find nothing else on the line. */
- if (*intel_parser.op_string == '\0')
- {
- cur_token = new_token;
- return;
- }
-
- /* The new token cannot be larger than the remainder of the operand
- string. */
- new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
- new_token.str[0] = '\0';
-
- if (strchr ("0123456789", *intel_parser.op_string))
- {
- char *p = new_token.str;
- char *q = intel_parser.op_string;
- new_token.code = T_CONST;
-
- /* Allow any kind of identifier char to encompass floating point and
- hexadecimal numbers. */
- while (is_identifier_char (*q))
- *p++ = *q++;
- *p = '\0';
-
- /* Recognize special symbol names [0-9][bf]. */
- if (strlen (intel_parser.op_string) == 2
- && (intel_parser.op_string[1] == 'b'
- || intel_parser.op_string[1] == 'f'))
- new_token.code = T_ID;
- }
-
- else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
- {
- size_t len = end_op - intel_parser.op_string;
-
- new_token.code = T_REG;
- new_token.reg = reg;
-
- memcpy (new_token.str, intel_parser.op_string, len);
- new_token.str[len] = '\0';
- }
-
- else if (is_identifier_char (*intel_parser.op_string))
- {
- char *p = new_token.str;
- char *q = intel_parser.op_string;
-
- /* A '.' or '$' followed by an identifier char is an identifier.
- Otherwise, it's operator '.' followed by an expression. */
- if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
- {
- new_token.code = '.';
- new_token.str[0] = '.';
- new_token.str[1] = '\0';
- }
- else
- {
- while (is_identifier_char (*q) || *q == '@')
- *p++ = *q++;
- *p = '\0';
-
- if (strcasecmp (new_token.str, "NOT") == 0)
- new_token.code = '~';
-
- else if (strcasecmp (new_token.str, "MOD") == 0)
- new_token.code = '%';
-
- else if (strcasecmp (new_token.str, "AND") == 0)
- new_token.code = '&';
-
- else if (strcasecmp (new_token.str, "OR") == 0)
- new_token.code = '|';
-
- else if (strcasecmp (new_token.str, "XOR") == 0)
- new_token.code = '^';
-
- else if (strcasecmp (new_token.str, "SHL") == 0)
- new_token.code = T_SHL;
-
- else if (strcasecmp (new_token.str, "SHR") == 0)
- new_token.code = T_SHR;
-
- else if (strcasecmp (new_token.str, "BYTE") == 0)
- new_token.code = T_BYTE;
-
- else if (strcasecmp (new_token.str, "WORD") == 0)
- new_token.code = T_WORD;
-
- else if (strcasecmp (new_token.str, "DWORD") == 0)
- new_token.code = T_DWORD;
-
- else if (strcasecmp (new_token.str, "FWORD") == 0)
- new_token.code = T_FWORD;
-
- else if (strcasecmp (new_token.str, "QWORD") == 0)
- new_token.code = T_QWORD;
-
- else if (strcasecmp (new_token.str, "TBYTE") == 0
- /* XXX remove (gcc still uses it) */
- || strcasecmp (new_token.str, "XWORD") == 0)
- new_token.code = T_TBYTE;
-
- else if (strcasecmp (new_token.str, "XMMWORD") == 0
- || strcasecmp (new_token.str, "OWORD") == 0)
- new_token.code = T_XMMWORD;
-
- else if (strcasecmp (new_token.str, "YMMWORD") == 0)
- new_token.code = T_YMMWORD;
-
- else if (strcasecmp (new_token.str, "PTR") == 0)
- new_token.code = T_PTR;
-
- else if (strcasecmp (new_token.str, "SHORT") == 0)
- new_token.code = T_SHORT;
-
- else if (strcasecmp (new_token.str, "OFFSET") == 0)
- {
- new_token.code = T_OFFSET;
-
- /* ??? This is not mentioned in the MASM grammar but gcc
- makes use of it with -mintel-syntax. OFFSET may be
- followed by FLAT: */
- if (strncasecmp (q, " FLAT:", 6) == 0)
- strcat (new_token.str, " FLAT:");
- }
-
- else
- new_token.code = T_ID;
- }
- }
-
- else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
- {
- new_token.code = *intel_parser.op_string;
- new_token.str[0] = *intel_parser.op_string;
- new_token.str[1] = '\0';
- }
-
- else if (strchr ("<>", *intel_parser.op_string)
- && *intel_parser.op_string == *(intel_parser.op_string + 1))
- {
- new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
- new_token.str[0] = *intel_parser.op_string;
- new_token.str[1] = *intel_parser.op_string;
- new_token.str[2] = '\0';
- }
-
- else
- as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
-
- intel_parser.op_string += strlen (new_token.str);
- cur_token = new_token;
-}
-
-/* Put cur_token back into the token stream and make cur_token point to
- prev_token. */
-static void
-intel_putback_token (void)
-{
- if (cur_token.code != T_NIL)
- {
- intel_parser.op_string -= strlen (cur_token.str);
- free (cur_token.str);
- }
- cur_token = prev_token;
-
- /* Forget prev_token. */
- prev_token.code = T_NIL;
- prev_token.reg = NULL;
- prev_token.str = NULL;
-}
-
-void
-tc_x86_parse_to_dw2regnum (expressionS *exp)
-{
- int saved_naked_reg;
- char saved_register_dot;
-
- saved_naked_reg = allow_naked_reg;
- allow_naked_reg = 1;
- saved_register_dot = register_chars['.'];
- register_chars['.'] = '.';
- allow_pseudo_reg = 1;
- expression_and_evaluate (exp);
- allow_pseudo_reg = 0;
- register_chars['.'] = saved_register_dot;
- allow_naked_reg = saved_naked_reg;
-
- if (exp->X_op == O_register && exp->X_add_number >= 0)
- {
- if ((addressT) exp->X_add_number < i386_regtab_size)
- {
- exp->X_op = O_constant;
- exp->X_add_number = i386_regtab[exp->X_add_number]
- .dw2_regnum[flag_code >> 1];
- }
- else
- exp->X_op = O_illegal;
- }
-}
-
-void
-tc_x86_frame_initial_instructions (void)
-{
- static unsigned int sp_regno[2];
-
- if (!sp_regno[flag_code >> 1])
- {
- char *saved_input = input_line_pointer;
- char sp[][4] = {"esp", "rsp"};
- expressionS exp;
-
- input_line_pointer = sp[flag_code >> 1];
- tc_x86_parse_to_dw2regnum (&exp);
- assert (exp.X_op == O_constant);
- sp_regno[flag_code >> 1] = exp.X_add_number;
- input_line_pointer = saved_input;
- }
-
- cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
- cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
-}
-
-int
-i386_elf_section_type (const char *str, size_t len)
-{
- if (flag_code == CODE_64BIT
- && len == sizeof ("unwind") - 1
- && strncmp (str, "unwind", 6) == 0)
- return SHT_X86_64_UNWIND;
-
- return -1;
-}
-
-#ifdef TE_SOLARIS
-void
-i386_solaris_fix_up_eh_frame (segT sec)
-{
- if (flag_code == CODE_64BIT)
- elf_section_type (sec) = SHT_X86_64_UNWIND;
-}
-#endif
-
-#ifdef TE_PE
-void
-tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
-{
- expressionS expr;
-
- expr.X_op = O_secrel;
- expr.X_add_symbol = symbol;
- expr.X_add_number = 0;
- emit_expr (&expr, size);
-}
-#endif
-
-#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
-/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
-
-int
-x86_64_section_letter (int letter, char **ptr_msg)
-{
- if (flag_code == CODE_64BIT)
- {
- if (letter == 'l')
- return SHF_X86_64_LARGE;
-
- *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
- }
- else
- *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
- return -1;
-}
-
-int
+bfd_vma
x86_64_section_word (char *str, size_t len)
{
if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))