x86/Intel: correct MOVSD and CMPSD handling

[deliverable/binutils-gdb.git] / gas / config / tc-i386.h

diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h
index c7c53bea61a5292369e08bc9e754a3f8eb83edc7..b02a25671f5978546c5d7f6930ff09729796862e 100644 (file)
--- a/gas/config/tc-i386.h
+++ b/gas/config/tc-i386.h
@@ -1,5 +1,5 @@
 /* tc-i386.h -- Header file for tc-i386.c
-   Copyright (C) 1989-2018 Free Software Foundation, Inc.
+   Copyright (C) 1989-2019 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -63,6 +63,8 @@ extern unsigned long i386_mach (void);
 #define ELF_TARGET_FORMAT      "elf32-i386-nacl"
 #define ELF_TARGET_FORMAT32    "elf32-x86-64-nacl"
 #define ELF_TARGET_FORMAT64    "elf64-x86-64-nacl"
+#elif defined TE_CLOUDABI
+#define ELF_TARGET_FORMAT64    "elf64-x86-64-cloudabi"
 #endif
 
 #ifdef TE_SOLARIS
@@ -174,6 +176,7 @@ extern int tc_i386_fix_adjustable (struct fix *);
   (GENERIC_FORCE_RELOCATION_LOCAL (FIX)                                \
    || (FIX)->fx_r_type == BFD_RELOC_386_PLT32                  \
    || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC                  \
+   || (FIX)->fx_r_type == BFD_RELOC_X86_64_GOTPCREL            \
    || (FIX)->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX           \
    || (FIX)->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX)
 
@@ -205,7 +208,7 @@ if ((n)                                                                     \
     goto around;                                                       \
   }
 
-#define MAX_MEM_FOR_RS_ALIGN_CODE 4095
+#define MAX_MEM_FOR_RS_ALIGN_CODE  (alignment ? ((1 << alignment) - 1) : 1)
 
 void i386_print_statistics (FILE *);
 #define tc_print_statistics i386_print_statistics
@@ -250,6 +253,7 @@ struct i386_tc_frag_data
   enum processor_type isa;
   i386_cpu_flags isa_flags;
   enum processor_type tune;
+  unsigned int max_bytes;
 };
 
 /* We need to emit the right NOP pattern in .align frags.  This is
@@ -257,20 +261,16 @@ struct i386_tc_frag_data
    the isa/tune settings at the time the .align was assembled.  */
 #define TC_FRAG_TYPE struct i386_tc_frag_data
 
-#define TC_FRAG_INIT(FRAGP)                                    \
+#define TC_FRAG_INIT(FRAGP, MAX_BYTES)                         \
  do                                                            \
    {                                                           \
      (FRAGP)->tc_frag_data.isa = cpu_arch_isa;                 \
      (FRAGP)->tc_frag_data.isa_flags = cpu_arch_isa_flags;     \
      (FRAGP)->tc_frag_data.tune = cpu_arch_tune;               \
+     (FRAGP)->tc_frag_data.max_bytes = (MAX_BYTES);            \
    }                                                           \
  while (0)
 
-#ifdef SCO_ELF
-#define tc_init_after_args() sco_id ()
-extern void sco_id (void);
-#endif
-
 #define WORKING_DOT_WORD 1
 
 /* How to generate NOPs for .nop direct directive.  */
@@ -284,7 +284,8 @@ if (fragP->fr_type == rs_align_code)                                        \
     offsetT __count = (fragP->fr_next->fr_address                      \
                       - fragP->fr_address                              \
                       - fragP->fr_fix);                                \
-    if (__count > 0 && __count <= MAX_MEM_FOR_RS_ALIGN_CODE)           \
+    if (__count > 0                                                    \
+       && (unsigned int) __count <= fragP->tc_frag_data.max_bytes)     \
       md_generate_nops (fragP, fragP->fr_literal + fragP->fr_fix,      \
                        __count, 0);                                    \
   }
@@ -321,6 +322,11 @@ extern bfd_vma x86_64_section_letter (int, const char **);
 #define md_elf_section_letter(LETTER, PTR_MSG) x86_64_section_letter (LETTER, PTR_MSG)
 #define md_elf_section_word(STR, LEN)          x86_64_section_word (STR, LEN)
 
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+extern void x86_cleanup (void);
+#define md_cleanup() x86_cleanup ()
+#endif
+
 #ifdef TE_PE
 
 #define O_secrel O_md1