/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
- Copyright (C) 1998-2016 Free Software Foundation, Inc.
+ Copyright (C) 1998-2019 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GAS, the GNU Assembler.
struct hash_control *const_hash; /* constant hash table */
struct hash_control *entry_hash; /* code entry hint hash table */
- /* If X_op is != O_absent, the registername for the instruction's
+ /* If X_op is != O_absent, the register name for the instruction's
qualifying predicate. If NULL, p0 is assumed for instructions
that are predictable. */
expressionS qp;
demand_empty_rest_of_line ();
obj_elf_change_section
- (sec_name, SHT_NOBITS,
+ (sec_name, SHT_NOBITS, 0,
SHF_ALLOC | SHF_WRITE | SHF_IA_64_VMS_OVERLAID | SHF_IA_64_VMS_GLOBAL,
0, NULL, 1, 0);
as_fatal (_("Only constant offsets are supported"));
break;
}
+ /* Fall through. */
case rs_fill:
s_index += 3 * (first_frag->fr_offset >> 4);
break;
for (ptr = list; ptr; ptr = ptr->next)
{
if (ptr->slot_number == SLOT_NUM_NOT_SET)
- as_bad (_(" Insn slot not set in unwind record."));
+ as_bad (_("Insn slot not set in unwind record."));
t = slot_index (ptr->slot_number, ptr->slot_frag,
first_addr, first_frag, before_relax);
switch (ptr->r.type)
e2.X_op = O_absent;
reg1 = e1.X_add_number;
- /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
+ /* Make sure it's a valid ar.xxx reg, OR its br0, aka 'rp'. */
if (e1.X_op != O_register)
{
as_bad (_("First operand to .save not a register"));
reg1 = e1.X_add_number;
val = e2.X_add_number;
- /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
+ /* Make sure it's a valid ar.xxx reg, OR its br0, aka 'rp'. */
if (e1.X_op != O_register)
{
as_bad (_("First operand to .%s not a register"), po);
if (!*drpp)
{
- *drpp = obstack_alloc (¬es, sizeof (*dr));
+ *drpp = XOBNEW (¬es, struct dynreg);
memset (*drpp, 0, sizeof (*dr));
}
- name = obstack_alloc (¬es, len + 1);
+ name = XOBNEWVEC (¬es, char, len + 1);
memcpy (name, start, len);
name[len] = '\0';
/* SOR must be an integer multiple of 8 */
if (e->X_op == O_constant && e->X_add_number & 0x7)
return OPERAND_OUT_OF_RANGE;
+ /* Fall through. */
case IA64_OPND_SOF:
case IA64_OPND_SOL:
if (e->X_op == O_constant)
case IA64_OPND_IMM14:
case IA64_OPND_IMM22:
relocatable = 1;
+ /* Fall through. */
case IA64_OPND_IMM1:
case IA64_OPND_IMM8:
case IA64_OPND_IMM8U4:
++CURR_SLOT.num_fixups;
return OPERAND_MATCH;
}
+ /* Fall through. */
case IA64_OPND_TAG13:
case IA64_OPND_TAG13b:
switch (e->X_op)
labels. */
if (defining_tag)
{
- fix = obstack_alloc (¬es, sizeof (*fix));
+ fix = XOBNEW (¬es, struct label_fix);
fix->sym = sym;
fix->next = CURR_SLOT.tag_fixups;
fix->dw2_mark_labels = FALSE;
if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
{
md.last_text_seg = now_seg;
- fix = obstack_alloc (¬es, sizeof (*fix));
+ fix = XOBNEW (¬es, struct label_fix);
fix->sym = sym;
fix->next = CURR_SLOT.label_fixups;
fix->dw2_mark_labels = dwarf2_loc_mark_labels;
{
specs[count++] = tmpl;
}
+ /* Fall through. */
case AR_RSC:
if (!rsrc_write &&
(regno == AR_BSPSTORE
case IA64_DVS_SPECIFIC:
if (md.debug_dv)
fprintf (stderr, "Implementation-specific, assume worst case...\n");
- /* ...fall through... */
+ /* Fall through. */
case IA64_DVS_INSTR:
if (md.debug_dv)
fprintf (stderr, "Inserting instr serialization\n");