-/* tc-m32r.c -- Assembler for the Mitsubishi M32R/X.
- Copyright (C) 1996, 1997 Free Software Foundation.
+/* tc-m32r.c -- Assembler for the Mitsubishi M32R.
+ Copyright (C) 1996, 1997, 1998 Free Software Foundation.
This file is part of GAS, the GNU Assembler.
#include "subsegs.h"
#include "cgen-opc.h"
-/* Non-null if last insn was a 16 bit insn on a 32 bit boundary
- (i.e. was the first of two 16 bit insns). */
-static const CGEN_INSN *prev_insn = NULL;
+typedef struct
+{
+ const CGEN_INSN * insn;
+ CGEN_FIELDS fields;
+#ifdef CGEN_INT_INSN
+ cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
+#else
+ char buffer [CGEN_MAX_INSN_SIZE];
+#endif
+ char * addr;
+ fragS * frag;
+ int indices [MAX_OPERAND_INSTANCES];
+}
+m32r_insn;
+
+/* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
+ boundary (i.e. was the first of two 16 bit insns). */
+static m32r_insn prev_insn;
/* Non-zero if we've seen a relaxable insn since the last 32 bit
alignment request. */
/* If non-NULL, pointer to cpu description file to read.
This allows runtime additions to the assembler. */
-static char *m32r_cpu_desc;
+static char * m32r_cpu_desc;
/* start-sanitize-m32rx */
/* Non-zero if -m32rx has been specified, in which case support for the
extended M32RX instruction set should be enabled. */
-/* Indicates the target BFD machine number. */
static int enable_m32rx = 0;
+
+/* Non-zero if the programmer should be warned when an explicit parallel
+ instruction might have constraint violations. */
+static int warn_explicit_parallel_conflicts = 1;
/* end-sanitize-m32rx */
/* stuff for .scomm symbols. */
-static segT sbss_section;
+static segT sbss_section;
static asection scom_section;
-static asymbol scom_symbol;
+static asymbol scom_symbol;
-const char comment_chars[] = ";";
-const char line_comment_chars[] = "#";
+const char comment_chars[] = ";";
+const char line_comment_chars[] = "#";
const char line_separator_chars[] = "";
-const char EXP_CHARS[] = "eE";
-const char FLT_CHARS[] = "dD";
+const char EXP_CHARS[] = "eE";
+const char FLT_CHARS[] = "dD";
/* Relocations against symbols are done in two
parts, with a HI relocation and a LO relocation. Each relocation
struct m32r_hi_fixup
{
- /* Next HI fixup. */
- struct m32r_hi_fixup *next;
- /* This fixup. */
- fixS *fixp;
- /* The section this fixup is in. */
- segT seg;
+ struct m32r_hi_fixup * next; /* Next HI fixup. */
+ fixS * fixp; /* This fixup. */
+ segT seg; /* The section this fixup is in. */
+
};
/* The list of unmatched HI relocs. */
-static struct m32r_hi_fixup *m32r_hi_fixup_list;
-
-static void m32r_record_hi16 PARAMS ((int, fixS *, segT seg));
+static struct m32r_hi_fixup * m32r_hi_fixup_list;
\f
/* start-sanitize-m32rx */
static void
-allow_m32rx (int on)
+allow_m32rx (on)
+ int on;
{
enable_m32rx = on;
if (stdoutput != NULL)
- bfd_set_arch_mach (stdoutput, TARGET_ARCH, enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
+ bfd_set_arch_mach (stdoutput, TARGET_ARCH,
+ enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
}
/* end-sanitize-m32rx */
\f
-const char *md_shortopts = "";
+const char * md_shortopts = "";
struct option md_longopts[] =
{
/* start-sanitize-m32rx */
#define OPTION_M32RX (OPTION_MD_BASE)
{"m32rx", no_argument, NULL, OPTION_M32RX},
+#define OPTION_WARN (OPTION_MD_BASE + 1)
+ {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN},
+#define OPTION_NO_WARN (OPTION_MD_BASE + 2)
+ {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN},
/* end-sanitize-m32rx */
#if 0 /* not supported yet */
-#define OPTION_RELAX (OPTION_MD_BASE + 1)
+#define OPTION_RELAX (OPTION_MD_BASE + 3)
{"relax", no_argument, NULL, OPTION_RELAX},
-#define OPTION_CPU_DESC (OPTION_MD_BASE + 2)
+#define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
{"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
#endif
{NULL, no_argument, NULL, 0}
};
-size_t md_longopts_size = sizeof(md_longopts);
+size_t md_longopts_size = sizeof (md_longopts);
int
md_parse_option (c, arg)
- int c;
- char *arg;
+ int c;
+ char * arg;
{
switch (c)
{
case OPTION_M32RX:
allow_m32rx (1);
break;
+
+ case OPTION_WARN:
+ warn_explicit_parallel_conflicts = 1;
+ break;
+
+ case OPTION_NO_WARN:
+ warn_explicit_parallel_conflicts = 0;
+ break;
/* end-sanitize-m32rx */
#if 0 /* not supported yet */
void
md_show_usage (stream)
- FILE *stream;
+ FILE * stream;
{
fprintf (stream, "M32R/X options:\n");
/* start-sanitize-m32rx */
fprintf (stream, "\
--m32rx support the extended m32rx instruction set\n");
+
+ fprintf (stream, "\
+--warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\n");
+ fprintf (stream, "\
+--no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n");
/* end-sanitize-m32rx */
#if 0
int
m32r_do_align (n, fill, len, max)
- int n;
- const char *fill;
- int len;
- int max;
+ int n;
+ const char * fill;
+ int len;
+ int max;
{
- if ((fill == NULL || (*fill == 0 && len == 1))
+ if ((fill == NULL || (* fill == 0 && len == 1))
&& (now_seg->flags & SEC_CODE) != 0
/* Only do this special handling if aligning to at least a
4 byte boundary. */
&& n > 1
- /* Only do this special handling if we're allowed to emit at
+ /* Only do this special handling if we're allowed to emit at
least two bytes. */
&& (max == 0 || max > 1))
{
nops. */
if (n > 2)
{
- static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 };
+ static const unsigned char multi_nop_pattern[] =
+ { 0x70, 0x00, 0xf0, 0x00 };
frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
max ? max - 2 : 0);
}
assemble_nop (opcode)
int opcode;
{
- char *f = frag_more (2);
+ char * f = frag_more (2);
md_number_to_chars (f, opcode, 2);
}
int ignore;
{
(void) m32r_do_align (2, NULL, 0, 0);
- prev_insn = NULL;
+ prev_insn.insn = NULL;
seen_relaxable_p = 0;
}
m32r_fill_insn (done)
int done;
{
- segT seg;
+ segT seg;
subsegT subseg;
if (prev_seg != NULL)
{
- seg = now_seg;
+ seg = now_seg;
subseg = now_subseg;
+
subseg_set (prev_seg, prev_subseg);
+
fill_insn (0);
+
subseg_set (seg, subseg);
}
+
return 1;
}
\f
md_begin ()
{
flagword applicable;
- segT seg;
- subsegT subseg;
+ segT seg;
+ subsegT subseg;
/* Initialize the `cgen' interface. */
/* This is a callback from cgen to gas to parse operands. */
cgen_parse_operand_fn = cgen_parse_operand;
+
/* Set the machine number and endian. */
CGEN_SYM (init_asm) (0 /* mach number */,
- target_big_endian ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
+ target_big_endian ?
+ CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
#if 0 /* not supported yet */
/* If a runtime cpu description file was provided, parse it. */
if (m32r_cpu_desc != NULL)
{
- const char *errmsg;
+ const char * errmsg;
errmsg = cgen_read_cpu_file (m32r_cpu_desc);
if (errmsg != NULL)
#endif
/* Save the current subseg so we can restore it [it's the default one and
- we don't want the initial section to be .sbss. */
- seg = now_seg;
+ we don't want the initial section to be .sbss]. */
+ seg = now_seg;
subseg = now_subseg;
/* The sbss section is for local .scomm symbols. */
sbss_section = subseg_new (".sbss", 0);
+
/* This is copied from perform_an_assembly_pass. */
applicable = bfd_applicable_section_flags (stdoutput);
bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
+
#if 0 /* What does this do? [see perform_an_assembly_pass] */
seg_info (bss_section)->bss = 1;
#endif
/* We must construct a fake section similar to bfd_com_section
but with the name .scommon. */
- scom_section = bfd_com_section;
- scom_section.name = ".scommon";
- scom_section.output_section = &scom_section;
- scom_section.symbol = &scom_symbol;
- scom_section.symbol_ptr_ptr = &scom_section.symbol;
- scom_symbol = *bfd_com_section.symbol;
- scom_symbol.name = ".scommon";
- scom_symbol.section = &scom_section;
+ scom_section = bfd_com_section;
+ scom_section.name = ".scommon";
+ scom_section.output_section = & scom_section;
+ scom_section.symbol = & scom_symbol;
+ scom_section.symbol_ptr_ptr = & scom_section.symbol;
+ scom_symbol = * bfd_com_section.symbol;
+ scom_symbol.name = ".scommon";
+ scom_symbol.section = & scom_section;
/* start-sanitize-m32rx */
allow_m32rx (enable_m32rx);
/* end-sanitize-m32rx */
}
-void
-md_assemble (str)
- char *str;
+/* start-sanitize-m32rx */
+#ifdef HAVE_CPU_M32RX
+
+/* Returns true if an output of instruction 'a' is referenced by an operand
+ of instruction 'b'. If 'check_outputs' is true then b's outputs are
+ checked, otherwise its inputs are examined. */
+static int
+first_writes_to_seconds_operands (a, b, check_outputs)
+ m32r_insn * a;
+ m32r_insn * b;
+ const int check_outputs;
+{
+ const CGEN_OPERAND_INSTANCE * a_operands = CGEN_INSN_OPERANDS (a->insn);
+ const CGEN_OPERAND_INSTANCE * b_operands = CGEN_INSN_OPERANDS (b->insn);
+ int a_index;
+
+ /* If at least one of the instructions take sno opeands, then there is
+ nothing to check. There really are instructions without operands,
+ eg 'nop'. */
+ if (a_operands == NULL || b_operands == NULL)
+ return 0;
+
+ /* Scan the operand list of 'a' looking for an output operand. */
+ for (a_index = 0;
+ CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END;
+ a_index ++, a_operands ++)
+ {
+ if (CGEN_OPERAND_INSTANCE_TYPE (a_operands) == CGEN_OPERAND_INSTANCE_OUTPUT)
+ {
+ int b_index;
+
+ /* Scan operand list of 'b' looking for an operand that references
+ the same hardware element, and which goes in the right direction. */
+ for (b_index = 0;
+ CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END;
+ b_index ++, b_operands ++)
+ {
+ if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) ==
+ (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT))
+ && (CGEN_OPERAND_INSTANCE_HW (b_operands) == CGEN_OPERAND_INSTANCE_HW (a_operands))
+ && (a->indices [a_index] == b->indices [b_index]))
+ return 1;
+ }
+ }
+ }
+
+ return 0;
+}
+
+/* Returns true if the insn can (potentially) alter the program counter. */
+static int
+writes_to_pc (a)
+ m32r_insn * a;
+{
+#if 0
+ const CGEN_OPERAND_INSTANCE * a_operands == CGEN_INSN_OPERANDS (a->insn);
+
+ if (a_operands == NULL)
+ return 0;
+
+ while (CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END)
+ {
+ if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands) != NULL
+ && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC)
+ return 1;
+
+ a_operands ++;
+ }
+#else
+ if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_UNCOND_CTI)
+ || CGEN_INSN_ATTR (a->insn, CGEN_INSN_COND_CTI))
+ return 1;
+#endif
+ return 0;
+}
+
+/* Returns NULL if the two 16 bit insns can be executed in parallel,
+ otherwise it returns a pointer to an error message explaining why not. */
+static const char *
+can_make_parallel (a, b)
+ m32r_insn * a;
+ m32r_insn * b;
{
+ PIPE_ATTR a_pipe;
+ PIPE_ATTR b_pipe;
+
+ /* Make sure the instructions are the right length. */
+ if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16
+ || CGEN_FIELDS_BITSIZE (& b->fields) != 16)
+ abort();
+
+ if (first_writes_to_seconds_operands (a, b, true))
+ return "Instructions write to the same destination register.";
+
+ a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE);
+ b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE);
+
+ /* Make sure that the instructions use the correct execution pipelines. */
+ if ( a_pipe == PIPE_NONE
+ || b_pipe == PIPE_NONE)
+ return "Instructions do not use parallel execution pipelines.";
+
+ /* Leave this test for last, since it is the only test that can
+ go away if the instructions are swapped, and we want to make
+ sure that any other errors are detected before this happens. */
+ if ( a_pipe == PIPE_S
+ || b_pipe == PIPE_O)
+ return "Instructions share the same execution pipeline";
+
+ return NULL;
+}
+
#ifdef CGEN_INT_INSN
- cgen_insn_t buffer[CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
+static void
+make_parallel (buffer)
+ cgen_insn_t * buffer;
+{
+ /* Force the top bit of the second insn to be set. */
+
+ bfd_vma value;
+
+ if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
+ {
+ value = bfd_getb16 ((bfd_byte *) buffer);
+ value |= 0x8000;
+ bfd_putb16 (value, (char *) buffer);
+ }
+ else
+ {
+ value = bfd_getl16 ((bfd_byte *) buffer);
+ value |= 0x8000;
+ bfd_putl16 (value, (char *) buffer);
+ }
+}
#else
- char buffer[CGEN_MAX_INSN_SIZE];
+static void
+make_parallel (buffer)
+ char * buffer;
+{
+ /* Force the top bit of the second insn to be set. */
+
+ buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80;
+}
#endif
- CGEN_FIELDS fields;
- const CGEN_INSN *insn;
- char *errmsg;
+
+
+static void
+assemble_parallel_insn (str, str2)
+ char * str;
+ char * str2;
+{
+ char * str3;
+ m32r_insn first;
+ m32r_insn second;
+ char * errmsg;
+
+ * str2 = 0; /* Seperate the two instructions. */
+
+ /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
+ so that the parallel instruction will start on a 32 bit boundary. */
+ if (prev_insn.insn)
+ fill_insn (0);
+
+ /* Parse the first instruction. */
+ if (! (first.insn = CGEN_SYM (assemble_insn)
+ (str, & first.fields, first.buffer, & errmsg)))
+ {
+ as_bad (errmsg);
+ return;
+ }
+
+ /* Check to see if this is an allowable parallel insn. */
+ if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
+ {
+ as_bad ("instruction '%s' cannot be executed in parallel.", str);
+ return;
+ }
+
+ if (! enable_m32rx
+ && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
+ {
+ as_bad ("instruction '%s' is for the M32RX only", str);
+ return;
+ }
+
+ *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
+ str3 = str; /* Save the original string pointer. */
+ str = str2 + 2; /* Advanced past the parsed string. */
+ str2 = str3; /* Remember the entire string in case it is needed for error messages. */
+
+ /* Preserve any fixups that have been generated and reset the list to empty. */
+ cgen_save_fixups();
+
+ /* Get the indicies of the operands of the instruction. */
+ /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
+ doesn't seem right. Perhaps allow passing fields like we do insn. */
+ /* FIXME: ALIAS insns do not have operands, so we use this function
+ to find the equivalent insn and overwrite the value stored in our
+ structure. When aliases behave differently this may have to change. */
+ first.insn = m32r_cgen_get_insn_operands (first.insn, bfd_getb16 ((char *) first.buffer), 16,
+ first.indices);
+ if (first.insn == NULL)
+ as_fatal ("internal error: m32r_cgen_get_insn_operands failed for first insn");
+
+ /* Parse the second instruction. */
+ if (! (second.insn = CGEN_SYM (assemble_insn)
+ (str, & second.fields, second.buffer, & errmsg)))
+ {
+ as_bad (errmsg);
+ return;
+ }
+
+ /* Check it. */
+ if (! enable_m32rx
+ && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
+ {
+ as_bad ("instruction '%s' is for the M32RX only", str);
+ return;
+ }
+
+ if (! enable_m32rx)
+ {
+ if ( strcmp (first.insn->name, "nop") != 0
+ && strcmp (second.insn->name, "nop") != 0)
+ {
+ as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2);
+ return;
+ }
+ }
+
+ /* Get the indicies of the operands of the instruction. */
+ second.insn = m32r_cgen_get_insn_operands (second.insn, bfd_getb16 ((char *) second.buffer), 16,
+ second.indices);
+ if (second.insn == NULL)
+ as_fatal ("internal error: m32r_cgen_get_insn_operands failed for second insn");
+
+ /* We assume that if the first instruction writes to a register that is
+ read by the second instruction it is because the programmer intended
+ this to happen, (after all they have explicitly requested that these
+ two instructions be executed in parallel). Although if the global
+ variable warn_explicit_parallel_conflicts is true then we do generate
+ a warning message. Similarly we assume that parallel branch and jump
+ instructions are deliberate and should not produce errors. */
+
+ if (warn_explicit_parallel_conflicts)
+ {
+ if (first_writes_to_seconds_operands (& first, & second, false))
+ as_warn ("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?", str2);
+
+ if (first_writes_to_seconds_operands (& second, & first, false))
+ as_warn ("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?", str2);
+ }
+
+ if ((errmsg = (char *) can_make_parallel (& first, & second)) == NULL)
+ {
+ /* Get the fixups for the first instruction. */
+ cgen_swap_fixups ();
+
+ /* Write it out. */
+ (void) cgen_asm_finish_insn (first.insn, first.buffer,
+ CGEN_FIELDS_BITSIZE (& first.fields));
+
+ /* Force the top bit of the second insn to be set. */
+ make_parallel (second.buffer);
+
+ /* Get its fixups. */
+ cgen_restore_fixups ();
+
+ /* Write it out. */
+ (void) cgen_asm_finish_insn (second.insn, second.buffer,
+ CGEN_FIELDS_BITSIZE (& second.fields));
+ }
+ /* Try swapping the instructions to see if they work that way. */
+ else if (can_make_parallel (& second, & first) == NULL)
+ {
+ /* Write out the second instruction first. */
+ (void) cgen_asm_finish_insn (second.insn, second.buffer,
+ CGEN_FIELDS_BITSIZE (& second.fields));
+
+ /* Force the top bit of the first instruction to be set. */
+ make_parallel (first.buffer);
+
+ /* Get the fixups for the first instruction. */
+ cgen_restore_fixups ();
+
+ /* Write out the first instruction. */
+ (void) cgen_asm_finish_insn (first.insn, first.buffer,
+ CGEN_FIELDS_BITSIZE (& first.fields));
+ }
+ else
+ {
+ as_bad ("'%s': %s", str2, errmsg);
+ return;
+ }
+
+ /* Set these so m32r_fill_insn can use them. */
+ prev_seg = now_seg;
+ prev_subseg = now_subseg;
+
+ return;
+}
+
+#endif /* HAVE_CPU_M32RX */
+
+/* end-sanitize-m32rx */
+
+
+void
+md_assemble (str)
+ char * str;
+{
+ m32r_insn insn;
+ char * errmsg;
+ char * str2 = NULL;
/* Initialize GAS's cgen interface for a new instruction. */
cgen_asm_init_parse ();
- insn = CGEN_SYM (assemble_insn) (str, &fields, buffer, &errmsg);
- if (!insn)
+/* start-sanitize-m32rx */
+#ifdef HAVE_CPU_M32RX
+ /* Look for a parallel instruction seperator. */
+ if ((str2 = strstr (str, "||")) != NULL)
+ {
+ assemble_parallel_insn (str, str2);
+ return;
+ }
+#endif
+/* end-sanitize-m32rx */
+
+ insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg);
+ if (!insn.insn)
{
as_bad (errmsg);
return;
}
- if (CGEN_INSN_BITSIZE (insn) == 32)
+/* start-sanitize-m32rx */
+#ifdef HAVE_CPU_M32RX
+ if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
+ {
+ as_bad ("instruction '%s' is for the M32RX only", str);
+ return;
+ }
+#endif
+/* end-sanitize-m32rx */
+
+ if (CGEN_INSN_BITSIZE (insn.insn) == 32)
{
/* 32 bit insns must live on 32 bit boundaries. */
- /* FIXME: If calling fill_insn too many times turns us into a memory
- pig, can we call assemble_nop instead of !seen_relaxable_p? */
- if (prev_insn || seen_relaxable_p)
- fill_insn (0);
- cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (&fields));
+ if (prev_insn.insn || seen_relaxable_p)
+ {
+ /* FIXME: If calling fill_insn too many times turns us into a memory
+ pig, can we call assemble_nop instead of !seen_relaxable_p? */
+ fill_insn (0);
+ }
+
+ (void) cgen_asm_finish_insn (insn.insn, insn.buffer,
+ CGEN_FIELDS_BITSIZE (& insn.fields));
}
else
{
+/* start-sanitize-m32rx */
+/* start-sanitize-phase2-m32rx */
+ int swap = false;
+/* end-sanitize-phase2-m32rx */
+/* end-sanitize-m32rx */
+
+ if (CGEN_INSN_BITSIZE (insn.insn) != 16)
+ abort();
+
+ /* Get the indicies of the operands of the instruction. */
+ insn.insn = m32r_cgen_get_insn_operands (insn.insn,
+ bfd_getb16 ((char *) insn.buffer),
+ 16,
+ insn.indices);
+ if (insn.insn == NULL)
+ as_fatal ("internal error: m32r_cgen_get_insn_operands failed");
+
/* Keep track of whether we've seen a pair of 16 bit insns.
- PREV_INSN is NULL when we're on a 32 bit boundary. */
- if (prev_insn)
- prev_insn = NULL;
+ prev_insn.insn is NULL when we're on a 32 bit boundary. */
+ if (prev_insn.insn)
+ {
+/* start-sanitize-m32rx */
+/* start-sanitize-phase2-m32rx */
+#ifdef HAVE_CPU_M32RX
+ /* Look to see if this instruction can be combined with the
+ previous instruction to make one, parallel, 32 bit instruction.
+ If the previous instruction (potentially) changed the flow of
+ program control, then it cannot be combined with the current
+ instruction. Also if the output of the previous instruction
+ is used as an input to the current instruction then it cannot
+ be combined. Otherwise call can_make_parallel() with both
+ orderings of the instructions to see if they can be combined. */
+ if (! writes_to_pc (& prev_insn)
+ && ! first_writes_to_seconds_operands (& prev_insn, &insn, false)
+ )
+ {
+ if (can_make_parallel (& prev_insn, & insn) == NULL)
+ make_parallel (insn.buffer);
+ else if (can_make_parallel (& insn, & prev_insn.insn) == NULL)
+ swap = true;
+ }
+#endif
+/* end-sanitize-phase2-m32rx */
+/* end-sanitize-m32rx */
+
+ prev_insn.insn = NULL;
+ }
else
- prev_insn = insn;
- cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (&fields));
+ {
+ prev_insn = insn;
+ }
+
+ /* Record the frag that might be used by this insn. */
+ insn.frag = frag_now;
+ insn.addr = cgen_asm_finish_insn (insn.insn, insn.buffer,
+ CGEN_FIELDS_BITSIZE (& insn.fields));
+
+/* start-sanitize-m32rx */
+/* start-sanitize-phase2-m32rx */
+#ifdef HAVE_CPU_M32RX
+ if (swap)
+ {
+ int tmp;
+
+#define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
+
+ /* Swap the two insns */
+ SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
+ SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
+
+ make_parallel (insn.addr);
+ /* Swap any relaxable frags recorded for the two insns. */
+ if (prev_insn.frag->fr_opcode == prev_insn.addr)
+ {
+ prev_insn.frag->fr_opcode = insn.addr;
+ }
+ else if (insn.frag->fr_opcode == insn.addr)
+ {
+ insn.frag->fr_opcode = prev_insn.addr;
+ }
+ }
+/* end-sanitize-phase2-m32rx */
+
+ /* Record where this instruction was assembled. */
+ prev_insn.addr = insn.addr;
+ prev_insn.frag = insn.frag;
+#endif
+/* end-sanitize-m32rx */
+
/* If the insn needs the following one to be on a 32 bit boundary
(e.g. subroutine calls), fill this insn's slot. */
- if (prev_insn
- && CGEN_INSN_ATTR (insn, CGEN_INSN_FILL_SLOT) != 0)
+ if (prev_insn.insn
+ && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_FILL_SLOT) != 0)
fill_insn (0);
- }
- /* If this is a relaxable insn (can be replaced with a larger version)
- mark the fact so that we can emit an alignment directive for a following
- 32 bit insn if we see one. */
- if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAXABLE) != 0)
- seen_relaxable_p = 1;
+ /* If this is a relaxable insn (can be replaced with a larger version)
+ mark the fact so that we can emit an alignment directive for a
+ following 32 bit insn if we see one. */
+ if (CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) != 0)
+ seen_relaxable_p = 1;
+ }
/* Set these so m32r_fill_insn can use them. */
- prev_seg = now_seg;
+ prev_seg = now_seg;
prev_subseg = now_subseg;
}
void
md_operand (expressionP)
- expressionS *expressionP;
+ expressionS * expressionP;
{
- if (*input_line_pointer == '#')
+ if (* input_line_pointer == '#')
{
- input_line_pointer++;
+ input_line_pointer ++;
expression (expressionP);
}
}
valueT
md_section_align (segment, size)
- segT segment;
+ segT segment;
valueT size;
{
int align = bfd_get_section_alignment (stdoutput, segment);
symbolS *
md_undefined_symbol (name)
- char *name;
+ char * name;
{
return 0;
}
m32r_scomm (ignore)
int ignore;
{
- register char *name;
- register char c;
- register char *p;
- offsetT size;
- register symbolS *symbolP;
- offsetT align;
- int align2;
+ register char * name;
+ register char c;
+ register char * p;
+ offsetT size;
+ register symbolS * symbolP;
+ offsetT align;
+ int align2;
name = input_line_pointer;
c = get_symbol_end ();
/* just after name is now '\0' */
p = input_line_pointer;
- *p = c;
+ * p = c;
SKIP_WHITESPACE ();
- if (*input_line_pointer != ',')
+ if (* input_line_pointer != ',')
{
as_bad ("Expected comma after symbol-name: rest of line ignored.");
ignore_rest_of_line ();
return;
}
- input_line_pointer++; /* skip ',' */
+ input_line_pointer ++; /* skip ',' */
if ((size = get_absolute_expression ()) < 0)
{
as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size);
}
/* The third argument to .scomm is the alignment. */
- if (*input_line_pointer != ',')
+ if (* input_line_pointer != ',')
align = 8;
else
{
- ++input_line_pointer;
+ ++ input_line_pointer;
align = get_absolute_expression ();
if (align <= 0)
{
/* Convert to a power of 2 alignment. */
if (align)
{
- for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2)
+ for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
continue;
if (align != 1)
{
else
align2 = 0;
- *p = 0;
+ * p = 0;
symbolP = symbol_find_or_make (name);
- *p = c;
+ * p = c;
if (S_IS_DEFINED (symbolP))
{
if (symbolP->local)
{
- segT old_sec = now_seg;
- int old_subsec = now_subseg;
- char *pfrag;
+ segT old_sec = now_seg;
+ int old_subsec = now_subseg;
+ char * pfrag;
record_alignment (sbss_section, align2);
subseg_set (sbss_section, 0);
+
if (align2)
frag_align (align2, 0, 0);
+
if (S_GET_SEGMENT (symbolP) == sbss_section)
symbolP->sy_frag->fr_symbol = 0;
+
symbolP->sy_frag = frag_now;
+
pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
(char *) 0);
- *pfrag = 0;
+ * pfrag = 0;
S_SET_SIZE (symbolP, size);
S_SET_SEGMENT (symbolP, sbss_section);
S_CLEAR_EXTERNAL (symbolP);
S_SET_VALUE (symbolP, (valueT) size);
S_SET_ALIGN (symbolP, align2);
S_SET_EXTERNAL (symbolP);
- S_SET_SEGMENT (symbolP, &scom_section);
+ S_SET_SEGMENT (symbolP, & scom_section);
}
demand_empty_rest_of_line ();
long
m32r_relax_frag (fragP, stretch)
- fragS *fragP;
- long stretch;
+ fragS * fragP;
+ long stretch;
{
/* Address of branch insn. */
long address = fragP->fr_address + fragP->fr_fix - 2;
int
md_estimate_size_before_relax (fragP, segment)
- fragS *fragP;
- segT segment;
+ fragS * fragP;
+ segT segment;
{
- int old_fr_fix = fragP->fr_fix;
- char *opcode = fragP->fr_opcode;
+ int old_fr_fix = fragP->fr_fix;
+ char * opcode = fragP->fr_opcode;
/* The only thing we have to handle here are symbols outside of the
current segment. They may be undefined or in a different segment in
frag_wane (fragP);
#else
{
- const CGEN_INSN *insn;
- int i;
+ const CGEN_INSN * insn;
+ int i;
/* Update the recorded insn.
Fortunately we don't have to look very far.
}
if (i == 4)
abort ();
+
fragP->fr_cgen.insn = insn;
return 2;
}
void
md_convert_frag (abfd, sec, fragP)
- bfd *abfd;
- segT sec;
- fragS *fragP;
+ bfd * abfd;
+ segT sec;
+ fragS * fragP;
{
- char *opcode, *displacement;
- int target_address, opcode_address, extension, addend;
+ char * opcode;
+ char * displacement;
+ int target_address;
+ int opcode_address;
+ int extension;
+ int addend;
opcode = fragP->fr_opcode;
{
case 1 :
extension = 0;
- displacement = &opcode[1];
+ displacement = & opcode[1];
break;
case 2 :
opcode[0] |= 0x80;
extension = 2;
- displacement = &opcode[1];
+ displacement = & opcode[1];
break;
case 3 :
opcode[2] = opcode[0] | 0x80;
md_number_to_chars (opcode, PAR_NOP_INSN, 2);
opcode_address += 2;
extension = 4;
- displacement = &opcode[3];
+ displacement = & opcode[3];
break;
default :
abort ();
long
md_pcrel_from_section (fixP, sec)
- fixS *fixP;
- segT sec;
+ fixS * fixP;
+ segT sec;
{
if (fixP->fx_addsy != (symbolS *) NULL
&& (! S_IS_DEFINED (fixP->fx_addsy)
bfd_reloc_code_real_type
CGEN_SYM (lookup_reloc) (insn, operand, fixP)
- const CGEN_INSN *insn;
- const CGEN_OPERAND *operand;
- fixS *fixP;
+ const CGEN_INSN * insn;
+ const CGEN_OPERAND * operand;
+ fixS * fixP;
{
switch (CGEN_OPERAND_TYPE (operand))
{
return BFD_RELOC_NONE;
}
+/* Record a HI16 reloc for later matching with its LO16 cousin. */
+
+static void
+m32r_record_hi16 (reloc_type, fixP, seg)
+ int reloc_type;
+ fixS * fixP;
+ segT seg;
+{
+ struct m32r_hi_fixup * hi_fixup;
+
+ assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
+ || reloc_type == BFD_RELOC_M32R_HI16_ULO);
+
+ hi_fixup = ((struct m32r_hi_fixup *)
+ xmalloc (sizeof (struct m32r_hi_fixup)));
+ hi_fixup->fixp = fixP;
+ hi_fixup->seg = now_seg;
+ hi_fixup->next = m32r_hi_fixup_list;
+
+ m32r_hi_fixup_list = hi_fixup;
+}
+
/* Called while parsing an instruction to create a fixup.
We need to check for HI16 relocs and queue them up for later sorting. */
fixS *
m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
- fragS *frag;
- int where;
- const CGEN_INSN *insn;
- int length;
- const CGEN_OPERAND *operand;
- int opinfo;
- expressionS *exp;
+ fragS * frag;
+ int where;
+ const CGEN_INSN * insn;
+ int length;
+ const CGEN_OPERAND * operand;
+ int opinfo;
+ expressionS * exp;
{
- fixS *fixP = cgen_record_fixup_exp (frag, where, insn, length,
- operand, opinfo, exp);
+ fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length,
+ operand, opinfo, exp);
switch (CGEN_OPERAND_TYPE (operand))
{
return fixP;
}
-/* Record a HI16 reloc for later matching with its LO16 cousin. */
-
-static void
-m32r_record_hi16 (reloc_type, fixP, seg)
- int reloc_type;
- fixS *fixP;
- segT seg;
-{
- struct m32r_hi_fixup *hi_fixup;
-
- assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
- || reloc_type == BFD_RELOC_M32R_HI16_ULO);
-
- hi_fixup = ((struct m32r_hi_fixup *)
- xmalloc (sizeof (struct m32r_hi_fixup)));
- hi_fixup->fixp = fixP;
- hi_fixup->seg = now_seg;
- hi_fixup->next = m32r_hi_fixup_list;
- m32r_hi_fixup_list = hi_fixup;
-}
-
/* Return BFD reloc type from opinfo field in a fixS.
It's tricky using fx_r_type in m32r_frob_file because the values
are BFD_RELOC_UNUSED + operand number. */
void
m32r_frob_file ()
{
- struct m32r_hi_fixup *l;
+ struct m32r_hi_fixup * l;
for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
{
- segment_info_type *seginfo;
- int pass;
+ segment_info_type * seginfo;
+ int pass;
assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
|| FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
seginfo = seg_info (l->seg);
for (pass = 0; pass < 2; pass++)
{
- fixS *f, *prev;
+ fixS * f;
+ fixS * prev;
prev = NULL;
for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
|| prev->fx_addsy != f->fx_addsy
|| prev->fx_offset != f->fx_offset))
{
- fixS **pf;
+ fixS ** pf;
/* Move l->fixp before f. */
for (pf = &seginfo->fix_root;
- *pf != l->fixp;
- pf = &(*pf)->fx_next)
- assert (*pf != NULL);
+ * pf != l->fixp;
+ pf = & (* pf)->fx_next)
+ assert (* pf != NULL);
- *pf = l->fixp->fx_next;
+ * pf = l->fixp->fx_next;
l->fixp->fx_next = f;
if (prev == NULL)
int
m32r_force_relocation (fix)
- fixS *fix;
+ fixS * fix;
{
if (! m32r_relax)
return 0;
void
md_number_to_chars (buf, val, n)
- char *buf;
+ char * buf;
valueT val;
- int n;
+ int n;
{
if (target_big_endian)
number_to_chars_bigendian (buf, val, n);
char *litP;
int *sizeP;
{
- int i,prec;
- LITTLENUM_TYPE words[MAX_LITTLENUMS];
- LITTLENUM_TYPE *wordP;
- char *t;
- char *atof_ieee ();
+ int i;
+ int prec;
+ LITTLENUM_TYPE words [MAX_LITTLENUMS];
+ LITTLENUM_TYPE * wordP;
+ char * t;
+ char * atof_ieee ();
switch (type)
{
/* FIXME: Some targets allow other format chars for bigger sizes here. */
default:
- *sizeP = 0;
+ * sizeP = 0;
return "Bad call to md_atof()";
}
t = atof_ieee (input_line_pointer, type, words);
if (t)
input_line_pointer = t;
- *sizeP = prec * sizeof (LITTLENUM_TYPE);
+ * sizeP = prec * sizeof (LITTLENUM_TYPE);
if (target_big_endian)
{
for (i = 0; i < prec; i++)
{
- md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
+ md_number_to_chars (litP, (valueT) words[i],
+ sizeof (LITTLENUM_TYPE));
litP += sizeof (LITTLENUM_TYPE);
}
}
{
for (i = prec - 1; i >= 0; i--)
{
- md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
+ md_number_to_chars (litP, (valueT) words[i],
+ sizeof (LITTLENUM_TYPE));
litP += sizeof (LITTLENUM_TYPE);
}
}
projects / deliverable / binutils-gdb.git / blobdiff