/* tc-m68k.c -- Assemble for the m68k family
- Copyright (C) 1987, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
+ Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
+ 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
-#include <ctype.h>
#include "as.h"
+#include "safe-ctype.h"
#include "obstack.h"
#include "subsegs.h"
+#include "dwarf2dbg.h"
+#include "dw2gencfi.h"
#include "opcode/m68k.h"
#include "m68k-parse.h"
-/* This array holds the chars that always start a comment. If the
- pre-processor is disabled, these aren't very useful */
-#if defined (OBJ_ELF) || defined (TE_DELTA)
-const char comment_chars[] = "|#";
+#if defined (OBJ_ELF)
+#include "elf/m68k.h"
+#endif
+
+#ifdef M68KCOFF
+#include "obj-coff.h"
+#endif
+
+/* This string holds the chars that always start a comment. If the
+ pre-processor is disabled, these aren't very useful. The macro
+ tc_comment_chars points to this. We use this, rather than the
+ usual comment_chars, so that the --bitwise-or option will work. */
+#if defined (TE_SVR4) || defined (TE_DELTA)
+const char *m68k_comment_chars = "|#";
#else
-const char comment_chars[] = "|";
+const char *m68k_comment_chars = "|";
#endif
/* This array holds the chars that only start a comment at the beginning of
.line and .file directives will appear in the pre-processed output */
/* Note that input_file.c hand checks for '#' at the beginning of the
first line of the input file. This is because the compiler outputs
- #NO_APP at the beginning of its output. */
-/* Also note that comments like this one will always work. */
-const char line_comment_chars[] = "#";
+ #NO_APP at the beginning of its output. */
+/* Also note that comments like this one will always work. */
+const char line_comment_chars[] = "#*";
-const char line_separator_chars[] = "";
+const char line_separator_chars[] = ";";
-/* Chars that can be used to separate mant from exp in floating point nums */
-CONST char EXP_CHARS[] = "eE";
+/* Chars that can be used to separate mant from exp in floating point nums. */
+const char EXP_CHARS[] = "eE";
/* Chars that mean this number is a floating point constant, as
in "0f12.456" or "0d1.2345e12". */
-CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
+const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
changed in read.c . Ideally it shouldn't have to know about it at all,
but nothing is ideal around here. */
-const int md_reloc_size = 8; /* Size of relocation record */
+const int md_reloc_size = 8; /* Size of relocation record. */
/* Are we trying to generate PIC code? If so, absolute references
ought to be made into linkage table references or pc-relative
- references. Not implemented. For ELF there are other means
+ references. Not implemented. For ELF there are other means
to denote pic relocations. */
int flag_want_pic;
-static int flag_short_refs; /* -l option */
-static int flag_long_jumps; /* -S option */
+static int flag_short_refs; /* -l option. */
+static int flag_long_jumps; /* -S option. */
+static int flag_keep_pcrel; /* --pcrel option. */
#ifdef REGISTER_PREFIX_OPTIONAL
int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
be 32 bits. */
static int m68k_rel32 = 1;
-/* Its an arbitrary name: This means I don't approve of it */
-/* See flames below */
-static struct obstack robyn;
+/* This is non-zero if m68k_rel32 was set from the command line. */
+static int m68k_rel32_from_cmdline;
-#define TAB(x,y) (((x)<<2)+(y))
-#define TABTYPE(xy) ((xy) >> 2)
-#define BYTE 0
-#define SHORT 1
-#define LONG 2
-#define SZ_UNDEF 3
-#undef BRANCH
-/* Case `g' except when BCC68000 is applicable. */
-#define ABRANCH 1
-/* Coprocessor branches. */
-#define FBRANCH 2
-/* Mode 7.2 -- program counter indirect with (16-bit) displacement,
- supported on all cpus. Widens to 32-bit absolute. */
-#define PCREL 3
-/* For inserting an extra jmp instruction with long offset on 68000,
- for expanding conditional branches. (Not bsr or bra.) Since the
- 68000 doesn't support 32-bit displacements for conditional
- branches, we fake it by reversing the condition and branching
- around a jmp with an absolute long operand. */
-#define BCC68000 4
-/* For the DBcc "instructions". If the displacement requires 32 bits,
- the branch-around-a-jump game is played here too. */
-#define DBCC 5
-/* Not currently used? */
-#define PCLEA 6
-/* Mode AINDX (apc-relative) using PC, with variable target, might fit
- in 16 or 8 bits. */
-#define PCINDEX 7
+/* The default width to use for an index register when using a base
+ displacement. */
+static enum m68k_size m68k_index_width_default = SIZE_LONG;
+
+/* We want to warn if any text labels are misaligned. In order to get
+ the right line number, we need to record the line number for each
+ label. */
+struct label_line
+{
+ struct label_line *next;
+ symbolS *label;
+ char *file;
+ unsigned int line;
+ int text;
+};
+
+/* The list of labels. */
+
+static struct label_line *labels;
+
+/* The current label. */
+
+static struct label_line *current_label;
+
+/* Pointer to list holding the opcodes sorted by name. */
+static struct m68k_opcode const ** m68k_sorted_opcodes;
+
+/* Its an arbitrary name: This means I don't approve of it.
+ See flames below. */
+static struct obstack robyn;
struct m68k_incant
{
USP, VBR, URP, SRP, PCR,
0
};
+static const enum m68k_register mcf_control_regs[] = {
+ CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
+ RAMBAR0, RAMBAR1, MBAR,
+ 0
+};
+static const enum m68k_register mcf5249_control_regs[] = {
+ CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR1, MBAR, MBAR2,
+ 0
+};
+static const enum m68k_register mcf528x_control_regs[] = {
+ CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR,
+ 0
+};
+static const enum m68k_register mcfv4e_control_regs[] = {
+ CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
+ ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
+ PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
+ PCR3U0, PCR3L0, PCR3U1, PCR3L1,
+ 0
+};
#define cpu32_control_regs m68010_control_regs
static const enum m68k_register *control_regs;
-/* internal form of a 68020 instruction */
+/* Internal form of a 68020 instruction. */
struct m68k_it
{
const char *error;
- const char *args; /* list of opcode info */
+ const char *args; /* List of opcode info. */
int numargs;
- int numo; /* Number of shorts in opcode */
+ int numo; /* Number of shorts in opcode. */
short opcode[11];
struct m68k_op operands[6];
- int nexp; /* number of exprs in use */
+ int nexp; /* Number of exprs in use. */
struct m68k_exp exprs[4];
- int nfrag; /* Number of frags we have to produce */
+ int nfrag; /* Number of frags we have to produce. */
struct
{
- int fragoff; /* Where in the current opcode the frag ends */
+ int fragoff; /* Where in the current opcode the frag ends. */
symbolS *fadd;
- long foff;
+ offsetT foff;
int fragty;
}
fragb[4];
- int nrel; /* Num of reloc strucs in use */
+ int nrel; /* Num of reloc strucs in use. */
struct
{
int n;
enum pic_relocation pic_reloc;
#endif
}
- reloc[5]; /* Five is enough??? */
+ reloc[5]; /* Five is enough??? */
};
-#define cpu_of_arch(x) ((x) & m68000up)
+#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
#define float_of_arch(x) ((x) & mfloat)
#define mmu_of_arch(x) ((x) & mmmu)
+#define arch_coldfire_p(x) ((x) & mcfisa_a)
+#define arch_coldfire_fpu(x) ((x) & cfloat)
-static struct m68k_it the_ins; /* the instruction being assembled */
+/* Macros for determining if cpu supports a specific addressing mode. */
+#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
+
+static struct m68k_it the_ins; /* The instruction being assembled. */
#define op(ex) ((ex)->exp.X_op)
#define adds(ex) ((ex)->exp.X_add_symbol)
#define subs(ex) ((ex)->exp.X_op_symbol)
#define offs(ex) ((ex)->exp.X_add_number)
-/* Macros for adding things to the m68k_it struct */
+/* Macros for adding things to the m68k_it struct. */
+#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
-#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
+/* Like addword, but goes BEFORE general operands. */
-/* Like addword, but goes BEFORE general operands */
static void
-insop (w, opcode)
- int w;
- struct m68k_incant *opcode;
+insop (int w, const struct m68k_incant *opcode)
{
int z;
- for(z=the_ins.numo;z>opcode->m_codenum;--z)
- the_ins.opcode[z]=the_ins.opcode[z-1];
- for(z=0;z<the_ins.nrel;z++)
- the_ins.reloc[z].n+=2;
+ for (z = the_ins.numo; z > opcode->m_codenum; --z)
+ the_ins.opcode[z] = the_ins.opcode[z - 1];
+ for (z = 0; z < the_ins.nrel; z++)
+ the_ins.reloc[z].n += 2;
for (z = 0; z < the_ins.nfrag; z++)
the_ins.fragb[z].fragoff++;
- the_ins.opcode[opcode->m_codenum]=w;
+ the_ins.opcode[opcode->m_codenum] = w;
the_ins.numo++;
}
/* The numo+1 kludge is so we can hit the low order byte of the prev word.
Blecch. */
static void
-add_fix (width, exp, pc_rel, pc_fix)
- char width;
- struct m68k_exp *exp;
- int pc_rel;
- int pc_fix;
+add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
{
- the_ins.reloc[the_ins.nrel].n = (((width)=='B')
- ? (the_ins.numo*2-1)
- : (((width)=='b')
- ? (the_ins.numo*2+1)
- : (the_ins.numo*2)));
+ the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
+ ? the_ins.numo * 2 - 1
+ : (width == 'b'
+ ? the_ins.numo * 2 + 1
+ : the_ins.numo * 2));
the_ins.reloc[the_ins.nrel].exp = exp->exp;
the_ins.reloc[the_ins.nrel].wid = width;
the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
static void
-add_frag(add,off,type)
- symbolS *add;
- long off;
- int type;
+add_frag (symbolS *add, offsetT off, int type)
{
- the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
- the_ins.fragb[the_ins.nfrag].fadd=add;
- the_ins.fragb[the_ins.nfrag].foff=off;
- the_ins.fragb[the_ins.nfrag++].fragty=type;
+ the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
+ the_ins.fragb[the_ins.nfrag].fadd = add;
+ the_ins.fragb[the_ins.nfrag].foff = off;
+ the_ins.fragb[the_ins.nfrag++].fragty = type;
}
#define isvar(ex) \
(op (ex) != O_constant && op (ex) != O_big)
-static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
-static int get_num PARAMS ((struct m68k_exp *exp, int ok));
-static int reverse_16_bits PARAMS ((int in));
-static int reverse_8_bits PARAMS ((int in));
-static void install_gen_operand PARAMS ((int mode, int val));
-static void install_operand PARAMS ((int mode, int val));
-static void s_bss PARAMS ((int));
-static void s_data1 PARAMS ((int));
-static void s_data2 PARAMS ((int));
-static void s_even PARAMS ((int));
-static void s_proc PARAMS ((int));
-static void mri_chip PARAMS ((void));
-static void s_chip PARAMS ((int));
-static void s_fopt PARAMS ((int));
-static void s_opt PARAMS ((int));
-static void s_reg PARAMS ((int));
-static void s_restore PARAMS ((int));
-static void s_save PARAMS ((int));
-static void s_mri_if PARAMS ((int));
-static void s_mri_else PARAMS ((int));
-static void s_mri_endi PARAMS ((int));
-static void s_mri_break PARAMS ((int));
-static void s_mri_next PARAMS ((int));
-static void s_mri_for PARAMS ((int));
-static void s_mri_endf PARAMS ((int));
-static void s_mri_repeat PARAMS ((int));
-static void s_mri_until PARAMS ((int));
-static void s_mri_while PARAMS ((int));
-static void s_mri_endw PARAMS ((int));
+static char *crack_operand (char *str, struct m68k_op *opP);
+static int get_num (struct m68k_exp *exp, int ok);
+static int reverse_16_bits (int in);
+static int reverse_8_bits (int in);
+static void install_gen_operand (int mode, int val);
+static void install_operand (int mode, int val);
+static void s_bss (int);
+static void s_data1 (int);
+static void s_data2 (int);
+static void s_even (int);
+static void s_proc (int);
+static void s_chip (int);
+static void s_fopt (int);
+static void s_opt (int);
+static void s_reg (int);
+static void s_restore (int);
+static void s_save (int);
+static void s_mri_if (int);
+static void s_mri_else (int);
+static void s_mri_endi (int);
+static void s_mri_break (int);
+static void s_mri_next (int);
+static void s_mri_for (int);
+static void s_mri_endf (int);
+static void s_mri_repeat (int);
+static void s_mri_until (int);
+static void s_mri_while (int);
+static void s_mri_endw (int);
static int current_architecture;
+static int current_chip;
-struct m68k_cpu {
- unsigned long arch;
- const char *name;
- int alias;
-};
+struct m68k_cpu
+ {
+ unsigned long arch;
+ unsigned long chip;
+ const char *name;
+ int alias;
+ };
-static const struct m68k_cpu archs[] = {
- { m68000, "68000", 0 },
- { m68010, "68010", 0 },
- { m68020, "68020", 0 },
- { m68030, "68030", 0 },
- { m68040, "68040", 0 },
- { m68060, "68060", 0 },
- { cpu32, "cpu32", 0 },
- { m68881, "68881", 0 },
- { m68851, "68851", 0 },
- /* Aliases (effectively, so far as gas is concerned) for the above
- cpus. */
- { m68020, "68k", 1 },
- { m68000, "68302", 1 },
- { m68000, "68008", 1 },
- { m68000, "68ec000", 1 },
- { m68000, "68hc000", 1 },
- { m68000, "68hc001", 1 },
- { m68020, "68ec020", 1 },
- { m68030, "68ec030", 1 },
- { m68040, "68ec040", 1 },
- { cpu32, "68330", 1 },
- { cpu32, "68331", 1 },
- { cpu32, "68332", 1 },
- { cpu32, "68333", 1 },
- { cpu32, "68340", 1 },
- { cpu32, "68360", 1 },
- { m68881, "68882", 1 },
-};
+static const struct m68k_cpu archs[] =
+ {
+ { m68000, m68000, "68000", 0 },
+ { m68010, m68010, "68010", 0 },
+ { m68020, m68020, "68020", 0 },
+ { m68030, m68030, "68030", 0 },
+ { m68040, m68040, "68040", 0 },
+ { m68060, m68060, "68060", 0 },
+ { cpu32, cpu32, "cpu32", 0 },
+ { m68881, m68881, "68881", 0 },
+ { m68851, m68851, "68851", 0 },
+ { mcfisa_a, mcf5200, "5200", 0 },
+ { mcfisa_a|mcfhwdiv|mcfmac, mcf5206e, "5206e", 0 },
+ { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf521x, "521x", 0 },
+ { mcfisa_a|mcfhwdiv|mcfemac, mcf5249, "5249", 0 },
+ { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf528x, "528x", 0 },
+ { mcfisa_a|mcfhwdiv|mcfmac, mcf5307, "5307", 0 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "5407", 0 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "547x", 0 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5480, "548x", 0 },
+ /* Aliases (effectively, so far as gas is concerned) for the above
+ cpus. */
+ { m68020, m68020, "68k", 1 },
+ { m68000, m68000, "68008", 1 },
+ { m68000, m68000, "68302", 1 },
+ { m68000, m68000, "68306", 1 },
+ { m68000, m68000, "68307", 1 },
+ { m68000, m68000, "68322", 1 },
+ { m68000, m68000, "68356", 1 },
+ { m68000, m68000, "68ec000", 1 },
+ { m68000, m68000, "68hc000", 1 },
+ { m68000, m68000, "68hc001", 1 },
+ { m68020, m68020, "68ec020", 1 },
+ { m68030, m68030, "68ec030", 1 },
+ { m68040, m68040, "68ec040", 1 },
+ { m68060, m68060, "68ec060", 1 },
+ { cpu32, cpu32, "68330", 1 },
+ { cpu32, cpu32, "68331", 1 },
+ { cpu32, cpu32, "68332", 1 },
+ { cpu32, cpu32, "68333", 1 },
+ { cpu32, cpu32, "68334", 1 },
+ { cpu32, cpu32, "68336", 1 },
+ { cpu32, cpu32, "68340", 1 },
+ { cpu32, cpu32, "68341", 1 },
+ { cpu32, cpu32, "68349", 1 },
+ { cpu32, cpu32, "68360", 1 },
+ { m68881, m68881, "68882", 1 },
+ { mcfisa_a, mcf5200, "5202", 1 },
+ { mcfisa_a, mcf5200, "5204", 1 },
+ { mcfisa_a, mcf5200, "5206", 1 },
+ { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5214", 1 },
+ { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5216", 1 },
+ { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5280", 1 },
+ { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5281", 1 },
+ { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5282", 1 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "cfv4", 1 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5470", 1 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5471", 1 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5472", 1 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5473", 1 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5474", 1 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5475", 1 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5480", 1 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5481", 1 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5482", 1 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5483", 1 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5484", 1 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5485", 1 },
+ { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "cfv4e", 1 },
+ };
static const int n_archs = sizeof (archs) / sizeof (archs[0]);
-/* BCC68000 is for patching in an extra jmp instruction for long offsets
- on the 68000. The 68000 doesn't support long branches with branchs */
+/* This is the assembler relaxation table for m68k. m68k is a rich CISC
+ architecture and we have a lot of relaxation modes. */
+
+/* Macros used in the relaxation code. */
+#define TAB(x,y) (((x) << 2) + (y))
+#define TABTYPE(x) ((x) >> 2)
+
+/* Relaxation states. */
+#define BYTE 0
+#define SHORT 1
+#define LONG 2
+#define SZ_UNDEF 3
-/* This table desribes how you change sizes for the various types of variable
- size expressions. This version only supports two kinds. */
+/* Here are all the relaxation modes we support. First we can relax ordinary
+ branches. On 68020 and higher and on CPU32 all branch instructions take
+ three forms, so on these CPUs all branches always remain as such. When we
+ have to expand to the LONG form on a 68000, though, we substitute an
+ absolute jump instead. This is a direct replacement for unconditional
+ branches and a branch over a jump for conditional branches. However, if the
+ user requires PIC and disables this with --pcrel, we can only relax between
+ BYTE and SHORT forms, punting if that isn't enough. This gives us four
+ different relaxation modes for branches: */
+
+#define BRANCHBWL 0 /* Branch byte, word, or long. */
+#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
+#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
+#define BRANCHBW 3 /* Branch byte or word. */
+
+/* We also relax coprocessor branches and DBcc's. All CPUs that support
+ coprocessor branches support them in word and long forms, so we have only
+ one relaxation mode for them. DBcc's are word only on all CPUs. We can
+ relax them to the LONG form with a branch-around sequence. This sequence
+ can use a long branch (if available) or an absolute jump (if acceptable).
+ This gives us two relaxation modes. If long branches are not available and
+ absolute jumps are not acceptable, we don't relax DBcc's. */
+
+#define FBRANCH 4 /* Coprocessor branch. */
+#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
+#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
+
+/* That's all for instruction relaxation. However, we also relax PC-relative
+ operands. Specifically, we have three operand relaxation modes. On the
+ 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
+ on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
+ two. Also PC+displacement+index operands in their simple form (with a non-
+ suppressed index without memory indirection) are supported on all CPUs, but
+ on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
+ and on CPU32 we relax it to SHORT and LONG forms as well using the extended
+ form of the PC+displacement+index operand. Finally, some absolute operands
+ can be relaxed down to 16-bit PC-relative. */
+
+#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
+#define PCINDEX 8 /* PC + displacement + index. */
+#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
/* Note that calls to frag_var need to specify the maximum expansion
needed; this is currently 10 bytes for DBCC. */
How far Backward this mode will reach:
How many bytes this mode will add to the size of the frag
Which mode to go to if the offset won't fit in this one
- */
+
+ Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
relax_typeS md_relax_table[] =
{
- {1, 1, 0, 0}, /* First entries aren't used */
- {1, 1, 0, 0}, /* For no good reason except */
- {1, 1, 0, 0}, /* that the VAX doesn't either */
- {1, 1, 0, 0},
-
- {(127), (-128), 0, TAB (ABRANCH, SHORT)},
- {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
- {0, 0, 4, 0},
- {1, 1, 0, 0},
-
- {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
- {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
- {0, 0, 4, 0},
- {1, 1, 0, 0},
-
- {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
- {(32767), (-32768), 2, TAB (PCREL, LONG)},
- {0, 0, 4, 0},
- {1, 1, 0, 0},
-
- {(127), (-128), 0, TAB (BCC68000, SHORT)},
- {(32767), (-32768), 2, TAB (BCC68000, LONG)},
- {0, 0, 6, 0}, /* jmp long space */
- {1, 1, 0, 0},
-
- {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
- {(32767), (-32768), 2, TAB (DBCC, LONG)},
- {0, 0, 10, 0}, /* bra/jmp long space */
- {1, 1, 0, 0},
-
- {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
- {32767, -32768, 2, TAB (PCLEA, LONG)},
- {0, 0, 6, 0},
- {1, 1, 0, 0},
-
- /* For, e.g., jmp pcrel indexed. */
- {125, -130, 0, TAB (PCINDEX, SHORT)},
- {32765, -32770, 2, TAB (PCINDEX, LONG)},
- {0, 0, 4, 0},
- {1, 1, 0, 0},
+ { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
+ { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
+ { 0, 0, 4, 0 },
+ { 1, 1, 0, 0 },
+
+ { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
+ { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
+ { 0, 0, 4, 0 },
+ { 1, 1, 0, 0 },
+
+ { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
+ { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
+ { 0, 0, 6, 0 },
+ { 1, 1, 0, 0 },
+
+ { 127, -128, 0, TAB (BRANCHBW, SHORT) },
+ { 0, 0, 2, 0 },
+ { 1, 1, 0, 0 },
+ { 1, 1, 0, 0 },
+
+ { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
+ { 32767, -32768, 2, TAB (FBRANCH, LONG) },
+ { 0, 0, 4, 0 },
+ { 1, 1, 0, 0 },
+
+ { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
+ { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
+ { 0, 0, 10, 0 },
+ { 1, 1, 0, 0 },
+
+ { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
+ { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
+ { 0, 0, 10, 0 },
+ { 1, 1, 0, 0 },
+
+ { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
+ { 32767, -32768, 2, TAB (PCREL1632, LONG) },
+ { 0, 0, 6, 0 },
+ { 1, 1, 0, 0 },
+
+ { 125, -130, 0, TAB (PCINDEX, SHORT) },
+ { 32765, -32770, 2, TAB (PCINDEX, LONG) },
+ { 0, 0, 4, 0 },
+ { 1, 1, 0, 0 },
+
+ { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
+ { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
+ { 0, 0, 4, 0 },
+ { 1, 1, 0, 0 },
};
/* These are the machine dependent pseudo-ops. These are included so
the assembler can work on the output from the SUN C compiler, which
- generates these.
- */
+ generates these. */
/* This table describes all the machine specific pseudo-ops the assembler
has to support. The fields are:
pseudo-op name without dot
function to call to execute this pseudo-op
- Integer arg to pass to the function
- */
+ Integer arg to pass to the function. */
const pseudo_typeS md_pseudo_table[] =
{
{"data1", s_data1, 0},
{0, 0, 0}
};
-
/* The mote pseudo ops are put into the opcode table, since they
- don't start with a . they look like opcodes to gas.
- */
-extern void obj_coff_section ();
+ don't start with a . they look like opcodes to gas. */
-CONST pseudo_typeS mote_pseudo_table[] =
+const pseudo_typeS mote_pseudo_table[] =
{
{"dcl", cons, 4},
{0, 0, 0}
};
-#define issbyte(x) ((x)>=-128 && (x)<=127)
-#define isubyte(x) ((x)>=0 && (x)<=255)
-#define issword(x) ((x)>=-32768 && (x)<=32767)
-#define isuword(x) ((x)>=0 && (x)<=65535)
+#define issbyte(x) ((x) >= -128 && (x) <= 127)
+#define isubyte(x) ((x) >= 0 && (x) <= 255)
+#define issword(x) ((x) >= -32768 && (x) <= 32767)
+#define isuword(x) ((x) >= 0 && (x) <= 65535)
-#define isbyte(x) ((x)>= -255 && (x)<=255)
-#define isword(x) ((x)>=-65536 && (x)<=65535)
+#define isbyte(x) ((x) >= -255 && (x) <= 255)
+#define isword(x) ((x) >= -65536 && (x) <= 65535)
#define islong(x) (1)
-extern char *input_line_pointer;
-
-static char mklower_table[256];
-#define mklower(c) (mklower_table[(unsigned char)(c)])
static char notend_table[256];
static char alt_notend_table[256];
#define notend(s) \
|| (*s == ':' \
&& alt_notend_table[(unsigned char) s[1]])))
+/* Return a human readable string holding the list of chips that are
+ valid for a particular architecture, suppressing aliases (unless
+ there is only one of them). */
+
+static char *
+find_cf_chip (int architecture)
+{
+ static char buf[1024];
+ int i, j, n_chips, n_alias;
+ char *cp;
+
+ strcpy (buf, " (");
+ cp = buf + strlen (buf);
+
+ for (i = 0, n_chips = 0, n_alias = 0; i < n_archs; ++i)
+ if (archs[i].arch & architecture)
+ {
+ n_chips++;
+ if (archs[i].alias)
+ n_alias++;
+ }
+
+ if (n_chips == 0)
+ as_fatal (_("no matching ColdFire architectures found"));
+
+ if (n_alias > 1)
+ n_chips -= n_alias;
+
+ for (i = 0, j = 0; i < n_archs && j < n_chips; ++i)
+ if (archs[i].arch & architecture)
+ {
+ if (j)
+ {
+ if ((j == n_chips - 1 && !(n_alias > 1)) || ! n_alias)
+ {
+ if (n_chips == 2)
+ {
+ strncpy (cp, _(" or "), (sizeof (buf) - (cp - buf)));
+ cp += strlen (cp);
+ }
+ else
+ {
+ strncpy (cp, _(", or "), (sizeof (buf) - (cp - buf)));
+ cp += strlen (cp);
+ }
+ }
+ else
+ {
+ strncpy (cp, ", ", (sizeof (buf) - (cp - buf)));
+ cp += strlen (cp);
+ }
+ }
+ strncpy (cp, archs[i].name, (sizeof (buf) - (cp - buf)));
+ cp += strlen (cp);
+ j++;
+ }
+
+ if (n_alias > 1)
+ {
+ strncpy (cp, _(", or aliases"), (sizeof (buf) - (cp - buf)));
+ cp += strlen (cp);
+ }
+
+ strncpy (cp, ")", (sizeof (buf) - (cp - buf)));
+
+ return buf;
+}
+
#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
#ifdef NO_PCREL_RELOCS
int
-make_pcrel_absolute(fixP, add_number)
- fixS *fixP;
- long *add_number;
+make_pcrel_absolute (fixS *fixP, long *add_number)
{
register unsigned char *opcode = fixP->fx_frag->fr_opcode;
- /* rewrite the PC relative instructions to absolute address ones.
- * these are rumoured to be faster, and the apollo linker refuses
- * to deal with the PC relative relocations.
- */
- if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
+ /* Rewrite the PC relative instructions to absolute address ones.
+ these are rumored to be faster, and the apollo linker refuses
+ to deal with the PC relative relocations. */
+ if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP. */
{
+ if (flag_keep_pcrel)
+ as_fatal (_("Tried to convert PC relative branch to absolute jump"));
opcode[0] = 0x4e;
opcode[1] = 0xf9;
}
- else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
+ else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR. */
{
+ if (flag_keep_pcrel)
+ as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
opcode[0] = 0x4e;
opcode[1] = 0xb9;
}
else
- as_fatal ("Unknown PC relative instruction");
+ as_fatal (_("Unknown PC relative instruction"));
*add_number -= 4;
return 0;
}
#endif /* NO_PCREL_RELOCS */
short
-tc_coff_fix2rtype (fixP)
- fixS *fixP;
+tc_coff_fix2rtype (fixS *fixP)
{
if (fixP->fx_tcbit && fixP->fx_size == 4)
return R_RELLONG_NEG;
: fixP->fx_size == 2 ? R_DIR16
: R_DIR32);
#else
- return (fixP->fx_pcrel ?
- (fixP->fx_size == 1 ? R_PCRBYTE :
- fixP->fx_size == 2 ? R_PCRWORD :
- R_PCRLONG) :
- (fixP->fx_size == 1 ? R_RELBYTE :
- fixP->fx_size == 2 ? R_RELWORD :
- R_RELLONG));
+ return (fixP->fx_pcrel
+ ? (fixP->fx_size == 1 ? R_PCRBYTE
+ : fixP->fx_size == 2 ? R_PCRWORD
+ : R_PCRLONG)
+ : (fixP->fx_size == 1 ? R_RELBYTE
+ : fixP->fx_size == 2 ? R_RELWORD
+ : R_RELLONG));
#endif
}
#ifdef OBJ_ELF
+/* Return zero if the reference to SYMBOL from within the same segment may
+ be relaxed. */
+
+/* On an ELF system, we can't relax an externally visible symbol,
+ because it may be overridden by a shared library. However, if
+ TARGET_OS is "elf", then we presume that we are assembling for an
+ embedded system, in which case we don't have to worry about shared
+ libraries, and we can relax any external sym. */
+
+#define relaxable_symbol(symbol) \
+ (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
+ || S_IS_WEAK (symbol)))
+
/* Compute the relocation code for a fixup of SIZE bytes, using pc
relative relocation if PCREL is non-zero. PIC says whether a special
pic relocation was requested. */
-static bfd_reloc_code_real_type get_reloc_code
- PARAMS ((int, int, enum pic_relocation));
-
static bfd_reloc_code_real_type
-get_reloc_code (size, pcrel, pic)
- int size;
- int pcrel;
- enum pic_relocation pic;
+get_reloc_code (int size, int pcrel, enum pic_relocation pic)
{
switch (pic)
{
}
}
- as_bad ("Can not do %d byte %s%srelocation", size,
- pcrel ? "pc-relative " : "",
- pic == pic_none ? "" : "pic ");
+ if (pcrel)
+ {
+ if (pic == pic_none)
+ as_bad (_("Can not do %d byte pc-relative relocation"), size);
+ else
+ as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
+ }
+ else
+ {
+ if (pic == pic_none)
+ as_bad (_("Can not do %d byte relocation"), size);
+ else
+ as_bad (_("Can not do %d byte pic relocation"), size);
+ }
+
return BFD_RELOC_NONE;
}
correctly, so in some cases we force the original symbol to be
used. */
int
-tc_m68k_fix_adjustable (fixP)
- fixS *fixP;
+tc_m68k_fix_adjustable (fixS *fixP)
{
- /* Prevent all adjustments to global symbols. */
- if (S_IS_EXTERNAL (fixP->fx_addsy))
- return 0;
-
- /* adjust_reloc_syms doesn't know about the GOT */
+ /* Adjust_reloc_syms doesn't know about the GOT. */
switch (fixP->fx_r_type)
{
case BFD_RELOC_8_GOT_PCREL:
case BFD_RELOC_32_PLTOFF:
return 0;
+ case BFD_RELOC_VTABLE_INHERIT:
+ case BFD_RELOC_VTABLE_ENTRY:
+ return 0;
+
default:
return 1;
}
#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
+#define relaxable_symbol(symbol) 1
+
#endif /* OBJ_ELF */
#ifdef BFD_ASSEMBLER
arelent *
-tc_gen_reloc (section, fixp)
- asection *section;
- fixS *fixp;
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
{
arelent *reloc;
bfd_reloc_code_real_type code;
+ /* If the tcbit is set, then this was a fixup of a negative value
+ that was never resolved. We do not have a reloc to handle this,
+ so just return. We assume that other code will have detected this
+ situation and produced a helpful error message, so we just tell the
+ user that the reloc cannot be produced. */
if (fixp->fx_tcbit)
- abort ();
+ {
+ if (fixp->fx_addsy)
+ as_bad_where (fixp->fx_file, fixp->fx_line,
+ _("Unable to produce reloc against symbol '%s'"),
+ S_GET_NAME (fixp->fx_addsy));
+ return NULL;
+ }
if (fixp->fx_r_type != BFD_RELOC_NONE)
- code = fixp->fx_r_type;
+ {
+ code = fixp->fx_r_type;
+
+ /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
+ that fixup_segment converted a non-PC relative reloc into a
+ PC relative reloc. In such a case, we need to convert the
+ reloc code. */
+ if (fixp->fx_pcrel)
+ {
+ switch (code)
+ {
+ case BFD_RELOC_8:
+ code = BFD_RELOC_8_PCREL;
+ break;
+ case BFD_RELOC_16:
+ code = BFD_RELOC_16_PCREL;
+ break;
+ case BFD_RELOC_32:
+ code = BFD_RELOC_32_PCREL;
+ break;
+ case BFD_RELOC_8_PCREL:
+ case BFD_RELOC_16_PCREL:
+ case BFD_RELOC_32_PCREL:
+ case BFD_RELOC_8_GOT_PCREL:
+ case BFD_RELOC_16_GOT_PCREL:
+ case BFD_RELOC_32_GOT_PCREL:
+ case BFD_RELOC_8_GOTOFF:
+ case BFD_RELOC_16_GOTOFF:
+ case BFD_RELOC_32_GOTOFF:
+ case BFD_RELOC_8_PLT_PCREL:
+ case BFD_RELOC_16_PLT_PCREL:
+ case BFD_RELOC_32_PLT_PCREL:
+ case BFD_RELOC_8_PLTOFF:
+ case BFD_RELOC_16_PLTOFF:
+ case BFD_RELOC_32_PLTOFF:
+ break;
+ default:
+ as_bad_where (fixp->fx_file, fixp->fx_line,
+ _("Cannot make %s relocation PC relative"),
+ bfd_get_reloc_code_name (code));
+ }
+ }
+ }
else
{
#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
#undef F
#undef MAP
- reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
- assert (reloc != 0);
- reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
+ reloc = (arelent *) xmalloc (sizeof (arelent));
+ reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+ *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
#ifndef OBJ_ELF
if (fixp->fx_pcrel)
#else
if (!fixp->fx_pcrel)
reloc->addend = fixp->fx_addnumber;
- else if ((fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
+ else
reloc->addend = (section->vma
- + (fixp->fx_pcrel_adjust == 64
- ? -1 : fixp->fx_pcrel_adjust)
+ /* Explicit sign extension in case char is
+ unsigned. */
+ + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
+ fixp->fx_addnumber
+ md_pcrel_from (fixp));
- else
- reloc->addend = (fixp->fx_offset
- + (fixp->fx_pcrel_adjust == 64
- ? -1 : fixp->fx_pcrel_adjust));
#endif
reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
\f
/* Assemble an m68k instruction. */
-void
-m68k_ip (instring)
- char *instring;
+static void
+m68k_ip (char *instring)
{
register char *p;
register struct m68k_op *opP;
- register struct m68k_incant *opcode;
+ register const struct m68k_incant *opcode;
register const char *s;
register int tmpreg = 0, baseo = 0, outro = 0, nextword;
char *pdot, *pdotmove;
char c;
int losing;
int opsfound;
- char *crack_operand ();
LITTLENUM_TYPE words[6];
LITTLENUM_TYPE *wordp;
unsigned long ok_arch = 0;
if (*instring == ' ')
- instring++; /* skip leading whitespace */
+ instring++; /* Skip leading whitespace. */
/* Scan up to end of operation-code, which MUST end in end-of-string
- or exactly 1 space. */
+ or exactly 1 space. */
pdot = 0;
for (p = instring; *p != '\0'; p++)
{
if (p == instring)
{
- the_ins.error = "No operator";
+ the_ins.error = _("No operator");
return;
}
c = *p;
*p = '\0';
- opcode = (struct m68k_incant *) hash_find (op_hash, instring);
+ opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
*p = c;
if (pdot != NULL)
if (opcode == NULL)
{
- the_ins.error = "Unknown operator";
+ the_ins.error = _("Unknown operator");
return;
}
- /* found a legitimate opcode, start matching operands */
+ /* Found a legitimate opcode, start matching operands. */
while (*p == ' ')
++p;
char *old = input_line_pointer;
*old = '\n';
input_line_pointer = p;
- /* Ahh - it's a motorola style psuedo op */
+ /* Ahh - it's a motorola style psuedo op. */
mote_pseudo_table[opcode->m_opnum].poc_handler
(mote_pseudo_table[opcode->m_opnum].poc_val);
input_line_pointer = old;
for (n = opsfound; n > 0; --n)
the_ins.operands[n] = the_ins.operands[n - 1];
- memset ((char *) (&the_ins.operands[0]), '\0',
- sizeof (the_ins.operands[0]));
+ memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
the_ins.operands[0].mode = CONTROL;
the_ins.operands[0].reg = m68k_float_copnum;
opsfound++;
}
- /* We've got the operands. Find an opcode that'll accept them */
+ /* We've got the operands. Find an opcode that'll accept them. */
for (losing = 0;;)
{
/* If we didn't get the right number of ops, or we have no
- common model with this pattern then reject this pattern. */
+ common model with this pattern then reject this pattern. */
+ ok_arch |= opcode->m_arch;
if (opsfound != opcode->m_opnum
|| ((opcode->m_arch & current_architecture) == 0))
- {
- ++losing;
- ok_arch |= opcode->m_arch;
- }
+ ++losing;
else
{
for (s = opcode->m_operands, opP = &the_ins.operands[0];
}
break;
- case '`':
+ case '<':
switch (opP->mode)
{
+ case DREG:
+ case AREG:
+ case FPREG:
+ case CONTROL:
case IMMED:
+ case ADEC:
+ case REGLST:
+ losing++;
+ break;
+ default:
+ break;
+ }
+ break;
+
+ case '>':
+ switch (opP->mode)
+ {
case DREG:
case AREG:
case FPREG:
case CONTROL:
+ case IMMED:
case AINC:
case REGLST:
+ losing++;
+ break;
+ case ABSL:
+ break;
+ default:
+ if (opP->reg == PC
+ || opP->reg == ZPC)
+ losing++;
+ break;
+ }
+ break;
+
+ case 'm':
+ switch (opP->mode)
+ {
+ case DREG:
+ case AREG:
+ case AINDR:
+ case AINC:
+ case ADEC:
+ break;
+ default:
+ losing++;
+ }
+ break;
+
+ case 'n':
+ switch (opP->mode)
+ {
+ case DISP:
+ break;
+ default:
+ losing++;
+ }
+ break;
+
+ case 'o':
+ switch (opP->mode)
+ {
+ case BASE:
+ case ABSL:
+ case IMMED:
+ break;
+ default:
+ losing++;
+ }
+ break;
+
+ case 'p':
+ switch (opP->mode)
+ {
+ case DREG:
+ case AREG:
+ case AINDR:
+ case AINC:
+ case ADEC:
+ break;
+ case DISP:
+ if (opP->reg == PC || opP->reg == ZPC)
+ losing++;
+ break;
+ default:
+ losing++;
+ }
+ break;
+
+ case 'q':
+ switch (opP->mode)
+ {
+ case DREG:
case AINDR:
+ case AINC:
+ case ADEC:
+ break;
+ case DISP:
+ if (opP->reg == PC || opP->reg == ZPC)
+ losing++;
+ break;
+ default:
losing++;
break;
+ }
+ break;
+
+ case 'v':
+ switch (opP->mode)
+ {
+ case DREG:
+ case AINDR:
+ case AINC:
+ case ADEC:
+ case ABSL:
+ break;
+ case DISP:
+ if (opP->reg == PC || opP->reg == ZPC)
+ losing++;
+ break;
default:
+ losing++;
break;
}
break;
&& (opP->disp.exp.X_op != O_constant
|| ! isbyte (opP->disp.exp.X_add_number)))
losing++;
+ else if (s[1] == 'B'
+ && ! isvar (&opP->disp)
+ && (opP->disp.exp.X_op != O_constant
+ || ! issbyte (opP->disp.exp.X_add_number)))
+ losing++;
else if (s[1] == 'w'
&& ! isvar (&opP->disp)
&& (opP->disp.exp.X_op != O_constant
++losing;
break;
+ case '4':
+ if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
+ && (opP->mode != DISP
+ || opP->reg < ADDR0
+ || opP->reg > ADDR7))
+ ++losing;
+ break;
+
case 'B': /* FOO */
if (opP->mode != ABSL
|| (flag_long_jumps
losing++;
break;
+ case 'b':
+ switch (opP->mode)
+ {
+ case IMMED:
+ case ABSL:
+ case AREG:
+ case FPREG:
+ case CONTROL:
+ case POST:
+ case PRE:
+ case REGLST:
+ losing++;
+ break;
+ default:
+ break;
+ }
+ break;
+
case 'C':
if (opP->mode != CONTROL || opP->reg != CCR)
losing++;
losing++;
break;
+ case 'E':
+ if (opP->reg != ACC)
+ losing++;
+ break;
+
+ case 'e':
+ if (opP->reg != ACC && opP->reg != ACC1
+ && opP->reg != ACC2 && opP->reg != ACC3)
+ losing++;
+ break;
+
case 'F':
if (opP->mode != FPREG)
losing++;
break;
+ case 'G':
+ if (opP->reg != MACSR)
+ losing++;
+ break;
+
+ case 'g':
+ if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
+ losing++;
+ break;
+
+ case 'H':
+ if (opP->reg != MASK)
+ losing++;
+ break;
+
case 'I':
if (opP->mode != CONTROL
|| opP->reg < COP0
losing++;
break;
+ case 'i':
+ if (opP->mode != LSH && opP->mode != RSH)
+ losing++;
+ break;
+
case 'J':
if (opP->mode != CONTROL
|| opP->reg < USP
opP->mode = REGLST;
}
}
- else if (opP->mode == ABSL
- && opP->disp.size == SIZE_UNSPEC
- && opP->disp.exp.X_op == O_constant)
- {
- /* This is what the MRI REG pseudo-op generates. */
- opP->mode = REGLST;
- opP->mask = opP->disp.exp.X_add_number;
- }
else if (opP->mode != REGLST)
losing++;
else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
break;
case 'O':
- if (opP->mode != DREG && opP->mode != IMMED)
+ if (opP->mode != DREG
+ && opP->mode != IMMED
+ && opP->mode != ABSL)
losing++;
break;
losing++;
break;
+ case 'x':
+ if (opP->mode != IMMED)
+ losing++;
+ else if (opP->disp.exp.X_op != O_constant
+ || opP->disp.exp.X_add_number < -1
+ || opP->disp.exp.X_add_number > 7
+ || opP->disp.exp.X_add_number == 0)
+ losing++;
+ break;
+
/* JF these are out of order. We could put them
in order if we were willing to put up with
bunches of #ifdef m68851s in the code.
Don't forget that you need these operands
to use 68030 MMU instructions. */
#ifndef NO_68851
- /* Memory addressing mode used by pflushr */
+ /* Memory addressing mode used by pflushr. */
case '|':
if (opP->mode == CONTROL
|| opP->mode == FPREG
losing++;
break;
+ case 'w':
+ switch (opP->mode)
+ {
+ case IMMED:
+ case ABSL:
+ case AREG:
+ case DREG:
+ case FPREG:
+ case CONTROL:
+ case POST:
+ case PRE:
+ case REGLST:
+ losing++;
+ break;
+ default:
+ break;
+ }
+ break;
+
case 'X':
if (opP->mode != CONTROL
|| (!(opP->reg >= BAD && opP->reg <= BAD + 7)
&& opP->reg != IC
&& opP->reg != DC
&& opP->reg != BC))
- {
- losing++;
- } /* not a cache specifier. */
+ losing++;
break;
case '_':
++losing;
break;
+ case 'u':
+ if (opP->reg < DATA0L || opP->reg > ADDR7U)
+ losing++;
+ /* FIXME: kludge instead of fixing parser:
+ upper/lower registers are *not* CONTROL
+ registers, but ordinary ones. */
+ if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
+ || (opP->reg >= DATA0U && opP->reg <= DATA7U))
+ opP->mode = DREG;
+ else
+ opP->mode = AREG;
+ break;
+
+ case 'y':
+ if (!(opP->mode == AINDR
+ || (opP->mode == DISP
+ && !(opP->reg == PC || opP->reg == ZPC))))
+ losing++;
+ break;
+
+ case 'z':
+ if (!(opP->mode == AINDR || opP->mode == DISP))
+ losing++;
+ break;
+
default:
abort ();
- } /* switch on type of operand */
+ }
if (losing)
break;
- } /* for each operand */
- } /* if immediately wrong */
+ }
+ }
if (!losing)
- {
- break;
- } /* got it. */
+ break;
opcode = opcode->m_next;
&& !(ok_arch & current_architecture))
{
char buf[200], *cp;
- int len;
- strcpy (buf,
- "invalid instruction for this architecture; needs ");
+
+ strncpy (buf,
+ _("invalid instruction for this architecture; needs "),
+ sizeof (buf));
cp = buf + strlen (buf);
switch (ok_arch)
{
+ case mcfisa_a:
+ strncpy (cp, _("ColdFire ISA_A"),
+ sizeof (buf) - (cp - buf));
+ cp += strlen (cp);
+ strncpy (cp, find_cf_chip (ok_arch),
+ sizeof (buf) - (cp - buf));
+ cp += strlen (cp);
+ break;
+ case mcfhwdiv:
+ strncpy (cp, _("ColdFire hardware divide"),
+ sizeof (buf) - (cp - buf));
+ cp += strlen (cp);
+ strncpy (cp, find_cf_chip (ok_arch),
+ sizeof (buf) - (cp - buf));
+ cp += strlen (cp);
+ break;
+ case mcfisa_aa:
+ strncpy (cp, _("ColdFire ISA_A+"),
+ sizeof (buf) - (cp - buf));
+ cp += strlen (cp);
+ strncpy (cp, find_cf_chip (ok_arch),
+ sizeof (buf) - (cp - buf));
+ cp += strlen (cp);
+ break;
+ case mcfisa_b:
+ strncpy (cp, _("ColdFire ISA_B"),
+ sizeof (buf) - (cp - buf));
+ cp += strlen (cp);
+ strncpy (cp, find_cf_chip (ok_arch),
+ sizeof (buf) - (cp - buf));
+ cp += strlen (cp);
+ break;
+ case cfloat:
+ strncpy (cp, _("ColdFire fpu"), sizeof (buf) - (cp - buf));
+ cp += strlen (cp);
+ strncpy (cp, find_cf_chip (ok_arch),
+ sizeof (buf) - (cp - buf));
+ cp += strlen (cp);
+ break;
case mfloat:
- strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
+ strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
break;
case mmmu:
- strcpy (cp, "mmu (68030 or 68851)");
+ strcpy (cp, _("mmu (68030 or 68851)"));
break;
case m68020up:
- strcpy (cp, "68020 or higher");
+ strcpy (cp, _("68020 or higher"));
break;
case m68000up:
- strcpy (cp, "68000 or higher");
+ strcpy (cp, _("68000 or higher"));
break;
case m68010up:
- strcpy (cp, "68010 or higher");
+ strcpy (cp, _("68010 or higher"));
break;
default:
{
int got_one = 0, idx;
- for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
- idx++)
+
+ for (idx = 0; idx < n_archs; idx++)
{
if ((archs[idx].arch & ok_arch)
&& ! archs[idx].alias)
}
}
}
- len = cp - buf + 1;
- cp = malloc (len);
+ cp = xmalloc (strlen (buf) + 1);
strcpy (cp, buf);
the_ins.error = cp;
}
else
- the_ins.error = "operands mismatch";
+ the_ins.error = _("operands mismatch");
return;
- } /* Fell off the end */
+ }
losing = 0;
}
- /* now assemble it */
-
+ /* Now assemble it. */
the_ins.args = opcode->m_operands;
the_ins.numargs = opcode->m_opnum;
the_ins.numo = opcode->m_codenum;
for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
{
/* This switch is a doozy.
- Watch the first step; its a big one! */
+ Watch the first step; its a big one! */
switch (s[0])
{
case '$':
case '?':
case '/':
- case '`':
+ case '<':
+ case '>':
+ case 'b':
+ case 'm':
+ case 'n':
+ case 'o':
+ case 'p':
+ case 'q':
+ case 'v':
+ case 'w':
+ case 'y':
+ case 'z':
+ case '4':
#ifndef NO_68851
case '|':
#endif
case IMMED:
tmpreg = 0x3c; /* 7.4 */
if (strchr ("bwl", s[1]))
- nextword = get_num (&opP->disp, 80);
+ nextword = get_num (&opP->disp, 90);
else
nextword = get_num (&opP->disp, 0);
if (isvar (&opP->disp))
{
case 'b':
if (!isbyte (nextword))
- opP->error = "operand out of range";
+ opP->error = _("operand out of range");
addword (nextword);
baseo = 0;
break;
case 'w':
if (!isword (nextword))
- opP->error = "operand out of range";
+ opP->error = _("operand out of range");
addword (nextword);
baseo = 0;
break;
case 'W':
if (!issword (nextword))
- opP->error = "operand out of range";
+ opP->error = _("operand out of range");
addword (nextword);
baseo = 0;
break;
if (!baseo)
break;
- /* We gotta put out some float */
+ /* We gotta put out some float. */
if (op (&opP->disp) != O_big)
{
valueT val;
{
if (offs (&opP->disp) > baseo)
{
- as_warn ("Bignum too big for %c format; truncated",
+ as_warn (_("Bignum too big for %c format; truncated"),
s[1]);
offs (&opP->disp) = baseo;
}
break;
case DISP:
- nextword = get_num (&opP->disp, 80);
+ nextword = get_num (&opP->disp, 90);
+
+ /* Convert mode 5 addressing with a zero offset into
+ mode 2 addressing to reduce the instruction size by a
+ word. */
+ if (! isvar (&opP->disp)
+ && (nextword == 0)
+ && (opP->disp.size == SIZE_UNSPEC)
+ && (opP->reg >= ADDR0)
+ && (opP->reg <= ADDR7))
+ {
+ tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
+ break;
+ }
if (opP->reg == PC
&& ! isvar (&opP->disp)
#endif
}
- /* Force into index mode. Hope this works */
+ /* Force into index mode. Hope this works. */
/* We do the first bit for 32-bit displacements, and the
second bit for 16 bit ones. It is possible that we
|| (isvar (&opP->disp)
&& ((opP->disp.size == SIZE_UNSPEC
&& flag_short_refs == 0
- && cpu_of_arch (current_architecture) >= m68020)
+ && cpu_of_arch (current_architecture) >= m68020
+ && ! arch_coldfire_p (current_architecture))
|| opP->disp.size == SIZE_LONG)))
{
+ if (cpu_of_arch (current_architecture) < m68020
+ || arch_coldfire_p (current_architecture))
+ opP->error =
+ _("displacement too large for this architecture; needs 68020 or higher");
if (opP->reg == PC)
tmpreg = 0x3B; /* 7.3 */
else
{
add_frag (adds (&opP->disp),
offs (&opP->disp),
- TAB (PCLEA, SZ_UNDEF));
+ TAB (PCREL1632, SZ_UNDEF));
break;
}
}
case PRE:
case BASE:
nextword = 0;
- baseo = get_num (&opP->disp, 80);
+ baseo = get_num (&opP->disp, 90);
if (opP->mode == POST || opP->mode == PRE)
- outro = get_num (&opP->odisp, 80);
+ outro = get_num (&opP->odisp, 90);
/* Figure out the `addressing mode'.
Also turn on the BASE_DISABLE bit, if needed. */
if (opP->reg == PC || opP->reg == ZPC)
else
siz2 = SIZE_UNSPEC;
- /* Index register stuff */
+ /* Index register stuff. */
if (opP->index.reg != 0
&& opP->index.reg >= DATA
&& opP->index.reg <= ADDR7)
{
nextword |= (opP->index.reg - DATA) << 12;
- if (opP->index.size == SIZE_UNSPEC
- || opP->index.size == SIZE_LONG)
+ if (opP->index.size == SIZE_LONG
+ || (opP->index.size == SIZE_UNSPEC
+ && m68k_index_width_default == SIZE_LONG))
nextword |= 0x800;
- if (cpu_of_arch (current_architecture) < m68020)
+ if ((opP->index.scale != 1
+ && cpu_of_arch (current_architecture) < m68020)
+ || (opP->index.scale == 8
+ && (arch_coldfire_p (current_architecture)
+ && !arch_coldfire_fpu (current_architecture))))
{
- if (opP->index.scale != 1)
- {
- opP->error =
- "scale factor invalid on this architecture; needs 68020 or higher";
- }
+ opP->error =
+ _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
}
+ if (arch_coldfire_p (current_architecture)
+ && opP->index.size == SIZE_WORD)
+ opP->error = _("invalid index size for coldfire");
+
switch (opP->index.scale)
{
case 1:
{
if (siz1 == SIZE_BYTE
|| cpu_of_arch (current_architecture) < m68020
+ || arch_coldfire_p (current_architecture)
|| (siz1 == SIZE_UNSPEC
&& ! isvar (&opP->disp)
&& issbyte (baseo)))
else if (siz1 != SIZE_BYTE)
{
if (siz1 != SIZE_UNSPEC)
- as_warn ("Forcing byte displacement");
+ as_warn (_("Forcing byte displacement"));
if (! issbyte (baseo))
- opP->error = "byte displacement out of range";
+ opP->error = _("byte displacement out of range");
}
break;
#endif
)
{
- nextword += baseo & 0xff;
- addword (nextword);
- add_frag (adds (&opP->disp), offs (&opP->disp),
- TAB (PCINDEX, SZ_UNDEF));
+ /* The code in md_convert_frag_1 needs to be
+ able to adjust nextword. Call frag_grow
+ to ensure that we have enough space in
+ the frag obstack to make all the bytes
+ contiguous. */
+ frag_grow (14);
+ nextword += baseo & 0xff;
+ addword (nextword);
+ add_frag (adds (&opP->disp), offs (&opP->disp),
+ TAB (PCINDEX, SZ_UNDEF));
break;
- }
+ }
}
}
else
{
- nextword |= 0x40; /* No index reg */
+ nextword |= 0x40; /* No index reg. */
if (opP->index.reg >= ZDATA0
&& opP->index.reg <= ZDATA7)
nextword |= (opP->index.reg - ZDATA0) << 12;
/* It isn't simple. */
- if (cpu_of_arch (current_architecture) < m68020)
+ if (cpu_of_arch (current_architecture) < m68020
+ || arch_coldfire_p (current_architecture))
opP->error =
- "invalid operand mode for this architecture; needs 68020 or higher";
+ _("invalid operand mode for this architecture; needs 68020 or higher");
nextword |= 0x100;
/* If the guy specified a width, we assume that it is
}
break;
case SIZE_BYTE:
- as_warn (":b not permitted; defaulting to :w");
+ as_warn (_(":b not permitted; defaulting to :w"));
/* Fall through. */
case SIZE_WORD:
nextword |= 0x20;
break;
}
- /* Figure out innner displacement stuff */
+ /* Figure out inner displacement stuff. */
if (opP->mode == POST || opP->mode == PRE)
{
+ if (cpu_of_arch (current_architecture) & cpu32)
+ opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
switch (siz2)
{
case SIZE_UNSPEC:
}
break;
case 1:
- as_warn (":b not permitted; defaulting to :w");
+ as_warn (_(":b not permitted; defaulting to :w"));
/* Fall through. */
case 2:
nextword |= 0x2;
break;
case ABSL:
- nextword = get_num (&opP->disp, 80);
+ nextword = get_num (&opP->disp, 90);
switch (opP->disp.size)
{
default:
addword (nextword);
break;
}
- /* Don't generate pc relative code on 68010 and
- 68000. */
if (isvar (&opP->disp)
&& !subs (&opP->disp)
&& adds (&opP->disp)
cannot be relaxed. */
&& opP->disp.pic_reloc == pic_none
#endif
- && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
- && cpu_of_arch (current_architecture) >= m68020
&& !flag_long_jumps
&& !strchr ("~%&$?", s[0]))
{
tmpreg = 0x3A; /* 7.2 */
add_frag (adds (&opP->disp),
offs (&opP->disp),
- TAB (PCREL, SZ_UNDEF));
+ TAB (ABSTOPCREL, SZ_UNDEF));
break;
}
- /* Fall through into long */
+ /* Fall through into long. */
case SIZE_LONG:
if (isvar (&opP->disp))
add_fix ('l', &opP->disp, 0, 0);
addword (nextword);
break;
- case SIZE_WORD: /* Word */
+ case SIZE_BYTE:
+ as_bad (_("unsupported byte value; use a different suffix"));
+ /* Fall through. */
+
+ case SIZE_WORD:
if (isvar (&opP->disp))
add_fix ('w', &opP->disp, 0, 0);
case CONTROL:
case FPREG:
default:
- as_bad ("unknown/incorrect operand");
- /* abort(); */
+ as_bad (_("unknown/incorrect operand"));
+ /* abort (); */
+ }
+
+ /* If s[0] is '4', then this is for the mac instructions
+ that can have a trailing_ampersand set. If so, set 0x100
+ bit on tmpreg so install_gen_operand can check for it and
+ set the appropriate bit (word2, bit 5). */
+ if (s[0] == '4')
+ {
+ if (opP->trailing_ampersand)
+ tmpreg |= 0x100;
}
install_gen_operand (s[1], tmpreg);
break;
break;
case '3':
default:
- tmpreg = 80;
+ tmpreg = 90;
break;
}
tmpreg = get_num (&opP->disp, tmpreg);
certain types of overflow.
user beware! */
if (!isbyte (tmpreg))
- opP->error = "out of range";
+ opP->error = _("out of range");
insop (tmpreg, opcode);
if (isvar (&opP->disp))
- the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
+ the_ins.reloc[the_ins.nrel - 1].n =
+ (opcode->m_codenum) * 2 + 1;
+ break;
+ case 'B':
+ if (!issbyte (tmpreg))
+ opP->error = _("out of range");
+ the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
+ if (isvar (&opP->disp))
+ the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
break;
case 'w':
if (!isword (tmpreg))
- opP->error = "out of range";
+ opP->error = _("out of range");
insop (tmpreg, opcode);
if (isvar (&opP->disp))
the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
break;
case 'W':
if (!issword (tmpreg))
- opP->error = "out of range";
+ opP->error = _("out of range");
insop (tmpreg, opcode);
if (isvar (&opP->disp))
the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
tmpreg &= 0xFF;
case '8':
case 'C':
+ case 'j':
install_operand (s[1], tmpreg);
break;
default:
break;
case 'B':
- tmpreg = get_num (&opP->disp, 80);
+ tmpreg = get_num (&opP->disp, 90);
switch (s[1])
{
case 'B':
- /* The pc_fix argument winds up in fx_pcrel_adjust,
- which is a char, and may therefore be unsigned. We
- want to pass -1, but we pass 64 instead, and convert
- back in md_pcrel_from. */
- add_fix ('B', &opP->disp, 1, 64);
+ add_fix ('B', &opP->disp, 1, -1);
break;
case 'W':
add_fix ('w', &opP->disp, 1, 0);
break;
case 'L':
long_branch:
- if (cpu_of_arch (current_architecture) < m68020)
- as_warn ("Can't use long branches on 68000/68010");
- the_ins.opcode[the_ins.numo - 1] |= 0xff;
+ if (! HAVE_LONG_BRANCH (current_architecture))
+ as_warn (_("Can't use long branches on 68000/68010/5200"));
+ the_ins.opcode[0] |= 0xff;
add_fix ('l', &opP->disp, 1, 0);
addword (0);
addword (0);
break;
case 'g':
- if (subs (&opP->disp)) /* We can't relax it */
+ if (subs (&opP->disp)) /* We can't relax it. */
goto long_branch;
#ifdef OBJ_ELF
if (opP->disp.pic_reloc != pic_none)
goto long_branch;
#endif
-
/* This could either be a symbol, or an absolute
- address. No matter, the frag hacking will finger it
- out. Not quite: it can't switch from BRANCH to
- BCC68000 for the case where opnd is absolute (it
- needs to use the 68000 hack since no conditional abs
- jumps). */
- if (((cpu_of_arch (current_architecture) < m68020)
- || (0 == adds (&opP->disp)))
- && (the_ins.opcode[0] >= 0x6200)
- && (the_ins.opcode[0] <= 0x6f00))
+ address. If it's an absolute address, turn it into
+ an absolute jump right here and keep it out of the
+ relaxer. */
+ if (adds (&opP->disp) == 0)
+ {
+ if (the_ins.opcode[0] == 0x6000) /* jbra */
+ the_ins.opcode[0] = 0x4EF9;
+ else if (the_ins.opcode[0] == 0x6100) /* jbsr */
+ the_ins.opcode[0] = 0x4EB9;
+ else /* jCC */
+ {
+ the_ins.opcode[0] ^= 0x0100;
+ the_ins.opcode[0] |= 0x0006;
+ addword (0x4EF9);
+ }
+ add_fix ('l', &opP->disp, 0, 0);
+ addword (0);
+ addword (0);
+ break;
+ }
+
+ /* Now we know it's going into the relaxer. Now figure
+ out which mode. We try in this order of preference:
+ long branch, absolute jump, byte/word branches only. */
+ if (HAVE_LONG_BRANCH (current_architecture))
add_frag (adds (&opP->disp), offs (&opP->disp),
- TAB (BCC68000, SZ_UNDEF));
+ TAB (BRANCHBWL, SZ_UNDEF));
+ else if (! flag_keep_pcrel)
+ {
+ if ((the_ins.opcode[0] == 0x6000)
+ || (the_ins.opcode[0] == 0x6100))
+ add_frag (adds (&opP->disp), offs (&opP->disp),
+ TAB (BRABSJUNC, SZ_UNDEF));
+ else
+ add_frag (adds (&opP->disp), offs (&opP->disp),
+ TAB (BRABSJCOND, SZ_UNDEF));
+ }
else
add_frag (adds (&opP->disp), offs (&opP->disp),
- TAB (ABRANCH, SZ_UNDEF));
+ TAB (BRANCHBW, SZ_UNDEF));
break;
case 'w':
if (isvar (&opP->disp))
{
-#if 1
- /* check for DBcc instruction */
- if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
+ /* Check for DBcc instructions. We can relax them,
+ but only if we have long branches and/or absolute
+ jumps. */
+ if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
+ && (HAVE_LONG_BRANCH (current_architecture)
+ || (! flag_keep_pcrel)))
{
- /* size varies if patch */
- /* needed for long form */
- add_frag (adds (&opP->disp), offs (&opP->disp),
- TAB (DBCC, SZ_UNDEF));
+ if (HAVE_LONG_BRANCH (current_architecture))
+ add_frag (adds (&opP->disp), offs (&opP->disp),
+ TAB (DBCCLBR, SZ_UNDEF));
+ else
+ add_frag (adds (&opP->disp), offs (&opP->disp),
+ TAB (DBCCABSJ, SZ_UNDEF));
break;
}
-#endif
add_fix ('w', &opP->disp, 1, 0);
}
addword (0);
break;
- case 'C': /* Fixed size LONG coproc branches */
+ case 'C': /* Fixed size LONG coproc branches. */
add_fix ('l', &opP->disp, 1, 0);
addword (0);
addword (0);
break;
- case 'c': /* Var size Coprocesssor branches */
- if (subs (&opP->disp))
- {
- add_fix ('l', &opP->disp, 1, 0);
- add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
- }
- else if (adds (&opP->disp))
- add_frag (adds (&opP->disp), offs (&opP->disp),
- TAB (FBRANCH, SZ_UNDEF));
- else
+ case 'c': /* Var size Coprocesssor branches. */
+ if (subs (&opP->disp) || (adds (&opP->disp) == 0))
{
- /* add_frag((symbolS *) 0, offs(&opP->disp),
- TAB(FBRANCH,SHORT)); */
the_ins.opcode[the_ins.numo - 1] |= 0x40;
add_fix ('l', &opP->disp, 1, 0);
addword (0);
addword (0);
}
+ else
+ add_frag (adds (&opP->disp), offs (&opP->disp),
+ TAB (FBRANCH, SZ_UNDEF));
break;
default:
abort ();
}
break;
- case 'C': /* Ignore it */
+ case 'C': /* Ignore it. */
break;
- case 'd': /* JF this is a kludge */
+ case 'd': /* JF this is a kludge. */
install_operand ('s', opP->reg - ADDR);
- tmpreg = get_num (&opP->disp, 80);
+ tmpreg = get_num (&opP->disp, 90);
if (!issword (tmpreg))
{
- as_warn ("Expression out of range, using 0");
+ as_warn (_("Expression out of range, using 0"));
tmpreg = 0;
}
addword (tmpreg);
install_operand (s[1], opP->reg - DATA);
break;
+ case 'e': /* EMAC ACCx, reg/reg. */
+ install_operand (s[1], opP->reg - ACC);
+ break;
+
+ case 'E': /* Ignore it. */
+ break;
+
case 'F':
install_operand (s[1], opP->reg - FP0);
break;
+ case 'g': /* EMAC ACCEXTx. */
+ install_operand (s[1], opP->reg - ACCEXT01);
+ break;
+
+ case 'G': /* Ignore it. */
+ case 'H':
+ break;
+
case 'I':
tmpreg = opP->reg - COP0;
install_operand (s[1], tmpreg);
break;
- case 'J': /* JF foo */
+ case 'i': /* MAC/EMAC scale factor. */
+ install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
+ break;
+
+ case 'J': /* JF foo. */
switch (opP->reg)
{
case SFC:
case TC:
tmpreg = 0x003;
break;
+ case ACR0:
case ITT0:
tmpreg = 0x004;
break;
+ case ACR1:
case ITT1:
tmpreg = 0x005;
break;
+ case ACR2:
case DTT0:
tmpreg = 0x006;
break;
+ case ACR3:
case DTT1:
tmpreg = 0x007;
break;
case PCR:
tmpreg = 0x808;
break;
+ case ROMBAR:
+ tmpreg = 0xC00;
+ break;
+ case ROMBAR1:
+ tmpreg = 0xC01;
+ break;
+ case FLASHBAR:
+ case RAMBAR0:
+ tmpreg = 0xC04;
+ break;
+ case RAMBAR:
+ case RAMBAR1:
+ tmpreg = 0xC05;
+ break;
+ case MPCR:
+ tmpreg = 0xC0C;
+ break;
+ case EDRAMBAR:
+ tmpreg = 0xC0D;
+ break;
+ case MBAR0:
+ case MBAR2:
+ case SECMBAR:
+ tmpreg = 0xC0E;
+ break;
+ case MBAR1:
+ case MBAR:
+ tmpreg = 0xC0F;
+ break;
+ case PCR1U0:
+ tmpreg = 0xD02;
+ break;
+ case PCR1L0:
+ tmpreg = 0xD03;
+ break;
+ case PCR2U0:
+ tmpreg = 0xD04;
+ break;
+ case PCR2L0:
+ tmpreg = 0xD05;
+ break;
+ case PCR3U0:
+ tmpreg = 0xD06;
+ break;
+ case PCR3L0:
+ tmpreg = 0xD07;
+ break;
+ case PCR1L1:
+ tmpreg = 0xD0A;
+ break;
+ case PCR1U1:
+ tmpreg = 0xD0B;
+ break;
+ case PCR2L1:
+ tmpreg = 0xD0C;
+ break;
+ case PCR2U1:
+ tmpreg = 0xD0D;
+ break;
+ case PCR3L1:
+ tmpreg = 0xD0E;
+ break;
+ case PCR3U1:
+ tmpreg = 0xD0F;
+ break;
default:
abort ();
}
if (s[1] == 'w')
{
if (tmpreg & 0x7FF0000)
- as_bad ("Floating point register in register list");
+ as_bad (_("Floating point register in register list"));
insop (reverse_16_bits (tmpreg), opcode);
}
else
{
if (tmpreg & 0x700FFFF)
- as_bad ("Wrong register in floating-point reglist");
+ as_bad (_("Wrong register in floating-point reglist"));
install_operand (s[1], reverse_8_bits (tmpreg >> 16));
}
break;
if (s[1] == 'w')
{
if (tmpreg & 0x7FF0000)
- as_bad ("Floating point register in register list");
+ as_bad (_("Floating point register in register list"));
insop (tmpreg, opcode);
}
else if (s[1] == '8')
{
if (tmpreg & 0x0FFFFFF)
- as_bad ("incorrect register in reglist");
+ as_bad (_("incorrect register in reglist"));
install_operand (s[1], tmpreg >> 24);
}
else
{
if (tmpreg & 0x700FFFF)
- as_bad ("wrong register in floating-point reglist");
+ as_bad (_("wrong register in floating-point reglist"));
else
install_operand (s[1], tmpreg >> 16);
}
case 'O':
tmpreg = ((opP->mode == DREG)
- ? 0x20 + opP->reg - DATA
+ ? 0x20 + (int) (opP->reg - DATA)
: (get_num (&opP->disp, 40) & 0x1F));
install_operand (s[1], tmpreg);
break;
case 'R':
/* This depends on the fact that ADDR registers are eight
more than their corresponding DATA regs, so the result
- will have the ADDR_REG bit set */
+ will have the ADDR_REG bit set. */
install_operand (s[1], opP->reg - DATA);
break;
install_operand (s[1], tmpreg);
break;
- case 'S': /* Ignore it */
+ case 'S': /* Ignore it. */
break;
case 'T':
install_operand (s[1], get_num (&opP->disp, 30));
break;
- case 'U': /* Ignore it */
+ case 'U': /* Ignore it. */
break;
case 'c':
tmpreg = 3;
break;
default:
- as_fatal ("failed sanity check");
- } /* switch on cache token */
+ as_fatal (_("failed sanity check"));
+ } /* switch on cache token. */
install_operand (s[1], tmpreg);
break;
#ifndef NO_68851
- /* JF: These are out of order, I fear. */
+ /* JF: These are out of order, I fear. */
case 'f':
switch (opP->reg)
{
tmpreg = get_num (&opP->disp, 20);
install_operand (s[1], tmpreg);
break;
- case '_': /* used only for move16 absolute 32-bit address */
- tmpreg = get_num (&opP->disp, 80);
+ case '_': /* used only for move16 absolute 32-bit address. */
+ if (isvar (&opP->disp))
+ add_fix ('l', &opP->disp, 0, 0);
+ tmpreg = get_num (&opP->disp, 90);
addword (tmpreg >> 16);
addword (tmpreg & 0xFFFF);
break;
+ case 'u':
+ install_operand (s[1], opP->reg - DATA0L);
+ opP->reg -= (DATA0L);
+ opP->reg &= 0x0F; /* remove upper/lower bit. */
+ break;
+ case 'x':
+ tmpreg = get_num (&opP->disp, 80);
+ if (tmpreg == -1)
+ tmpreg = 0;
+ install_operand (s[1], tmpreg);
+ break;
default:
abort ();
}
}
/* By the time whe get here (FINALLY) the_ins contains the complete
- instruction, ready to be emitted. . . */
+ instruction, ready to be emitted. . . */
}
static int
-reverse_16_bits (in)
- int in;
+reverse_16_bits (int in)
{
int out = 0;
int n;
} /* reverse_16_bits() */
static int
-reverse_8_bits (in)
- int in;
+reverse_8_bits (int in)
{
int out = 0;
int n;
ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
static void
-install_operand (mode, val)
- int mode;
- int val;
+install_operand (int mode, int val)
{
switch (mode)
{
case 's':
- the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
+ the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
break;
case 'd':
the_ins.opcode[0] |= val << 9;
break;
case 'j':
the_ins.opcode[1] |= val;
- the_ins.numo++; /* What a hack */
+ the_ins.numo++; /* What a hack. */
break;
case 'k':
the_ins.opcode[1] |= val << 4;
the_ins.opcode[1] = (val >> 16);
the_ins.opcode[2] = val & 0xffff;
break;
+ case 'm':
+ the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
+ the_ins.opcode[0] |= ((val & 0x7) << 9);
+ the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
+ break;
+ case 'n': /* MAC/EMAC Rx on !load. */
+ the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
+ the_ins.opcode[0] |= ((val & 0x7) << 9);
+ the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
+ break;
+ case 'o': /* MAC/EMAC Rx on load. */
+ the_ins.opcode[1] |= val << 12;
+ the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
+ break;
+ case 'M': /* MAC/EMAC Ry on !load. */
+ the_ins.opcode[0] |= (val & 0xF);
+ the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
+ break;
+ case 'N': /* MAC/EMAC Ry on load. */
+ the_ins.opcode[1] |= (val & 0xF);
+ the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
+ break;
+ case 'h':
+ the_ins.opcode[1] |= ((val != 1) << 10);
+ break;
+ case 'F':
+ the_ins.opcode[0] |= ((val & 0x3) << 9);
+ break;
+ case 'f':
+ the_ins.opcode[0] |= ((val & 0x3) << 0);
+ break;
+ case 'G': /* EMAC accumulator in a EMAC load instruction. */
+ the_ins.opcode[0] |= ((~val & 0x1) << 7);
+ the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
+ break;
+ case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
+ the_ins.opcode[0] |= ((val & 0x1) << 7);
+ the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
+ break;
+ case 'I':
+ the_ins.opcode[1] |= ((val & 0x3) << 9);
+ break;
+ case ']':
+ the_ins.opcode[0] |= (val & 0x1) <<10;
+ break;
case 'c':
default:
- as_fatal ("failed sanity check.");
+ as_fatal (_("failed sanity check."));
}
-} /* install_operand() */
+}
static void
-install_gen_operand (mode, val)
- int mode;
- int val;
+install_gen_operand (int mode, int val)
{
switch (mode)
{
+ case '/': /* Special for mask loads for mac/msac insns with
+ possible mask; trailing_ampersend set in bit 8. */
+ the_ins.opcode[0] |= (val & 0x3f);
+ the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
+ break;
case 's':
the_ins.opcode[0] |= val;
break;
case 'p':
the_ins.opcode[0] |= val;
break;
- /* more stuff goes here */
+ /* more stuff goes here. */
default:
- as_fatal ("failed sanity check.");
+ as_fatal (_("failed sanity check."));
}
-} /* install_gen_operand() */
+}
-/*
- * verify that we have some number of paren pairs, do m68k_ip_op(), and
- * then deal with the bitfield hack.
- */
+/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
+ then deal with the bitfield hack. */
static char *
-crack_operand (str, opP)
- register char *str;
- register struct m68k_op *opP;
+crack_operand (char *str, struct m68k_op *opP)
{
register int parens;
register int c;
else if (*str == ')')
{
if (!parens)
- { /* ERROR */
- opP->error = "Extra )";
+ { /* ERROR. */
+ opP->error = _("Extra )");
return str;
}
--parens;
inquote = ! inquote;
}
if (!*str && parens)
- { /* ERROR */
- opP->error = "Missing )";
+ { /* ERROR. */
+ opP->error = _("Missing )");
return str;
}
c = *str;
}
*str = c;
if (c == '}')
- c = *++str; /* JF bitfield hack */
+ c = *++str; /* JF bitfield hack. */
if (c)
{
c = *++str;
if (!c)
- as_bad ("Missing operand");
+ as_bad (_("Missing operand"));
+ }
+
+ /* Detect MRI REG symbols and convert them to REGLSTs. */
+ if (opP->mode == CONTROL && (int)opP->reg < 0)
+ {
+ opP->mode = REGLST;
+ opP->mask = ~(int)opP->reg;
+ opP->reg = 0;
}
+
return str;
}
the frags/bytes it assembles to.
*/
-void
-insert_reg (regname, regnum)
- char *regname;
- int regnum;
+static void
+insert_reg (const char *regname, int regnum)
{
char buf[100];
int i;
&zero_address_frag));
for (i = 0; regname[i]; i++)
- buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
+ buf[i] = TOUPPER (regname[i]);
buf[i] = '\0';
symbol_table_insert (symbol_new (buf, reg_section, regnum,
{ "ccr", CCR },
{ "cc", CCR },
- { "usp", USP },
- { "isp", ISP },
- { "sfc", SFC },
+ { "acc", ACC },
+ { "acc0", ACC },
+ { "acc1", ACC1 },
+ { "acc2", ACC2 },
+ { "acc3", ACC3 },
+ { "accext01", ACCEXT01 },
+ { "accext23", ACCEXT23 },
+ { "macsr", MACSR },
+ { "mask", MASK },
+
+ /* Control registers. */
+ { "sfc", SFC }, /* Source Function Code. */
{ "sfcr", SFC },
- { "dfc", DFC },
+ { "dfc", DFC }, /* Destination Function Code. */
{ "dfcr", DFC },
- { "cacr", CACR },
- { "caar", CAAR },
-
- { "vbr", VBR },
-
- { "msp", MSP },
- { "itt0", ITT0 },
- { "itt1", ITT1 },
- { "dtt0", DTT0 },
- { "dtt1", DTT1 },
- { "mmusr", MMUSR },
- { "tc", TC },
- { "srp", SRP },
- { "urp", URP },
+ { "cacr", CACR }, /* Cache Control Register. */
+ { "caar", CAAR }, /* Cache Address Register. */
+
+ { "usp", USP }, /* User Stack Pointer. */
+ { "vbr", VBR }, /* Vector Base Register. */
+ { "msp", MSP }, /* Master Stack Pointer. */
+ { "isp", ISP }, /* Interrupt Stack Pointer. */
+
+ { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
+ { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
+ { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
+ { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
+
+ /* 68ec040 versions of same */
+ { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
+ { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
+ { "dacr0", DTT0 }, /* Data Access Control Register 0. */
+ { "dacr1", DTT1 }, /* Data Access Control Register 0. */
+
+ /* mcf5200 versions of same. The ColdFire programmer's reference
+ manual indicated that the order is 2,3,0,1, but Ken Rose
+ <rose@netcom.com> says that 0,1,2,3 is the correct order. */
+ { "acr0", ACR0 }, /* Access Control Unit 0. */
+ { "acr1", ACR1 }, /* Access Control Unit 1. */
+ { "acr2", ACR2 }, /* Access Control Unit 2. */
+ { "acr3", ACR3 }, /* Access Control Unit 3. */
+
+ { "tc", TC }, /* MMU Translation Control Register. */
+ { "tcr", TC },
+
+ { "mmusr", MMUSR }, /* MMU Status Register. */
+ { "srp", SRP }, /* User Root Pointer. */
+ { "urp", URP }, /* Supervisor Root Pointer. */
+
{ "buscr", BUSCR },
{ "pcr", PCR },
+ { "rombar", ROMBAR }, /* ROM Base Address Register. */
+ { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
+ { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
+ { "mbar", MBAR }, /* Module Base Address Register. */
+
+ { "mbar0", MBAR0 }, /* mcfv4e registers. */
+ { "mbar1", MBAR1 }, /* mcfv4e registers. */
+ { "rombar0", ROMBAR }, /* mcfv4e registers. */
+ { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
+ { "mpcr", MPCR }, /* mcfv4e registers. */
+ { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
+ { "secmbar", SECMBAR }, /* mcfv4e registers. */
+ { "asid", TC }, /* mcfv4e registers. */
+ { "mmubar", BUSCR }, /* mcfv4e registers. */
+ { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
+ { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
+ { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
+ { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
+ { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
+ { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
+ { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
+ { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
+ { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
+ { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
+ { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
+ { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
+
+ { "flashbar", FLASHBAR }, /* mcf528x registers. */
+ { "rambar", RAMBAR }, /* mcf528x registers. */
+
+ { "mbar2", MBAR2 }, /* mcf5249 registers. */
+ /* End of control registers. */
+
{ "ac", AC },
{ "bc", BC },
{ "cal", CAL },
{ "tt0", TT0 },
{ "tt1", TT1 },
- /* 68ec030 versions of same */
+ /* 68ec030 versions of same. */
{ "ac0", TT0 },
{ "ac1", TT1 },
- /* 68ec030 access control unit, identical to 030 MMU status reg */
+ /* 68ec030 access control unit, identical to 030 MMU status reg. */
{ "acusr", PSR },
/* Suppressed data and address registers. */
{ "za6", ZADDR6 },
{ "za7", ZADDR7 },
+ /* Upper and lower data and address registers, used by macw and msacw. */
+ { "d0l", DATA0L },
+ { "d1l", DATA1L },
+ { "d2l", DATA2L },
+ { "d3l", DATA3L },
+ { "d4l", DATA4L },
+ { "d5l", DATA5L },
+ { "d6l", DATA6L },
+ { "d7l", DATA7L },
+
+ { "a0l", ADDR0L },
+ { "a1l", ADDR1L },
+ { "a2l", ADDR2L },
+ { "a3l", ADDR3L },
+ { "a4l", ADDR4L },
+ { "a5l", ADDR5L },
+ { "a6l", ADDR6L },
+ { "a7l", ADDR7L },
+
+ { "d0u", DATA0U },
+ { "d1u", DATA1U },
+ { "d2u", DATA2U },
+ { "d3u", DATA3U },
+ { "d4u", DATA4U },
+ { "d5u", DATA5U },
+ { "d6u", DATA6U },
+ { "d7u", DATA7U },
+
+ { "a0u", ADDR0U },
+ { "a1u", ADDR1U },
+ { "a2u", ADDR2U },
+ { "a3u", ADDR3U },
+ { "a4u", ADDR4U },
+ { "a5u", ADDR5U },
+ { "a6u", ADDR6U },
+ { "a7u", ADDR7U },
+
{ 0, 0 }
};
-void
-init_regtable ()
+static void
+init_regtable (void)
{
int i;
for (i = 0; init_table[i].name; i++)
#endif
void
-md_assemble (str)
- char *str;
+md_assemble (char *str)
{
const char *er;
short *fromP;
}
}
- memset ((char *) (&the_ins), '\0', sizeof (the_ins));
+ memset (&the_ins, '\0', sizeof (the_ins));
m68k_ip (str);
er = the_ins.error;
if (!er)
}
if (er)
{
- as_bad ("%s -- statement `%s' ignored", er, str);
+ as_bad (_("%s -- statement `%s' ignored"), er, str);
return;
}
+ /* If there is a current label, record that it marks an instruction. */
+ if (current_label != NULL)
+ {
+ current_label->text = 1;
+ current_label = NULL;
+ }
+
+#ifdef OBJ_ELF
+ /* Tie dwarf2 debug info to the address at the start of the insn. */
+ dwarf2_emit_insn (0);
+#endif
+
if (the_ins.nfrag == 0)
{
- /* No frag hacking involved; just put it out */
+ /* No frag hacking involved; just put it out. */
toP = frag_more (2 * the_ins.numo);
fromP = &the_ins.opcode[0];
for (m = the_ins.numo; m; --m)
toP += 2;
fromP++;
}
- /* put out symbol-dependent info */
+ /* Put out symbol-dependent info. */
for (m = 0; m < the_ins.nrel; m++)
{
switch (the_ins.reloc[m].wid)
n = 1;
break;
case '3':
- n = 2;
+ n = 1;
break;
case 'w':
+ case 'W':
n = 2;
break;
case 'l':
n = 4;
break;
default:
- as_fatal ("Don't know how to figure width of %c in md_assemble()",
+ as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
the_ins.reloc[m].wid);
}
get_reloc_code (n, the_ins.reloc[m].pcrel,
the_ins.reloc[m].pic_reloc));
fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
+ if (the_ins.reloc[m].wid == 'B')
+ fixP->fx_signed = 1;
}
return;
}
- /* There's some frag hacking */
+ /* There's some frag hacking. */
+ {
+ /* Calculate the max frag size. */
+ int wid;
+
+ wid = 2 * the_ins.fragb[0].fragoff;
+ for (n = 1; n < the_ins.nfrag; n++)
+ wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
+ /* frag_var part. */
+ wid += 10;
+ /* Make sure the whole insn fits in one chunk, in particular that
+ the var part is attached, as we access one byte before the
+ variable frag for byte branches. */
+ frag_grow (wid);
+ }
+
for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
{
int wid;
}
}
+/* Comparison function used by qsort to rank the opcode entries by name. */
+
+static int
+m68k_compare_opcode (const void * v1, const void * v2)
+{
+ struct m68k_opcode * op1, * op2;
+ int ret;
+
+ op1 = *(struct m68k_opcode **) v1;
+ op2 = *(struct m68k_opcode **) v2;
+
+ /* Compare the two names. If different, return the comparison.
+ If the same, return the order they are in the opcode table. */
+ ret = strcmp (op1->name, op2->name);
+ if (ret)
+ return ret;
+ if (op1 < op2)
+ return -1;
+ return 0;
+}
+
void
-md_begin ()
+md_begin (void)
{
- /*
- * md_begin -- set up hash tables with 68000 instructions.
- * similar to what the vax assembler does. ---phr
- */
+ const struct m68k_opcode *ins;
+ struct m68k_incant *hack, *slak;
+ const char *retval = 0; /* Empty string, or error msg text. */
+ int i;
+
+ /* Set up hash tables with 68000 instructions.
+ similar to what the vax assembler does. */
/* RMS claims the thing to do is take the m68k-opcode.h table, and make
a copy of it at runtime, adding in the information we want but isn't
there. I think it'd be better to have an awk script hack the table
my lord ghod hath spoken, so we do it this way. Excuse the ugly var
names. */
- register const struct m68k_opcode *ins;
- register struct m68k_incant *hack, *slak;
- register const char *retval = 0; /* empty string, or error msg text */
- register unsigned int i;
- register char c;
-
if (flag_mri)
{
flag_reg_prefix_optional = 1;
m68k_abspcadd = 1;
- m68k_rel32 = 0;
+ if (! m68k_rel32_from_cmdline)
+ m68k_rel32 = 0;
}
+ /* First sort the opcode table into alphabetical order to seperate
+ the order that the assembler wants to see the opcodes from the
+ order that the disassembler wants to see them. */
+ m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
+ if (!m68k_sorted_opcodes)
+ as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
+ m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
+
+ for (i = m68k_numopcodes; i--;)
+ m68k_sorted_opcodes[i] = m68k_opcodes + i;
+
+ qsort (m68k_sorted_opcodes, m68k_numopcodes,
+ sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
+
op_hash = hash_new ();
obstack_begin (&robyn, 4000);
hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
do
{
- ins = &m68k_opcodes[i];
- /* We *could* ignore insns that don't match our arch here
- but just leaving them out of the hash. */
+ ins = m68k_sorted_opcodes[i];
+
+ /* We *could* ignore insns that don't match our
+ arch here by just leaving them out of the hash. */
slak->m_operands = ins->args;
slak->m_opnum = strlen (slak->m_operands) / 2;
slak->m_arch = ins->arch;
slak->m_opcode = ins->opcode;
- /* This is kludgey */
+ /* This is kludgey. */
slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
if (i + 1 != m68k_numopcodes
- && !strcmp (ins->name, m68k_opcodes[i + 1].name))
+ && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
{
- slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
+ slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
i++;
}
else
retval = hash_insert (op_hash, ins->name, (char *) hack);
if (retval)
- as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
+ as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
}
for (i = 0; i < m68k_numaliases; i++)
const char *name = m68k_opcode_aliases[i].primary;
const char *alias = m68k_opcode_aliases[i].alias;
PTR val = hash_find (op_hash, name);
+
if (!val)
- as_fatal ("Internal Error: Can't find %s in hash table", name);
+ as_fatal (_("Internal Error: Can't find %s in hash table"), name);
retval = hash_insert (op_hash, alias, val);
if (retval)
- as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
+ as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
}
/* In MRI mode, all unsized branches are variable sized. Normally,
{ "bsr", "jbsr", },
};
- for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
+ for (i = 0;
+ i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
+ i++)
{
const char *name = mri_aliases[i].primary;
const char *alias = mri_aliases[i].alias;
PTR val = hash_find (op_hash, name);
+
if (!val)
- as_fatal ("Internal Error: Can't find %s in hash table", name);
+ as_fatal (_("Internal Error: Can't find %s in hash table"), name);
retval = hash_jam (op_hash, alias, val);
if (retval)
- as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
+ as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
}
}
- for (i = 0; i < sizeof (mklower_table); i++)
- mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
-
- for (i = 0; i < sizeof (notend_table); i++)
+ for (i = 0; i < (int) sizeof (notend_table); i++)
{
notend_table[i] = 0;
alt_notend_table[i] = 0;
}
+
notend_table[','] = 1;
notend_table['{'] = 1;
notend_table['}'] = 1;
#endif
/* We need to put '(' in alt_notend_table to handle
- cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
- */
+ cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
alt_notend_table['('] = 1;
/* We need to put '@' in alt_notend_table to handle
- cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
- */
+ cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
alt_notend_table['@'] = 1;
+ /* We need to put digits in alt_notend_table to handle
+ bfextu %d0{24:1},%d0 */
+ alt_notend_table['0'] = 1;
+ alt_notend_table['1'] = 1;
+ alt_notend_table['2'] = 1;
+ alt_notend_table['3'] = 1;
+ alt_notend_table['4'] = 1;
+ alt_notend_table['5'] = 1;
+ alt_notend_table['6'] = 1;
+ alt_notend_table['7'] = 1;
+ alt_notend_table['8'] = 1;
+ alt_notend_table['9'] = 1;
+
#ifndef MIT_SYNTAX_ONLY
/* Insert pseudo ops, these have to go into the opcode table since
- gas expects pseudo ops to start with a dot */
+ gas expects pseudo ops to start with a dot. */
{
int n = 0;
+
while (mote_pseudo_table[n].poc_name)
{
- hack = (struct m68k_incant *)
- obstack_alloc (&robyn, sizeof (struct m68k_incant));
+ hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
hash_insert (op_hash,
mote_pseudo_table[n].poc_name, (char *) hack);
hack->m_operands = 0;
#endif
}
+static void
+select_control_regs (void)
+{
+ /* Note which set of "movec" control registers is available. */
+ switch (current_chip)
+ {
+ case 0:
+ if (verbose)
+ as_warn (_("architecture not yet selected: defaulting to 68020"));
+ control_regs = m68020_control_regs;
+ break;
+
+ case m68000:
+ control_regs = m68000_control_regs;
+ break;
+ case m68010:
+ control_regs = m68010_control_regs;
+ break;
+ case m68020:
+ case m68030:
+ control_regs = m68020_control_regs;
+ break;
+ case m68040:
+ control_regs = m68040_control_regs;
+ break;
+ case m68060:
+ control_regs = m68060_control_regs;
+ break;
+ case cpu32:
+ control_regs = cpu32_control_regs;
+ break;
+ case mcf5200:
+ case mcf5206e:
+ case mcf5307:
+ case mcf5407:
+ control_regs = mcf_control_regs;
+ break;
+ case mcf5249:
+ control_regs = mcf5249_control_regs;
+ break;
+ case mcf528x:
+ case mcf521x:
+ control_regs = mcf528x_control_regs;
+ break;
+ case mcf5470:
+ case mcf5480:
+ control_regs = mcfv4e_control_regs;
+ break;
+ default:
+ abort ();
+ }
+}
+
void
-m68k_init_after_args ()
+m68k_init_after_args (void)
{
if (cpu_of_arch (current_architecture) == 0)
{
break;
if (i == n_archs)
{
- as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
+ as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
current_architecture |= m68020;
}
else
if (current_architecture & m68851)
{
if (current_architecture & m68040)
- {
- as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
- }
+ as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
}
/* What other incompatibilities could we check for? */
&& (cpu_of_arch (current_architecture)
/* Can CPU32 have a 68881 coprocessor?? */
& (m68020 | m68030 | cpu32)))
- {
- current_architecture |= m68881;
- }
+ current_architecture |= m68881;
+
if (!no_68851
&& (cpu_of_arch (current_architecture) & m68020up) != 0
&& (cpu_of_arch (current_architecture) & m68040up) == 0)
- {
- current_architecture |= m68851;
- }
+ current_architecture |= m68851;
+
if (no_68881 && (current_architecture & m68881))
- as_bad ("options for 68881 and no-68881 both given");
+ as_bad (_("options for 68881 and no-68881 both given"));
+
if (no_68851 && (current_architecture & m68851))
- as_bad ("options for 68851 and no-68851 both given");
+ as_bad (_("options for 68851 and no-68851 both given"));
#ifdef OBJ_AOUT
/* Work out the magic number. This isn't very general. */
#endif
/* Note which set of "movec" control registers is available. */
- switch (cpu_of_arch (current_architecture))
- {
- case m68000:
- control_regs = m68000_control_regs;
- break;
- case m68010:
- control_regs = m68010_control_regs;
- break;
- case m68020:
- case m68030:
- control_regs = m68020_control_regs;
- break;
- case m68040:
- control_regs = m68040_control_regs;
- break;
- case m68060:
- control_regs = m68060_control_regs;
- break;
- case cpu32:
- control_regs = cpu32_control_regs;
- break;
- default:
- abort ();
- }
+ select_control_regs ();
- if (cpu_of_arch (current_architecture) < m68020)
+ if (cpu_of_arch (current_architecture) < m68020
+ || arch_coldfire_p (current_architecture))
md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
}
+\f
+/* This is called when a label is defined. */
+
+void
+m68k_frob_label (symbolS *sym)
+{
+ struct label_line *n;
+
+ n = (struct label_line *) xmalloc (sizeof *n);
+ n->next = labels;
+ n->label = sym;
+ as_where (&n->file, &n->line);
+ n->text = 0;
+ labels = n;
+ current_label = n;
+}
+
+/* This is called when a value that is not an instruction is emitted. */
+
+void
+m68k_flush_pending_output (void)
+{
+ current_label = NULL;
+}
+
+/* This is called at the end of the assembly, when the final value of
+ the label is known. We warn if this is a text symbol aligned at an
+ odd location. */
+
+void
+m68k_frob_symbol (symbolS *sym)
+{
+ if (S_GET_SEGMENT (sym) == reg_section
+ && (int) S_GET_VALUE (sym) < 0)
+ {
+ S_SET_SEGMENT (sym, absolute_section);
+ S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
+ }
+ else if ((S_GET_VALUE (sym) & 1) != 0)
+ {
+ struct label_line *l;
+ for (l = labels; l != NULL; l = l->next)
+ {
+ if (l->label == sym)
+ {
+ if (l->text)
+ as_warn_where (l->file, l->line,
+ _("text label `%s' aligned to odd boundary"),
+ S_GET_NAME (sym));
+ break;
+ }
+ }
+ }
+}
+\f
/* This is called if we go in or out of MRI mode because of the .mri
pseudo-op. */
void
-m68k_mri_mode_change (on)
- int on;
+m68k_mri_mode_change (int on)
{
if (on)
{
#endif
}
m68k_abspcadd = 1;
- m68k_rel32 = 0;
+ if (! m68k_rel32_from_cmdline)
+ m68k_rel32 = 0;
}
else
{
#endif
}
m68k_abspcadd = 0;
- m68k_rel32 = 1;
+ if (! m68k_rel32_from_cmdline)
+ m68k_rel32 = 1;
}
}
-/* Equal to MAX_PRECISION in atof-ieee.c */
+/* Equal to MAX_PRECISION in atof-ieee.c. */
#define MAX_LITTLENUMS 6
/* Turn a string in input_line_pointer into a floating point constant
- of type type, and store the appropriate bytes in *litP. The number
- of LITTLENUMS emitted is stored in *sizeP . An error message is
+ of type TYPE, and store the appropriate bytes in *LITP. The number
+ of LITTLENUMS emitted is stored in *SIZEP. An error message is
returned, or NULL on OK. */
char *
-md_atof (type, litP, sizeP)
- char type;
- char *litP;
- int *sizeP;
+md_atof (int type, char *litP, int *sizeP)
{
int prec;
LITTLENUM_TYPE words[MAX_LITTLENUMS];
LITTLENUM_TYPE *wordP;
char *t;
- char *atof_ieee ();
switch (type)
{
default:
*sizeP = 0;
- return "Bad call to MD_ATOF()";
+ return _("Bad call to MD_ATOF()");
}
t = atof_ieee (input_line_pointer, type, words);
if (t)
}
void
-md_number_to_chars (buf, val, n)
- char *buf;
- valueT val;
- int n;
+md_number_to_chars (char *buf, valueT val, int n)
{
number_to_chars_bigendian (buf, val, n);
}
-static void
-md_apply_fix_2 (fixP, val)
- fixS *fixP;
- offsetT val;
+void
+md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
{
+ offsetT val = *valP;
addressT upper_limit;
offsetT lower_limit;
to generate the code we want. */
char *buf = fixP->fx_frag->fr_literal;
buf += fixP->fx_where;
- /* end ibm compiler workaround */
+ /* End ibm compiler workaround. */
- if (val & 0x80000000)
- val |= ~(addressT)0x7fffffff;
- else
- val &= 0x7fffffff;
+ val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
+
+ if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
+ fixP->fx_done = 1;
#ifdef OBJ_ELF
if (fixP->fx_addsy)
{
memset (buf, 0, fixP->fx_size);
- fixP->fx_addnumber = val; /* Remember value for emit_reloc */
+ fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
+
+ if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+ && !S_IS_DEFINED (fixP->fx_addsy)
+ && !S_IS_WEAK (fixP->fx_addsy))
+ S_SET_WEAK (fixP->fx_addsy);
return;
}
#endif
+#ifdef BFD_ASSEMBLER
+ if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+ || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
+ return;
+#endif
+
switch (fixP->fx_size)
{
- /* The cast to offsetT below are necessary to make code correct for
- machines where ints are smaller than offsetT */
+ /* The cast to offsetT below are necessary to make code
+ correct for machines where ints are smaller than offsetT. */
case 1:
*buf++ = val;
upper_limit = 0x7f;
*buf++ = (val >> 8);
*buf++ = val;
upper_limit = 0x7fffffff;
- lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
+ lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
break;
default:
BAD_CASE (fixP->fx_size);
like "0xff" for a byte field. So extend the upper part of the range
to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
so that we can do any range checking at all. */
- if (!fixP->fx_pcrel)
+ if (! fixP->fx_pcrel && ! fixP->fx_signed)
upper_limit = upper_limit * 2 + 1;
if ((addressT) val > upper_limit
&& (val > 0 || val < lower_limit))
- as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
+ as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
/* A one byte PC-relative reloc means a short branch. We can't use
a short branch with a value of 0 or -1, because those indicate
- different opcodes (branches with longer offsets). */
- if (fixP->fx_pcrel
+ different opcodes (branches with longer offsets). fixup_segment
+ in write.c may have clobbered fx_pcrel, so we need to examine the
+ reloc type. */
+ if ((fixP->fx_pcrel
+#ifdef BFD_ASSEMBLER
+ || fixP->fx_r_type == BFD_RELOC_8_PCREL
+#endif
+ )
&& fixP->fx_size == 1
&& (fixP->fx_addsy == NULL
|| S_IS_DEFINED (fixP->fx_addsy))
&& (val == 0 || val == -1))
- as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
-}
-
-#ifdef BFD_ASSEMBLER
-int
-md_apply_fix (fixP, valp)
- fixS *fixP;
- valueT *valp;
-{
- md_apply_fix_2 (fixP, (addressT) *valp);
- return 1;
+ as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
}
-#else
-void md_apply_fix (fixP, val)
- fixS *fixP;
- long val;
-{
- md_apply_fix_2 (fixP, (addressT) val);
-}
-#endif
/* *fragP has been relaxed to its final size, and now needs to have
the bytes inside it modified to conform to the new size There is UGLY
MAGIC here. ..
*/
-void
-md_convert_frag_1 (fragP)
- register fragS *fragP;
+static void
+md_convert_frag_1 (fragS *fragP)
{
long disp;
- long ext = 0;
fixS *fixP;
/* Address in object code of the displacement. */
/* Address in gas core of the place to store the displacement. */
/* This convinces the native rs6000 compiler to generate the code we
- want. */
+ want. */
register char *buffer_address = fragP->fr_literal;
buffer_address += fragP->fr_fix;
- /* end ibm compiler workaround */
+ /* End ibm compiler workaround. */
/* The displacement of the address, from current location. */
disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
disp = (disp + fragP->fr_offset) - object_address;
-#ifdef BFD_ASSEMBLER
- disp += fragP->fr_symbol->sy_frag->fr_address;
-#endif
-
switch (fragP->fr_subtype)
{
- case TAB (BCC68000, BYTE):
- case TAB (ABRANCH, BYTE):
+ case TAB (BRANCHBWL, BYTE):
+ case TAB (BRABSJUNC, BYTE):
+ case TAB (BRABSJCOND, BYTE):
+ case TAB (BRANCHBW, BYTE):
know (issbyte (disp));
if (disp == 0)
- as_bad ("short branch with zero offset: use :w");
- fragP->fr_opcode[1] = disp;
- ext = 0;
- break;
- case TAB (DBCC, SHORT):
- know (issword (disp));
- ext = 2;
+ as_bad_where (fragP->fr_file, fragP->fr_line,
+ _("short branch with zero offset: use :w"));
+ fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
+ fragP->fr_offset, 1, RELAX_RELOC_PC8);
+ fixP->fx_pcrel_adjust = -1;
break;
- case TAB (BCC68000, SHORT):
- case TAB (ABRANCH, SHORT):
- know (issword (disp));
+ case TAB (BRANCHBWL, SHORT):
+ case TAB (BRABSJUNC, SHORT):
+ case TAB (BRABSJCOND, SHORT):
+ case TAB (BRANCHBW, SHORT):
fragP->fr_opcode[1] = 0x00;
- ext = 2;
+ fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
+ 1, RELAX_RELOC_PC16);
+ fragP->fr_fix += 2;
+ break;
+ case TAB (BRANCHBWL, LONG):
+ fragP->fr_opcode[1] = (char) 0xFF;
+ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
+ 1, RELAX_RELOC_PC32);
+ fragP->fr_fix += 4;
break;
- case TAB (ABRANCH, LONG):
- if (cpu_of_arch (current_architecture) < m68020)
+ case TAB (BRABSJUNC, LONG):
+ if (fragP->fr_opcode[0] == 0x61) /* jbsr */
{
- if (fragP->fr_opcode[0] == 0x61)
- /* BSR */
- {
- fragP->fr_opcode[0] = 0x4E;
- fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
-
- fix_new (fragP,
- fragP->fr_fix,
- 4,
- fragP->fr_symbol,
- fragP->fr_offset,
- 0,
- NO_RELOC);
-
- fragP->fr_fix += 4;
- ext = 0;
- }
- /* BRA */
- else if (fragP->fr_opcode[0] == 0x60)
- {
- fragP->fr_opcode[0] = 0x4E;
- fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
- fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
- fragP->fr_offset, 0, NO_RELOC);
- fragP->fr_fix += 4;
- ext = 0;
- }
- else
- {
- as_bad ("Long branch offset not supported.");
- }
+ if (flag_keep_pcrel)
+ as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
+ fragP->fr_opcode[0] = 0x4E;
+ fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
+ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
+ 0, RELAX_RELOC_ABS32);
+ fragP->fr_fix += 4;
+ }
+ else if (fragP->fr_opcode[0] == 0x60) /* jbra */
+ {
+ if (flag_keep_pcrel)
+ as_fatal (_("Tried to convert PC relative branch to absolute jump"));
+ fragP->fr_opcode[0] = 0x4E;
+ fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
+ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
+ 0, RELAX_RELOC_ABS32);
+ fragP->fr_fix += 4;
}
else
{
- fragP->fr_opcode[1] = (char) 0xff;
- ext = 4;
+ /* This cannot happen, because jbsr and jbra are the only two
+ unconditional branches. */
+ abort ();
}
break;
- case TAB (BCC68000, LONG):
- /* only Bcc 68000 instructions can come here */
- /* change bcc into b!cc/jmp absl long */
- fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
- fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
+ case TAB (BRABSJCOND, LONG):
+ if (flag_keep_pcrel)
+ as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
+
+ /* Only Bcc 68000 instructions can come here
+ Change bcc into b!cc/jmp absl long. */
+ fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
+ fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
/* JF: these used to be fr_opcode[2,3], but they may be in a
- different frag, in which case refering to them is a no-no.
- Only fr_opcode[0,1] are guaranteed to work. */
- *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
- *buffer_address++ = (char) 0xf9;
- fragP->fr_fix += 2; /* account for jmp instruction */
- fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
- fragP->fr_offset, 0, NO_RELOC);
- fragP->fr_fix += 4;
- ext = 0;
- break;
- case TAB (DBCC, LONG):
- /* only DBcc 68000 instructions can come here */
- /* change dbcc into dbcc/jmp absl long */
- /* JF: these used to be fr_opcode[2-7], but that's wrong */
- *buffer_address++ = 0x00; /* branch offset = 4 */
- *buffer_address++ = 0x04;
- *buffer_address++ = 0x60; /* put in bra pc+6 */
- *buffer_address++ = 0x06;
+ different frag, in which case referring to them is a no-no.
+ Only fr_opcode[0,1] are guaranteed to work. */
*buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
*buffer_address++ = (char) 0xf9;
-
- fragP->fr_fix += 6; /* account for bra/jmp instructions */
+ fragP->fr_fix += 2; /* Account for jmp instruction. */
fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
- fragP->fr_offset, 0, NO_RELOC);
+ fragP->fr_offset, 0, RELAX_RELOC_ABS32);
fragP->fr_fix += 4;
- ext = 0;
break;
case TAB (FBRANCH, SHORT):
know ((fragP->fr_opcode[1] & 0x40) == 0);
- ext = 2;
+ fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
+ 1, RELAX_RELOC_PC16);
+ fragP->fr_fix += 2;
break;
case TAB (FBRANCH, LONG):
- fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
- ext = 4;
+ fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
+ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
+ 1, RELAX_RELOC_PC32);
+ fragP->fr_fix += 4;
break;
- case TAB (PCREL, SHORT):
- ext = 2;
+ case TAB (DBCCLBR, SHORT):
+ case TAB (DBCCABSJ, SHORT):
+ fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
+ 1, RELAX_RELOC_PC16);
+ fragP->fr_fix += 2;
break;
- case TAB (PCREL, LONG):
- /* The thing to do here is force it to ABSOLUTE LONG, since
- PCREL is really trying to shorten an ABSOLUTE address anyway */
- /* JF FOO This code has not been tested */
- fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
- 0, NO_RELOC);
- if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
- as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
- (unsigned) fragP->fr_opcode[0],
- (unsigned long) fragP->fr_address);
- fragP->fr_opcode[1] &= ~0x3F;
- fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
+ case TAB (DBCCLBR, LONG):
+ /* Only DBcc instructions can come here.
+ Change dbcc into dbcc/bral.
+ JF: these used to be fr_opcode[2-7], but that's wrong. */
+ if (flag_keep_pcrel)
+ as_fatal (_("Tried to convert DBcc to absolute jump"));
+
+ *buffer_address++ = 0x00; /* Branch offset = 4. */
+ *buffer_address++ = 0x04;
+ *buffer_address++ = 0x60; /* Put in bra pc+6. */
+ *buffer_address++ = 0x06;
+ *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
+ *buffer_address++ = (char) 0xff;
+
+ fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
+ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
+ RELAX_RELOC_PC32);
fragP->fr_fix += 4;
- ext = 0;
break;
- case TAB (PCLEA, SHORT):
- fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
- fragP->fr_offset, 1, NO_RELOC);
+ case TAB (DBCCABSJ, LONG):
+ /* Only DBcc instructions can come here.
+ Change dbcc into dbcc/jmp.
+ JF: these used to be fr_opcode[2-7], but that's wrong. */
+ if (flag_keep_pcrel)
+ as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
+
+ *buffer_address++ = 0x00; /* Branch offset = 4. */
+ *buffer_address++ = 0x04;
+ *buffer_address++ = 0x60; /* Put in bra pc + 6. */
+ *buffer_address++ = 0x06;
+ *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
+ *buffer_address++ = (char) 0xf9;
+
+ fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
+ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
+ RELAX_RELOC_ABS32);
+ fragP->fr_fix += 4;
+ break;
+ case TAB (PCREL1632, SHORT):
fragP->fr_opcode[1] &= ~0x3F;
fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
- ext = 2;
+ fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
+ fragP->fr_offset, 1, RELAX_RELOC_PC16);
+ fragP->fr_fix += 2;
break;
- case TAB (PCLEA, LONG):
- fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
- fragP->fr_offset, 1, NO_RELOC);
- fixP->fx_pcrel_adjust = 2;
+ case TAB (PCREL1632, LONG):
/* Already set to mode 7.3; this indicates: PC indirect with
suppressed index, 32-bit displacement. */
*buffer_address++ = 0x01;
*buffer_address++ = 0x70;
fragP->fr_fix += 2;
- ext = 4;
+ fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
+ fragP->fr_offset, 1, RELAX_RELOC_PC32);
+ fixP->fx_pcrel_adjust = 2;
+ fragP->fr_fix += 4;
break;
-
case TAB (PCINDEX, BYTE):
- disp += 2;
- if (!issbyte (disp))
- {
- as_bad ("displacement doesn't fit in one byte");
- disp = 0;
- }
assert (fragP->fr_fix >= 2);
buffer_address[-2] &= ~1;
- buffer_address[-1] = disp;
- ext = 0;
+ fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
+ fragP->fr_offset, 1, RELAX_RELOC_PC8);
+ fixP->fx_pcrel_adjust = 1;
break;
case TAB (PCINDEX, SHORT):
- disp += 2;
- assert (issword (disp));
assert (fragP->fr_fix >= 2);
buffer_address[-2] |= 0x1;
buffer_address[-1] = 0x20;
fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
- fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
- NO_RELOC);
+ fragP->fr_offset, 1, RELAX_RELOC_PC16);
fixP->fx_pcrel_adjust = 2;
- ext = 2;
+ fragP->fr_fix += 2;
break;
case TAB (PCINDEX, LONG):
- disp += 2;
- fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
- fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
- NO_RELOC);
- fixP->fx_pcrel_adjust = 2;
assert (fragP->fr_fix >= 2);
buffer_address[-2] |= 0x1;
buffer_address[-1] = 0x30;
- ext = 4;
+ fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
+ fragP->fr_offset, 1, RELAX_RELOC_PC32);
+ fixP->fx_pcrel_adjust = 2;
+ fragP->fr_fix += 4;
+ break;
+ case TAB (ABSTOPCREL, SHORT):
+ fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
+ 1, RELAX_RELOC_PC16);
+ fragP->fr_fix += 2;
+ break;
+ case TAB (ABSTOPCREL, LONG):
+ if (flag_keep_pcrel)
+ as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
+ /* The thing to do here is force it to ABSOLUTE LONG, since
+ ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
+ if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
+ abort ();
+ fragP->fr_opcode[1] &= ~0x3F;
+ fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
+ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
+ 0, RELAX_RELOC_ABS32);
+ fragP->fr_fix += 4;
break;
- }
-
- if (ext)
- {
- md_number_to_chars (buffer_address, (long) disp, (int) ext);
- fragP->fr_fix += ext;
}
}
#ifndef BFD_ASSEMBLER
void
-md_convert_frag (headers, sec, fragP)
- object_headers *headers;
- segT sec;
- fragS *fragP;
+md_convert_frag (object_headers *headers ATTRIBUTE_UNUSED,
+ segT sec ATTRIBUTE_UNUSED,
+ fragS *fragP)
{
md_convert_frag_1 (fragP);
}
#else
void
-md_convert_frag (abfd, sec, fragP)
- bfd *abfd;
- segT sec;
- fragS *fragP;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+ segT sec ATTRIBUTE_UNUSED,
+ fragS *fragP)
{
md_convert_frag_1 (fragP);
}
the frag list to be relaxed
*/
int
-md_estimate_size_before_relax (fragP, segment)
- register fragS *fragP;
- segT segment;
+md_estimate_size_before_relax (fragS *fragP, segT segment)
{
- int old_fix;
- register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
-
- old_fix = fragP->fr_fix;
-
- /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
+ /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
switch (fragP->fr_subtype)
{
-
- case TAB (ABRANCH, SZ_UNDEF):
+ case TAB (BRANCHBWL, SZ_UNDEF):
+ case TAB (BRABSJUNC, SZ_UNDEF):
+ case TAB (BRABSJCOND, SZ_UNDEF):
{
- if ((fragP->fr_symbol != NULL) /* Not absolute */
- && S_GET_SEGMENT (fragP->fr_symbol) == segment)
+ if (S_GET_SEGMENT (fragP->fr_symbol) == segment
+ && relaxable_symbol (fragP->fr_symbol))
{
fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
- break;
- }
- else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
- {
- /* On 68000, or for absolute value, switch to abs long */
- /* FIXME, we should check abs val, pick short or long */
- if (fragP->fr_opcode[0] == 0x61)
- {
- fragP->fr_opcode[0] = 0x4E;
- fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
- fix_new (fragP, fragP->fr_fix, 4,
- fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
- fragP->fr_fix += 4;
- frag_wane (fragP);
- }
- else if (fragP->fr_opcode[0] == 0x60)
- {
- fragP->fr_opcode[0] = 0x4E;
- fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
- fix_new (fragP, fragP->fr_fix, 4,
- fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
- fragP->fr_fix += 4;
- frag_wane (fragP);
- }
- else
- {
- as_warn ("Long branch offset to extern symbol not supported.");
- }
- }
- else
- { /* Symbol is still undefined. Make it simple */
- fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
- fragP->fr_offset, 1, NO_RELOC);
- fragP->fr_fix += 4;
- fragP->fr_opcode[1] = (char) 0xff;
- frag_wane (fragP);
- break;
}
-
- break;
- } /* case TAB(ABRANCH,SZ_UNDEF) */
-
- case TAB (FBRANCH, SZ_UNDEF):
- {
- if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
+ else if (flag_short_refs)
{
- fragP->fr_subtype = TAB (FBRANCH, SHORT);
- fragP->fr_var += 2;
+ /* Symbol is undefined and we want short ref. */
+ fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
}
else
{
- fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
- fragP->fr_offset, 1, NO_RELOC);
- fragP->fr_fix += 4;
- fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
- frag_wane (fragP);
+ /* Symbol is still undefined. Make it LONG. */
+ fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
}
break;
- } /* TAB(FBRANCH,SZ_UNDEF) */
+ }
- case TAB (PCREL, SZ_UNDEF):
+ case TAB (BRANCHBW, SZ_UNDEF):
{
if (S_GET_SEGMENT (fragP->fr_symbol) == segment
- || flag_short_refs
- || cpu_of_arch (current_architecture) < m68020)
- {
- fragP->fr_subtype = TAB (PCREL, SHORT);
- fragP->fr_var += 2;
- }
- else
- {
- fragP->fr_subtype = TAB (PCREL, LONG);
- fragP->fr_var += 4;
- }
- break;
- } /* TAB(PCREL,SZ_UNDEF) */
-
- case TAB (BCC68000, SZ_UNDEF):
- {
- if ((fragP->fr_symbol != NULL)
- && S_GET_SEGMENT (fragP->fr_symbol) == segment)
- {
- fragP->fr_subtype = TAB (BCC68000, BYTE);
- break;
- }
- /* only Bcc 68000 instructions can come here */
- /* change bcc into b!cc/jmp absl long */
- fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
- if (flag_short_refs)
- {
- fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
- /* JF: these were fr_opcode[2,3] */
- buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
- buffer_address[1] = (char) 0xf8;
- fragP->fr_fix += 2; /* account for jmp instruction */
- fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
- fragP->fr_offset, 0, NO_RELOC);
- fragP->fr_fix += 2;
- }
- else
- {
- fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
- /* JF: these were fr_opcode[2,3] */
- buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
- buffer_address[1] = (char) 0xf9;
- fragP->fr_fix += 2; /* account for jmp instruction */
- fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
- fragP->fr_offset, 0, NO_RELOC);
- fragP->fr_fix += 4;
- }
- frag_wane (fragP);
- break;
- } /* case TAB(BCC68000,SZ_UNDEF) */
-
- case TAB (DBCC, SZ_UNDEF):
- {
- if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
- {
- fragP->fr_subtype = TAB (DBCC, SHORT);
- fragP->fr_var += 2;
- break;
- }
- /* only DBcc 68000 instructions can come here */
- /* change dbcc into dbcc/jmp absl long */
- /* JF: these used to be fr_opcode[2-4], which is wrong. */
- buffer_address[0] = 0x00; /* branch offset = 4 */
- buffer_address[1] = 0x04;
- buffer_address[2] = 0x60; /* put in bra pc + ... */
-
- if (flag_short_refs)
+ && relaxable_symbol (fragP->fr_symbol))
{
- /* JF: these were fr_opcode[5-7] */
- buffer_address[3] = 0x04; /* plus 4 */
- buffer_address[4] = 0x4e; /* Put in Jump Word */
- buffer_address[5] = (char) 0xf8;
- fragP->fr_fix += 6; /* account for bra/jmp instruction */
- fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
- fragP->fr_offset, 0, NO_RELOC);
- fragP->fr_fix += 2;
+ fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
}
else
{
- /* JF: these were fr_opcode[5-7] */
- buffer_address[3] = 0x06; /* Plus 6 */
- buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
- buffer_address[5] = (char) 0xf9;
- fragP->fr_fix += 6; /* account for bra/jmp instruction */
- fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
- fragP->fr_offset, 0, NO_RELOC);
- fragP->fr_fix += 4;
+ /* Symbol is undefined and we don't have long branches. */
+ fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
}
-
- frag_wane (fragP);
break;
- } /* case TAB(DBCC,SZ_UNDEF) */
+ }
- case TAB (PCLEA, SZ_UNDEF):
+ case TAB (FBRANCH, SZ_UNDEF):
+ case TAB (DBCCLBR, SZ_UNDEF):
+ case TAB (DBCCABSJ, SZ_UNDEF):
+ case TAB (PCREL1632, SZ_UNDEF):
{
- if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
- || flag_short_refs
- || cpu_of_arch (current_architecture) < m68020)
+ if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
+ && relaxable_symbol (fragP->fr_symbol))
+ || flag_short_refs)
{
- fragP->fr_subtype = TAB (PCLEA, SHORT);
- fragP->fr_var += 2;
+ fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
}
else
{
- fragP->fr_subtype = TAB (PCLEA, LONG);
- fragP->fr_var += 6;
+ fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
}
break;
- } /* TAB(PCLEA,SZ_UNDEF) */
+ }
case TAB (PCINDEX, SZ_UNDEF):
- if (S_GET_SEGMENT (fragP->fr_symbol) == segment
- || cpu_of_arch (current_architecture) < m68020)
+ if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
+ && relaxable_symbol (fragP->fr_symbol)))
{
fragP->fr_subtype = TAB (PCINDEX, BYTE);
}
else
{
fragP->fr_subtype = TAB (PCINDEX, LONG);
- fragP->fr_var += 4;
}
break;
+ case TAB (ABSTOPCREL, SZ_UNDEF):
+ {
+ if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
+ && relaxable_symbol (fragP->fr_symbol)))
+ {
+ fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
+ }
+ else
+ {
+ fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
+ }
+ break;
+ }
+
default:
break;
}
- /* now that SZ_UNDEF are taken care of, check others */
+ /* Now that SZ_UNDEF are taken care of, check others. */
switch (fragP->fr_subtype)
{
- case TAB (BCC68000, BYTE):
- case TAB (ABRANCH, BYTE):
- /* We can't do a short jump to the next instruction,
- so we force word mode. */
- if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
- fragP->fr_symbol->sy_frag == fragP->fr_next)
+ case TAB (BRANCHBWL, BYTE):
+ case TAB (BRABSJUNC, BYTE):
+ case TAB (BRABSJCOND, BYTE):
+ case TAB (BRANCHBW, BYTE):
+ /* We can't do a short jump to the next instruction, so in that
+ case we force word mode. If the symbol is at the start of a
+ frag, and it is the next frag with any data in it (usually
+ this is just the next frag, but assembler listings may
+ introduce empty frags), we must use word mode. */
+ if (fragP->fr_symbol)
{
- fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
- fragP->fr_var += 2;
+ fragS *sym_frag;
+
+ sym_frag = symbol_get_frag (fragP->fr_symbol);
+ if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
+ {
+ fragS *l;
+
+ for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
+ if (l->fr_fix != 0)
+ break;
+ if (l == sym_frag)
+ fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
+ }
}
break;
default:
break;
}
- return fragP->fr_var + fragP->fr_fix - old_fix;
+ return md_relax_table[fragP->fr_subtype].rlx_length;
}
#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
/* the bit-field entries in the relocation_info struct plays hell
with the byte-order problems of cross-assembly. So as a hack,
I added this mach. dependent ri twiddler. Ugly, but it gets
- you there. -KWK */
+ you there. -KWK */
/* on m68k: first 4 bytes are normal unsigned long, next three bytes
are symbolnum, most sig. byte first. Last byte is broken up with
bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
nibble as nuthin. (on Sun 3 at least) */
/* Translate the internal relocation information into target-specific
- format. */
+ format. */
#ifdef comment
void
-md_ri_to_chars (the_bytes, ri)
- char *the_bytes;
- struct reloc_info_generic *ri;
+md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
{
- /* this is easy */
+ /* This is easy. */
md_number_to_chars (the_bytes, ri->r_address, 4);
- /* now the fun stuff */
+ /* Now the fun stuff. */
the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
- the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
- the_bytes[6] = ri->r_symbolnum & 0x0ff;
- the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
- ((ri->r_extern << 4) & 0x10));
+ the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
+ the_bytes[6] = ri->r_symbolnum & 0x0ff;
+ the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
+ | ((ri->r_length << 5) & 0x60)
+ | ((ri->r_extern << 4) & 0x10));
}
-#endif /* comment */
+#endif
#ifndef BFD_ASSEMBLER
void
-tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
- char *where;
- fixS *fixP;
- relax_addressT segment_address_in_file;
+tc_aout_fix_to_chars (char *where, fixS *fixP,
+ relax_addressT segment_address_in_file)
{
/*
* In: length of relocation (or of address) in chars: 1, 2 or 4.
* Out: GNU LD relocation length code: 0, 1, or 2.
*/
- static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
+ static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
long r_symbolnum;
know (fixP->fx_addsy != NULL);
md_number_to_chars (where,
- fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
- 4);
+ (fixP->fx_frag->fr_address
+ + fixP->fx_where - segment_address_in_file), 4);
r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
? S_GET_TYPE (fixP->fx_addsy)
where[4] = (r_symbolnum >> 16) & 0x0ff;
where[5] = (r_symbolnum >> 8) & 0x0ff;
where[6] = r_symbolnum & 0x0ff;
- where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
- (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
+ where[7] = (((fixP->fx_pcrel << 7) & 0x80)
+ | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60)
+ | ((!S_IS_DEFINED (fixP->fx_addsy) << 4) & 0x10));
}
#endif
#endif /* OBJ_AOUT or OBJ_BOUT */
#ifndef WORKING_DOT_WORD
-CONST int md_short_jump_size = 4;
-CONST int md_long_jump_size = 6;
+const int md_short_jump_size = 4;
+const int md_long_jump_size = 6;
void
-md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
- char *ptr;
- addressT from_addr, to_addr;
- fragS *frag;
- symbolS *to_symbol;
+md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
+ fragS *frag ATTRIBUTE_UNUSED,
+ symbolS *to_symbol ATTRIBUTE_UNUSED)
{
valueT offset;
}
void
-md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
- char *ptr;
- addressT from_addr, to_addr;
- fragS *frag;
- symbolS *to_symbol;
+md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
+ fragS *frag, symbolS *to_symbol)
{
valueT offset;
- if (cpu_of_arch (current_architecture) < m68020)
+ if (!HAVE_LONG_BRANCH (current_architecture))
{
+ if (flag_keep_pcrel)
+ as_fatal (_("Tried to convert PC relative branch to absolute jump"));
offset = to_addr - S_GET_VALUE (to_symbol);
md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
md_number_to_chars (ptr + 2, (valueT) offset, 4);
aren't OK are an error (what a shock, no?)
0: Everything is OK
- 10: Absolute 1:8 only
- 20: Absolute 0:7 only
- 30: absolute 0:15 only
- 40: Absolute 0:31 only
- 50: absolute 0:127 only
+ 10: Absolute 1:8 only
+ 20: Absolute 0:7 only
+ 30: absolute 0:15 only
+ 40: Absolute 0:31 only
+ 50: absolute 0:127 only
55: absolute -64:63 only
- 60: absolute -128:127 only
- 70: absolute 0:4095 only
- 80: No bignums
-
- */
+ 60: absolute -128:127 only
+ 70: absolute 0:4095 only
+ 80: absolute -1, 1:7 only
+ 90: No bignums. */
static int
-get_num (exp, ok)
- struct m68k_exp *exp;
- int ok;
+get_num (struct m68k_exp *exp, int ok)
{
if (exp->exp.X_op == O_absent)
{
- /* Do the same thing the VAX asm does */
+ /* Do the same thing the VAX asm does. */
op (exp) = O_constant;
adds (exp) = 0;
subs (exp) = 0;
offs (exp) = 0;
if (ok == 10)
{
- as_warn ("expression out of range: defaulting to 1");
+ as_warn (_("expression out of range: defaulting to 1"));
offs (exp) = 1;
}
}
case 10:
if (offs (exp) < 1 || offs (exp) > 8)
{
- as_warn ("expression out of range: defaulting to 1");
+ as_warn (_("expression out of range: defaulting to 1"));
offs (exp) = 1;
}
break;
if (offs (exp) < 0 || offs (exp) > 4095)
{
outrange:
- as_warn ("expression out of range: defaulting to 0");
+ as_warn (_("expression out of range: defaulting to 0"));
offs (exp) = 0;
}
break;
+ case 80:
+ if (offs (exp) < -1
+ || offs (exp) > 7
+ || offs (exp) == 0)
+ {
+ as_warn (_("expression out of range: defaulting to 1"));
+ offs (exp) = 1;
+ }
+ break;
default:
break;
}
}
else if (exp->exp.X_op == O_big)
{
- if (offs (exp) <= 0 /* flonum */
- && (ok == 80 /* no bignums */
- || (ok > 10 /* small-int ranges including 0 ok */
+ if (offs (exp) <= 0 /* flonum. */
+ && (ok == 90 /* no bignums */
+ || (ok > 10 /* Small-int ranges including 0 ok. */
/* If we have a flonum zero, a zero integer should
do as well (e.g., in moveq). */
&& generic_floating_point_number.exponent == 0
&& generic_floating_point_number.low[0] == 0)))
{
- /* HACK! Turn it into a long */
+ /* HACK! Turn it into a long. */
LITTLENUM_TYPE words[6];
- gen_to_words (words, 2, 8L); /* These numbers are magic! */
+ gen_to_words (words, 2, 8L); /* These numbers are magic! */
op (exp) = O_constant;
adds (exp) = 0;
subs (exp) = 0;
adds (exp) = 0;
subs (exp) = 0;
offs (exp) = (ok == 10) ? 1 : 0;
- as_warn ("Can't deal with expression; defaulting to %ld",
+ as_warn (_("Can't deal with expression; defaulting to %ld"),
offs (exp));
}
}
else
{
- if (ok >= 10 && ok <= 70)
+ if (ok >= 10 && ok <= 80)
{
op (exp) = O_constant;
adds (exp) = 0;
subs (exp) = 0;
offs (exp) = (ok == 10) ? 1 : 0;
- as_warn ("Can't deal with expression; defaulting to %ld",
+ as_warn (_("Can't deal with expression; defaulting to %ld"),
offs (exp));
}
}
break;
case SIZE_BYTE:
if (!isbyte (offs (exp)))
- as_warn ("expression doesn't fit in BYTE");
+ as_warn (_("expression doesn't fit in BYTE"));
break;
case SIZE_WORD:
if (!isword (offs (exp)))
- as_warn ("expression doesn't fit in WORD");
+ as_warn (_("expression doesn't fit in WORD"));
break;
}
}
}
/* These are the back-ends for the various machine dependent pseudo-ops. */
-void demand_empty_rest_of_line (); /* Hate those extra verbose names */
static void
-s_data1 (ignore)
- int ignore;
+s_data1 (int ignore ATTRIBUTE_UNUSED)
{
subseg_set (data_section, 1);
demand_empty_rest_of_line ();
}
static void
-s_data2 (ignore)
- int ignore;
+s_data2 (int ignore ATTRIBUTE_UNUSED)
{
subseg_set (data_section, 2);
demand_empty_rest_of_line ();
}
static void
-s_bss (ignore)
- int ignore;
+s_bss (int ignore ATTRIBUTE_UNUSED)
{
/* We don't support putting frags in the BSS segment, we fake it
by marking in_bss, then looking at s_skip for clues. */
}
static void
-s_even (ignore)
- int ignore;
+s_even (int ignore ATTRIBUTE_UNUSED)
{
register int temp;
register long temp_fill;
temp = 1; /* JF should be 2? */
temp_fill = get_absolute_expression ();
- if (!need_pass_2) /* Never make frag if expect extra pass. */
- frag_align (temp, (int) temp_fill);
+ if (!need_pass_2) /* Never make frag if expect extra pass. */
+ frag_align (temp, (int) temp_fill, 0);
demand_empty_rest_of_line ();
+ record_alignment (now_seg, temp);
}
static void
-s_proc (ignore)
- int ignore;
+s_proc (int ignore ATTRIBUTE_UNUSED)
{
demand_empty_rest_of_line ();
}
\f
/* Pseudo-ops handled for MRI compatibility. */
+/* This function returns non-zero if the argument is a conditional
+ pseudo-op. This is called when checking whether a pending
+ alignment is needed. */
+
+int
+m68k_conditional_pseudoop (pseudo_typeS *pop)
+{
+ return (pop->poc_handler == s_mri_if
+ || pop->poc_handler == s_mri_else);
+}
+
/* Handle an MRI style chip specification. */
static void
-mri_chip ()
+mri_chip (void)
{
char *s;
char c;
int i;
s = input_line_pointer;
- c = get_symbol_end ();
+ /* We can't use get_symbol_end since the processor names are not proper
+ symbols. */
+ while (is_part_of_name (c = *input_line_pointer++))
+ ;
+ *--input_line_pointer = 0;
for (i = 0; i < n_archs; i++)
if (strcasecmp (s, archs[i].name) == 0)
break;
if (i >= n_archs)
{
- as_bad ("%s: unrecognized processor name", s);
+ as_bad (_("%s: unrecognized processor name"), s);
*input_line_pointer = c;
ignore_rest_of_line ();
return;
else
current_architecture &= m68881 | m68851;
current_architecture |= archs[i].arch;
+ current_chip = archs[i].chip;
while (*input_line_pointer == '/')
{
++input_line_pointer;
s = input_line_pointer;
- c = get_symbol_end ();
+ /* We can't use get_symbol_end since the processor names are not
+ proper symbols. */
+ while (is_part_of_name (c = *input_line_pointer++))
+ ;
+ *--input_line_pointer = 0;
if (strcmp (s, "68881") == 0)
current_architecture |= m68881;
else if (strcmp (s, "68851") == 0)
current_architecture |= m68851;
*input_line_pointer = c;
}
+
+ /* Update info about available control registers. */
+ select_control_regs ();
}
/* The MRI CHIP pseudo-op. */
static void
-s_chip (ignore)
- int ignore;
+s_chip (int ignore ATTRIBUTE_UNUSED)
{
char *stop = NULL;
char stopc;
/* The MRI FOPT pseudo-op. */
static void
-s_fopt (ignore)
- int ignore;
+s_fopt (int ignore ATTRIBUTE_UNUSED)
{
SKIP_WHITESPACE ();
input_line_pointer += 3;
temp = get_absolute_expression ();
if (temp < 0 || temp > 7)
- as_bad ("bad coprocessor id");
+ as_bad (_("bad coprocessor id"));
else
m68k_float_copnum = COP0 + temp;
}
else
{
- as_bad ("unrecognized fopt option");
+ as_bad (_("unrecognized fopt option"));
ignore_rest_of_line ();
return;
}
/* If this is not NULL, just call this function. The first argument
is the ARG field of this structure, the second argument is
whether the option was negated. */
- void (*pfn) PARAMS ((int arg, int on));
+ void (*pfn) (int arg, int on);
/* If this is not NULL, and the PFN field is NULL, set the variable
this points to. Set it to the ARG field if the option was not
/* The table used to handle the MRI OPT pseudo-op. */
-static void skip_to_comma PARAMS ((int, int));
-static void opt_nest PARAMS ((int, int));
-static void opt_chip PARAMS ((int, int));
-static void opt_list PARAMS ((int, int));
-static void opt_list_symbols PARAMS ((int, int));
+static void skip_to_comma (int, int);
+static void opt_nest (int, int);
+static void opt_chip (int, int);
+static void opt_list (int, int);
+static void opt_list_symbols (int, int);
static const struct opt_action opt_table[] =
{
{ "x", 0, 0, 0, 0 }
};
-#define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
+#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
/* The MRI OPT pseudo-op. */
static void
-s_opt (ignore)
- int ignore;
+s_opt (int ignore ATTRIBUTE_UNUSED)
{
do
{
else if (o->pvar != NULL)
{
if (! t && o->arg == o->notarg)
- as_bad ("option `%s' may not be negated", s);
+ as_bad (_("option `%s' may not be negated"), s);
*input_line_pointer = c;
*o->pvar = t ? o->arg : o->notarg;
}
}
if (i >= OPTCOUNT)
{
- as_bad ("option `%s' not recognized", s);
+ as_bad (_("option `%s' not recognized"), s);
*input_line_pointer = c;
}
}
}
/* Skip ahead to a comma. This is used for OPT options which we do
- not suppor tand which take arguments. */
+ not support and which take arguments. */
static void
-skip_to_comma (arg, on)
- int arg;
- int on;
+skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
{
while (*input_line_pointer != ','
&& ! is_end_of_line[(unsigned char) *input_line_pointer])
/* Handle the OPT NEST=depth option. */
static void
-opt_nest (arg, on)
- int arg;
- int on;
+opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
{
if (*input_line_pointer != '=')
{
- as_bad ("bad format of OPT NEST=depth");
+ as_bad (_("bad format of OPT NEST=depth"));
return;
}
/* Handle the OPT P=chip option. */
static void
-opt_chip (arg, on)
- int arg;
- int on;
+opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
{
if (*input_line_pointer != '=')
{
/* Handle the OPT S option. */
static void
-opt_list (arg, on)
- int arg;
- int on;
+opt_list (int arg ATTRIBUTE_UNUSED, int on)
{
listing_list (on);
}
/* Handle the OPT T option. */
static void
-opt_list_symbols (arg, on)
- int arg;
- int on;
+opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
{
if (on)
listing |= LISTING_SYMBOLS;
else
- listing &=~ LISTING_SYMBOLS;
+ listing &= ~LISTING_SYMBOLS;
}
/* Handle the MRI REG pseudo-op. */
static void
-s_reg (ignore)
- int ignore;
+s_reg (int ignore ATTRIBUTE_UNUSED)
{
char *s;
int c;
struct m68k_op rop;
- unsigned long mask;
+ int mask;
char *stop = NULL;
char stopc;
if (line_label == NULL)
{
- as_bad ("missing label");
+ as_bad (_("missing label"));
ignore_rest_of_line ();
return;
}
SKIP_WHITESPACE ();
s = input_line_pointer;
- while (isalnum ((unsigned char) *input_line_pointer)
+ while (ISALNUM (*input_line_pointer)
#ifdef REGISTER_PREFIX
|| *input_line_pointer == REGISTER_PREFIX
#endif
if (m68k_ip_op (s, &rop) != 0)
{
if (rop.error == NULL)
- as_bad ("bad register list");
+ as_bad (_("bad register list"));
else
- as_bad ("bad register list: %s", rop.error);
+ as_bad (_("bad register list: %s"), rop.error);
*input_line_pointer = c;
ignore_rest_of_line ();
return;
mask = 1 << 26;
else
{
- as_bad ("bad register list");
+ as_bad (_("bad register list"));
ignore_rest_of_line ();
return;
}
- S_SET_SEGMENT (line_label, absolute_section);
- S_SET_VALUE (line_label, mask);
- line_label->sy_frag = &zero_address_frag;
+ S_SET_SEGMENT (line_label, reg_section);
+ S_SET_VALUE (line_label, ~mask);
+ symbol_set_frag (line_label, &zero_address_frag);
if (flag_mri)
mri_comment_end (stop, stopc);
int keep_locals;
int short_refs;
int architecture;
+ int chip;
int quick;
int rel32;
int listing;
/* The MRI SAVE pseudo-op. */
static void
-s_save (ignore)
- int ignore;
+s_save (int ignore ATTRIBUTE_UNUSED)
{
struct save_opts *s;
s->keep_locals = flag_keep_locals;
s->short_refs = flag_short_refs;
s->architecture = current_architecture;
+ s->chip = current_chip;
s->quick = m68k_quick;
s->rel32 = m68k_rel32;
s->listing = listing;
/* The MRI RESTORE pseudo-op. */
static void
-s_restore (ignore)
- int ignore;
+s_restore (int ignore ATTRIBUTE_UNUSED)
{
struct save_opts *s;
if (save_stack == NULL)
{
- as_bad ("restore without save");
+ as_bad (_("restore without save"));
ignore_rest_of_line ();
return;
}
flag_keep_locals = s->keep_locals;
flag_short_refs = s->short_refs;
current_architecture = s->architecture;
+ current_chip = s->chip;
m68k_quick = s->quick;
m68k_rel32 = s->rel32;
listing = s->listing;
static int mri_control_index;
-/* Some function prototypes. */
-
-static char *mri_control_label PARAMS ((void));
-static struct mri_control_info *push_mri_control
- PARAMS ((enum mri_control_type));
-static void pop_mri_control PARAMS ((void));
-static int parse_mri_condition PARAMS ((int *));
-static int parse_mri_control_operand
- PARAMS ((int *, char **, char **, char **, char **));
-static int swap_mri_condition PARAMS ((int));
-static int reverse_mri_condition PARAMS ((int));
-static void build_mri_control_operand
- PARAMS ((int, int, char *, char *, char *, char *, const char *,
- const char *, int));
-static void parse_mri_control_expression
- PARAMS ((char *, int, const char *, const char *, int));
+/* Assemble an instruction for an MRI structured control directive. */
+
+static void
+mri_assemble (char *str)
+{
+ char *s;
+
+ /* md_assemble expects the opcode to be in lower case. */
+ for (s = str; *s != ' ' && *s != '\0'; s++)
+ *s = TOLOWER (*s);
+
+ md_assemble (str);
+}
/* Generate a new MRI label structured control directive label name. */
static char *
-mri_control_label ()
+mri_control_label (void)
{
char *n;
/* Create a new MRI structured control directive. */
static struct mri_control_info *
-push_mri_control (type)
- enum mri_control_type type;
+push_mri_control (enum mri_control_type type)
{
struct mri_control_info *n;
/* Pop off the stack of MRI structured control directives. */
static void
-pop_mri_control ()
+pop_mri_control (void)
{
struct mri_control_info *n;
/* Recognize a condition code in an MRI structured control expression. */
static int
-parse_mri_condition (pcc)
- int *pcc;
+parse_mri_condition (int *pcc)
{
char c1, c2;
if (*input_line_pointer != '>')
{
- as_bad ("syntax error in structured control directive");
+ as_bad (_("syntax error in structured control directive"));
return 0;
}
++input_line_pointer;
SKIP_WHITESPACE ();
- if (isupper (c1))
- c1 = tolower (c1);
- if (isupper (c2))
- c2 = tolower (c2);
+ c1 = TOLOWER (c1);
+ c2 = TOLOWER (c2);
*pcc = (c1 << 8) | c2;
/* Parse a single operand in an MRI structured control expression. */
static int
-parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
- int *pcc;
- char **leftstart;
- char **leftstop;
- char **rightstart;
- char **rightstop;
+parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
+ char **rightstart, char **rightstop)
{
char *s;
}
if (*s == '\0')
{
- as_bad ("missing condition code in structured control directive");
+ as_bad (_("missing condition code in structured control directive"));
return 0;
}
/* Look ahead for AND or OR or end of line. */
for (s = input_line_pointer; *s != '\0'; ++s)
{
- if ((strncasecmp (s, "AND", 3) == 0
- && (s[3] == '.' || ! is_part_of_name (s[3])))
- || (strncasecmp (s, "OR", 2) == 0
- && (s[2] == '.' || ! is_part_of_name (s[2]))))
+ /* We must make sure we don't misinterpret AND/OR at the end of labels!
+ if d0 <eq> #FOOAND and d1 <ne> #BAROR then
+ ^^^ ^^ */
+ if ((s == input_line_pointer
+ || *(s-1) == ' '
+ || *(s-1) == '\t')
+ && ((strncasecmp (s, "AND", 3) == 0
+ && (s[3] == '.' || ! is_part_of_name (s[3])))
+ || (strncasecmp (s, "OR", 2) == 0
+ && (s[2] == '.' || ! is_part_of_name (s[2])))))
break;
}
it generates the same result when the operands are swapped. */
static int
-swap_mri_condition (cc)
- int cc;
+swap_mri_condition (int cc)
{
switch (cc)
{
case MCC ('h', 'i'): return MCC ('c', 's');
case MCC ('l', 's'): return MCC ('c', 'c');
+ /* <HS> is an alias for <CC>. */
+ case MCC ('h', 's'):
case MCC ('c', 'c'): return MCC ('l', 's');
+ /* <LO> is an alias for <CS>. */
+ case MCC ('l', 'o'):
case MCC ('c', 's'): return MCC ('h', 'i');
case MCC ('p', 'l'): return MCC ('m', 'i');
case MCC ('m', 'i'): return MCC ('p', 'l');
case MCC ('l', 't'): return MCC ('g', 't');
case MCC ('g', 't'): return MCC ('l', 't');
case MCC ('l', 'e'): return MCC ('g', 'e');
+ /* Issue a warning for conditions we can not swap. */
+ case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
+ case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
+ case MCC ('v', 'c'):
+ case MCC ('v', 's'):
+ default :
+ as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
+ (char) (cc >> 8), (char) (cc));
+ break;
}
return cc;
}
/* Reverse the sense of a condition. */
static int
-reverse_mri_condition (cc)
- int cc;
+reverse_mri_condition (int cc)
{
switch (cc)
{
case MCC ('h', 'i'): return MCC ('l', 's');
case MCC ('l', 's'): return MCC ('h', 'i');
+ /* <HS> is an alias for <CC> */
+ case MCC ('h', 's'): return MCC ('l', 'o');
case MCC ('c', 'c'): return MCC ('c', 's');
+ /* <LO> is an alias for <CS> */
+ case MCC ('l', 'o'): return MCC ('h', 's');
case MCC ('c', 's'): return MCC ('c', 'c');
case MCC ('n', 'e'): return MCC ('e', 'q');
case MCC ('e', 'q'): return MCC ('n', 'e');
use for the branch. */
static void
-build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
- rightstop, truelab, falselab, extent)
- int qual;
- int cc;
- char *leftstart;
- char *leftstop;
- char *rightstart;
- char *rightstop;
- const char *truelab;
- const char *falselab;
- int extent;
+build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
+ char *rightstart, char *rightstop,
+ const char *truelab, const char *falselab,
+ int extent)
{
char *buf;
char *s;
{
char *temp;
- cc = swap_mri_condition (cc);
+ /* Correct conditional handling:
+ if #1 <lt> d0 then ;means if (1 < d0)
+ ...
+ endi
+
+ should assemble to:
+
+ cmp #1,d0 if we do *not* swap the operands
+ bgt true we need the swapped condition!
+ ble false
+ true:
+ ...
+ false:
+ */
temp = leftstart;
leftstart = rightstart;
rightstart = temp;
leftstop = rightstop;
rightstop = temp;
}
+ else
+ {
+ cc = swap_mri_condition (cc);
+ }
}
if (truelab == NULL)
cc = reverse_mri_condition (cc);
truelab = falselab;
}
-
+
if (leftstart != NULL)
{
buf = (char *) xmalloc (20
*s++ = 'm';
*s++ = 'p';
if (qual != '\0')
- *s++ = qual;
+ *s++ = TOLOWER (qual);
*s++ = ' ';
memcpy (s, leftstart, leftstop - leftstart);
s += leftstop - leftstart;
memcpy (s, rightstart, rightstop - rightstart);
s += rightstop - rightstart;
*s = '\0';
- md_assemble (buf);
+ mri_assemble (buf);
free (buf);
}
-
+
buf = (char *) xmalloc (20 + strlen (truelab));
s = buf;
*s++ = 'b';
*s++ = cc >> 8;
*s++ = cc & 0xff;
if (extent != '\0')
- *s++ = extent;
+ *s++ = TOLOWER (extent);
*s++ = ' ';
strcpy (s, truelab);
- md_assemble (buf);
+ mri_assemble (buf);
free (buf);
}
expression. EXTENT is the size to use for the branch. */
static void
-parse_mri_control_expression (stop, qual, truelab, falselab, extent)
- char *stop;
- int qual;
- const char *truelab;
- const char *falselab;
- int extent;
+parse_mri_control_expression (char *stop, int qual, const char *truelab,
+ const char *falselab, int extent)
{
int c;
int cc;
*stop = c;
if (input_line_pointer != stop)
- as_bad ("syntax error in structured control directive");
+ as_bad (_("syntax error in structured control directive"));
}
/* Handle the MRI IF pseudo-op. This may be a structured control
on its operands. */
static void
-s_mri_if (qual)
- int qual;
+s_mri_if (int qual)
{
char *s;
int c;
/* A structured control directive must end with THEN with an
optional qualifier. */
s = input_line_pointer;
- while (! is_end_of_line[(unsigned char) *s]
- && (! flag_mri || *s != '*'))
+ /* We only accept '*' as introduction of comments if preceded by white space
+ or at first column of a line (I think this can't actually happen here?)
+ This is important when assembling:
+ if d0 <ne> 12(a0,d0*2) then
+ if d0 <ne> #CONST*20 then. */
+ while (! (is_end_of_line[(unsigned char) *s]
+ || (flag_mri
+ && *s == '*'
+ && (s == input_line_pointer
+ || *(s-1) == ' '
+ || *(s-1) == '\t'))))
++s;
--s;
while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
{
if (qual != '\0')
{
- as_bad ("missing then");
+ as_bad (_("missing then"));
ignore_rest_of_line ();
return;
}
it is a conditional else. */
static void
-s_mri_else (qual)
- int qual;
+s_mri_else (int qual)
{
int c;
char *buf;
|| mri_control_stack->type != mri_if
|| mri_control_stack->else_seen)
{
- as_bad ("else without matching if");
+ as_bad (_("else without matching if"));
ignore_rest_of_line ();
return;
}
mri_control_stack->else_seen = 1;
buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
- q[0] = qual;
+ q[0] = TOLOWER (qual);
q[1] = '\0';
sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
- md_assemble (buf);
+ mri_assemble (buf);
free (buf);
colon (mri_control_stack->next);
/* Handle the MRI ENDI pseudo-op. */
static void
-s_mri_endi (ignore)
- int ignore;
+s_mri_endi (int ignore ATTRIBUTE_UNUSED)
{
if (mri_control_stack == NULL
|| mri_control_stack->type != mri_if)
{
- as_bad ("endi without matching if");
+ as_bad (_("endi without matching if"));
ignore_rest_of_line ();
return;
}
/* Handle the MRI BREAK pseudo-op. */
static void
-s_mri_break (extent)
- int extent;
+s_mri_break (int extent)
{
struct mri_control_info *n;
char *buf;
n = n->outer;
if (n == NULL)
{
- as_bad ("break outside of structured loop");
+ as_bad (_("break outside of structured loop"));
ignore_rest_of_line ();
return;
}
buf = (char *) xmalloc (20 + strlen (n->bottom));
- ex[0] = extent;
+ ex[0] = TOLOWER (extent);
ex[1] = '\0';
sprintf (buf, "bra%s %s", ex, n->bottom);
- md_assemble (buf);
+ mri_assemble (buf);
free (buf);
if (flag_mri)
/* Handle the MRI NEXT pseudo-op. */
static void
-s_mri_next (extent)
- int extent;
+s_mri_next (int extent)
{
struct mri_control_info *n;
char *buf;
n = n->outer;
if (n == NULL)
{
- as_bad ("next outside of structured loop");
+ as_bad (_("next outside of structured loop"));
ignore_rest_of_line ();
return;
}
buf = (char *) xmalloc (20 + strlen (n->next));
- ex[0] = extent;
+ ex[0] = TOLOWER (extent);
ex[1] = '\0';
sprintf (buf, "bra%s %s", ex, n->next);
- md_assemble (buf);
+ mri_assemble (buf);
free (buf);
if (flag_mri)
/* Handle the MRI FOR pseudo-op. */
static void
-s_mri_for (qual)
- int qual;
+s_mri_for (int qual)
{
const char *varstart, *varstop;
const char *initstart, *initstop;
++input_line_pointer;
if (*input_line_pointer != '=')
{
- as_bad ("missing =");
+ as_bad (_("missing ="));
ignore_rest_of_line ();
return;
}
}
if (initstop == NULL)
{
- as_bad ("missing to or downto");
+ as_bad (_("missing to or downto"));
ignore_rest_of_line ();
return;
}
}
if (endstop == NULL)
{
- as_bad ("missing do");
+ as_bad (_("missing do"));
ignore_rest_of_line ();
return;
}
}
if (bystop == NULL)
{
- as_bad ("missing do");
+ as_bad (_("missing do"));
ignore_rest_of_line ();
return;
}
}
/* We have fully parsed the FOR operands. Now build the loop. */
-
n = push_mri_control (mri_for);
buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
- /* move init,var */
+ /* Move init,var. */
s = buf;
*s++ = 'm';
*s++ = 'o';
*s++ = 'v';
*s++ = 'e';
if (qual != '\0')
- *s++ = qual;
+ *s++ = TOLOWER (qual);
*s++ = ' ';
memcpy (s, initstart, initstop - initstart);
s += initstop - initstart;
memcpy (s, varstart, varstop - varstart);
s += varstop - varstart;
*s = '\0';
- md_assemble (buf);
+ mri_assemble (buf);
colon (n->top);
- /* cmp end,var */
+ /* cmp end,var. */
s = buf;
*s++ = 'c';
*s++ = 'm';
*s++ = 'p';
if (qual != '\0')
- *s++ = qual;
+ *s++ = TOLOWER (qual);
*s++ = ' ';
memcpy (s, endstart, endstop - endstart);
s += endstop - endstart;
memcpy (s, varstart, varstop - varstart);
s += varstop - varstart;
*s = '\0';
- md_assemble (buf);
+ mri_assemble (buf);
- /* bcc bottom */
- ex[0] = extent;
+ /* bcc bottom. */
+ ex[0] = TOLOWER (extent);
ex[1] = '\0';
if (up)
sprintf (buf, "blt%s %s", ex, n->bottom);
else
sprintf (buf, "bgt%s %s", ex, n->bottom);
- md_assemble (buf);
+ mri_assemble (buf);
/* Put together the add or sub instruction used by ENDF. */
s = buf;
strcpy (s, "sub");
s += 3;
if (qual != '\0')
- *s++ = qual;
+ *s++ = TOLOWER (qual);
*s++ = ' ';
memcpy (s, bystart, bystop - bystart);
s += bystop - bystart;
/* Handle the MRI ENDF pseudo-op. */
static void
-s_mri_endf (ignore)
- int ignore;
+s_mri_endf (int ignore ATTRIBUTE_UNUSED)
{
if (mri_control_stack == NULL
|| mri_control_stack->type != mri_for)
{
- as_bad ("endf without for");
+ as_bad (_("endf without for"));
ignore_rest_of_line ();
return;
}
colon (mri_control_stack->next);
- md_assemble (mri_control_stack->incr);
+ mri_assemble (mri_control_stack->incr);
sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
- md_assemble (mri_control_stack->incr);
+ mri_assemble (mri_control_stack->incr);
free (mri_control_stack->incr);
/* Handle the MRI REPEAT pseudo-op. */
static void
-s_mri_repeat (ignore)
- int ignore;
+s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
{
struct mri_control_info *n;
/* Handle the MRI UNTIL pseudo-op. */
static void
-s_mri_until (qual)
- int qual;
+s_mri_until (int qual)
{
char *s;
if (mri_control_stack == NULL
|| mri_control_stack->type != mri_repeat)
{
- as_bad ("until without repeat");
+ as_bad (_("until without repeat"));
ignore_rest_of_line ();
return;
}
/* Handle the MRI WHILE pseudo-op. */
static void
-s_mri_while (qual)
- int qual;
+s_mri_while (int qual)
{
char *s;
struct mri_control_info *n;
s = input_line_pointer;
- while (! is_end_of_line[(unsigned char) *s]
- && (! flag_mri || *s != '*'))
+ /* We only accept '*' as introduction of comments if preceded by white space
+ or at first column of a line (I think this can't actually happen here?)
+ This is important when assembling:
+ while d0 <ne> 12(a0,d0*2) do
+ while d0 <ne> #CONST*20 do. */
+ while (! (is_end_of_line[(unsigned char) *s]
+ || (flag_mri
+ && *s == '*'
+ && (s == input_line_pointer
+ || *(s-1) == ' '
+ || *(s-1) == '\t'))))
s++;
--s;
while (*s == ' ' || *s == '\t')
if (s - input_line_pointer < 2
|| strncasecmp (s - 1, "DO", 2) != 0)
{
- as_bad ("missing do");
+ as_bad (_("missing do"));
ignore_rest_of_line ();
return;
}
/* Handle the MRI ENDW pseudo-op. */
static void
-s_mri_endw (ignore)
- int ignore;
+s_mri_endw (int ignore ATTRIBUTE_UNUSED)
{
char *buf;
if (mri_control_stack == NULL
|| mri_control_stack->type != mri_while)
{
- as_bad ("endw without while");
+ as_bad (_("endw without while"));
ignore_rest_of_line ();
return;
}
buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
sprintf (buf, "bra %s", mri_control_stack->next);
- md_assemble (buf);
+ mri_assemble (buf);
free (buf);
colon (mri_control_stack->bottom);
demand_empty_rest_of_line ();
}
\f
-/*
- * md_parse_option
- * Invocation line includes a switch not recognized by the base assembler.
- * See if it's a processor-specific option. These are:
- *
- * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
- * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
- * Select the architecture. Instructions or features not
- * supported by the selected architecture cause fatal
- * errors. More than one may be specified. The default is
- * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
- * for -m68000, and -m68882 is a synonym for -m68881.
- * -[A]m[c]no-68851, -[A]m[c]no-68881
- * Don't accept 688?1 instructions. (The "c" is kind of silly,
- * so don't use or document it, but that's the way the parsing
- * works).
- *
- * -pic Indicates PIC.
- * -k Indicates PIC. (Sun 3 only.)
- *
- */
+/* md_parse_option
+ Invocation line includes a switch not recognized by the base assembler.
+ See if it's a processor-specific option. These are:
+
+ -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
+ -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
+ Select the architecture. Instructions or features not
+ supported by the selected architecture cause fatal
+ errors. More than one may be specified. The default is
+ -m68020 -m68851 -m68881. Note that -m68008 is a synonym
+ for -m68000, and -m68882 is a synonym for -m68881.
+ -[A]m[c]no-68851, -[A]m[c]no-68881
+ Don't accept 688?1 instructions. (The "c" is kind of silly,
+ so don't use or document it, but that's the way the parsing
+ works).
+
+ -pic Indicates PIC.
+ -k Indicates PIC. (Sun 3 only.)
+ --pcrel
+ Never turn PC-relative branches into absolute jumps.
+ --bitwise-or
+ Permit `|' to be used in expressions. */
#ifdef OBJ_ELF
-CONST char *md_shortopts = "lSA:m:kQ:V";
+const char *md_shortopts = "lSA:m:kQ:V";
#else
-CONST char *md_shortopts = "lSA:m:k";
+const char *md_shortopts = "lSA:m:k";
#endif
struct option md_longopts[] = {
#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
{"register-prefix-optional", no_argument, NULL,
OPTION_REGISTER_PREFIX_OPTIONAL},
+#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
+ {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
+#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
+ {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
+#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
+ {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
+#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
+ {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
+#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
+ {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
+#define OPTION_PCREL (OPTION_MD_BASE + 7)
+ {"pcrel", no_argument, NULL, OPTION_PCREL},
{NULL, no_argument, NULL, 0}
};
-size_t md_longopts_size = sizeof(md_longopts);
+size_t md_longopts_size = sizeof (md_longopts);
int
-md_parse_option (c, arg)
- int c;
- char *arg;
+md_parse_option (int c, char *arg)
{
switch (c)
{
case 'l': /* -l means keep external to 2 bit offset
- rather than 16 bit one */
+ rather than 16 bit one. */
flag_short_refs = 1;
break;
flag_long_jumps = 1;
break;
+ case OPTION_PCREL: /* --pcrel means never turn PC-relative
+ branches into absolute jumps. */
+ flag_keep_pcrel = 1;
+ break;
+
case 'A':
if (*arg == 'm')
- arg++;
- /* intentional fall-through */
+ arg++;
+ /* Intentional fall-through. */
case 'm':
if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
if (!strcmp (arg, archs[i].name))
break;
if (i == n_archs)
- {
- unknown:
- as_bad ("unrecognized option `%s'", oarg);
- return 0;
- }
+ return 0;
+
arch = archs[i].arch;
if (arch == m68881)
no_68881 = 1;
else if (arch == m68851)
no_68851 = 1;
else
- goto unknown;
+ return 0;
}
else
{
if (!strcmp (arg, archs[i].name))
{
unsigned long arch = archs[i].arch;
+
if (cpu_of_arch (arch))
/* It's a cpu spec. */
{
current_architecture &= ~m68000up;
current_architecture |= arch;
+ current_chip = archs[i].chip;
}
else if (arch == m68881)
{
}
if (i == n_archs)
{
- as_bad ("unrecognized architecture specification `%s'", arg);
+ as_bad (_("unrecognized architecture specification `%s'"), arg);
return 0;
}
}
case OPTION_PIC:
case 'k':
flag_want_pic = 1;
- break; /* -pic, Position Independent Code */
+ break; /* -pic, Position Independent Code. */
case OPTION_REGISTER_PREFIX_OPTIONAL:
flag_reg_prefix_optional = 1;
case 'Q':
break;
+ case OPTION_BITWISE_OR:
+ {
+ char *n, *t;
+ const char *s;
+
+ n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
+ t = n;
+ for (s = m68k_comment_chars; *s != '\0'; s++)
+ if (*s != '|')
+ *t++ = *s;
+ *t = '\0';
+ m68k_comment_chars = n;
+ }
+ break;
+
+ case OPTION_BASE_SIZE_DEFAULT_16:
+ m68k_index_width_default = SIZE_WORD;
+ break;
+
+ case OPTION_BASE_SIZE_DEFAULT_32:
+ m68k_index_width_default = SIZE_LONG;
+ break;
+
+ case OPTION_DISP_SIZE_DEFAULT_16:
+ m68k_rel32 = 0;
+ m68k_rel32_from_cmdline = 1;
+ break;
+
+ case OPTION_DISP_SIZE_DEFAULT_32:
+ m68k_rel32 = 1;
+ m68k_rel32_from_cmdline = 1;
+ break;
+
default:
return 0;
}
}
void
-md_show_usage (stream)
- FILE *stream;
+md_show_usage (FILE *stream)
{
- fprintf(stream, "\
+ const char *default_cpu = TARGET_CPU;
+ int i;
+ unsigned int default_arch;
+
+ /* Get the canonical name for the default target CPU. */
+ if (*default_cpu == 'm')
+ default_cpu++;
+ for (i = 0; i < n_archs; i++)
+ {
+ if (strcasecmp (default_cpu, archs[i].name) == 0)
+ {
+ default_arch = archs[i].arch;
+ for (i = 0; i < n_archs; i++)
+ {
+ if (archs[i].arch == default_arch
+ && !archs[i].alias)
+ {
+ default_cpu = archs[i].name;
+ break;
+ }
+ }
+ }
+ }
+
+ fprintf (stream, _("\
680X0 options:\n\
-l use 1 word for refs to undefined symbols [default 2]\n\
--m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
- | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
- | -mcpu32\n\
- specify variant of 680X0 architecture [default 68020]\n\
+-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
+-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
+-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m521x | -m5249 |\n\
+-m528x | -m5307 | -m5407 | -m547x | -m548x | -mcfv4 | -mcfv4e\n\
+ specify variant of 680X0 architecture [default %s]\n\
-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
target has/lacks floating-point coprocessor\n\
- [default yes for 68020, 68030, and cpu32]\n");
- fprintf(stream, "\
+ [default yes for 68020, 68030, and cpu32]\n"),
+ default_cpu);
+ fprintf (stream, _("\
-m68851 | -mno-68851\n\
target has/lacks memory-management unit coprocessor\n\
[default yes for 68020 and up]\n\
-pic, -k generate position independent code\n\
-S turn jbsr into jsr\n\
+--pcrel never turn PC-relative branches into absolute jumps\n\
--register-prefix-optional\n\
- recognize register names without prefix character\n");
+ recognize register names without prefix character\n\
+--bitwise-or do not treat `|' as a comment character\n"));
+ fprintf (stream, _("\
+--base-size-default-16 base reg without size is 16 bits\n\
+--base-size-default-32 base reg without size is 32 bits (default)\n\
+--disp-size-default-16 displacement with unknown size is 16 bits\n\
+--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
}
\f
#ifdef TEST2
/* TEST2: Test md_assemble() */
-/* Warning, this routine probably doesn't work anymore */
-
-main ()
+/* Warning, this routine probably doesn't work anymore. */
+int
+main (void)
{
struct m68k_it the_ins;
char buf[120];
m68k_ip (&the_ins, buf);
if (the_ins.error)
{
- printf ("Error %s in %s\n", the_ins.error, buf);
+ printf (_("Error %s in %s\n"), the_ins.error, buf);
}
else
{
- printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
+ printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
for (n = 0; n < the_ins.numo; n++)
printf (" 0x%x", the_ins.opcode[n] & 0xffff);
printf (" ");
printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
continue;
}
- printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
+ printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
+ the_ins.operands[n].reg);
if (the_ins.operands[n].b_const)
- printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
- printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
+ printf ("Constant: '%.*s', ",
+ 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
+ the_ins.operands[n].b_const);
+ printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
+ the_ins.operands[n].isiz, the_ins.operands[n].imul);
if (the_ins.operands[n].b_iadd)
- printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
- (void) putchar ('\n');
+ printf ("Iadd: '%.*s',",
+ 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
+ the_ins.operands[n].b_iadd);
+ putchar ('\n');
}
}
m68k_ip_end ();
return 0;
}
-is_label (str)
- char *str;
+int
+is_label (char *str)
{
while (*str == ' ')
str++;
/* We have no need to default values of symbols. */
-/* ARGSUSED */
symbolS *
-md_undefined_symbol (name)
- char *name;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
{
return 0;
}
/* Round up a section size to the appropriate boundary. */
valueT
-md_section_align (segment, size)
- segT segment;
- valueT size;
+md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
{
- return size; /* Byte alignment is fine */
+#ifdef OBJ_AOUT
+#ifdef BFD_ASSEMBLER
+ /* For a.out, force the section size to be aligned. If we don't do
+ this, BFD will align it for us, but it will not write out the
+ final bytes of the section. This may be a bug in BFD, but it is
+ easier to fix it here since that is how the other a.out targets
+ work. */
+ int align;
+
+ align = bfd_get_section_alignment (stdoutput, segment);
+ size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
+#endif
+#endif
+
+ return size;
}
/* Exactly what point is a PC-relative offset relative TO?
On the 68k, it is relative to the address of the first extension
word. The difference between the addresses of the offset and the
- first extension word is stored in fx_pcrel_adjust. */
+ first extension word is stored in fx_pcrel_adjust. */
long
-md_pcrel_from (fixP)
- fixS *fixP;
+md_pcrel_from (fixS *fixP)
{
int adjust;
- /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
- -1 as 64. */
- adjust = fixP->fx_pcrel_adjust;
+ /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
+ sign extend the value here. */
+ adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
if (adjust == 64)
adjust = -1;
return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
}
#ifndef BFD_ASSEMBLER
-/*ARGSUSED*/
+#ifdef OBJ_COFF
+
void
-tc_coff_symbol_emit_hook (ignore)
- symbolS *ignore;
+tc_coff_symbol_emit_hook (symbolS *ignore ATTRIBUTE_UNUSED)
{
}
int
-tc_coff_sizemachdep (frag)
- fragS *frag;
+tc_coff_sizemachdep (fragS *frag)
{
switch (frag->fr_subtype & 0x3)
{
return 0;
}
}
+
+#endif
+#endif
+
+#ifdef OBJ_ELF
+void
+m68k_elf_final_processing (void)
+{
+ /* Set file-specific flags if this is a cpu32 processor. */
+ if (cpu_of_arch (current_architecture) & cpu32)
+ elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
+ else if ((cpu_of_arch (current_architecture) & m68000up)
+ && !(cpu_of_arch (current_architecture) & m68020up))
+ elf_elfheader (stdoutput)->e_flags |= EF_M68000;
+}
#endif
-/* end of tc-m68k.c */
+int
+tc_m68k_regname_to_dw2regnum (const char *regname)
+{
+ unsigned int regnum;
+ static const char *const regnames[] =
+ {
+ "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
+ "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
+ "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
+ "pc"
+ };
+
+ for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
+ if (strcmp (regname, regnames[regnum]) == 0)
+ return regnum;
+
+ return -1;
+}
+
+void
+tc_m68k_frame_initial_instructions (void)
+{
+ static int sp_regno = -1;
+
+ if (sp_regno < 0)
+ sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
+
+ cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
+ cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
+}
projects / deliverable / binutils-gdb.git / blobdiff