/* tc-mep.c -- Assembler for the Toshiba Media Processor.
- Copyright (C) 2001-2017 Free Software Foundation, Inc.
+ Copyright (C) 2001-2020 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
/* The MeP version of the cgen parse_operand function. The only difference
from the standard version is that we want to avoid treating '$foo' and
'($foo...)' as references to a symbol called '$foo'. The chances are
- that '$foo' is really a misspelt register. */
+ that '$foo' is really a misspelled register. */
static const char *
mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want,
an internally parallel core or an internally parallel coprocessor,
neither of which are supported at this time. */
if ( num_insns_saved > 2 )
- as_fatal("Internally paralled cores and coprocessors not supported.");
+ as_fatal("Internally paralleled cores and coprocessors not supported.");
/* If there are no insns saved, that's ok. Just return. This will
happen when mep_process_saved_insns is called when the end of the
1. The instruction is a 32 bit core or coprocessor insn and
can be executed by itself. Valid.
- 2. The instrucion is a core instruction for which a cop nop
+ 2. The instruction is a core instruction for which a cop nop
exists. In this case, insert the cop nop into the saved
insn array after the core insn and return. Valid.
mep_insn insn;
/* Move the insn and it's fixups to the second element of the
- saved insns arrary and insert a 16 bit core nope into the
+ saved insns array and insert a 16 bit core nope into the
first element. */
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
&insn.fields, insn.buffer,
1. The instruction is a 64 bit coprocessor insn and can be
executed by itself. Valid.
- 2. The instrucion is a core instruction for which a cop nop
+ 2. The instruction is a core instruction for which a cop nop
exists. In this case, insert the cop nop into the saved
insn array after the core insn and return. Valid.
we have to abort. */
/* If the insn is 64 bits long, it can run alone. The size check
- is done indepependantly of whether the insn is core or copro
+ is done independently of whether the insn is core or copro
in case 64 bit coprocessor insns are added later. */
if (insn0length == 64)
return;
#if CGEN_INT_INSN_P
cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) temp, 32,
- m->buffer[0]);
+ m->buffer[0], gas_cgen_cpu_desc->insn_endian);
#else
memcpy (temp, m->buffer, byte_len);
#endif
#endif /* MEP_IVC2_SUPPORTED */
/* The scheduling functions are just filters for invalid combinations.
- If there is a violation, they terminate assembly. Otherise they
+ If there is a violation, they terminate assembly. Otherwise they
just fall through. Successful combinations cause no side effects
other than valid nop insertion. */
valueT
md_section_align (segT segment, valueT size)
{
- int align = bfd_get_section_alignment (stdoutput, segment);
+ int align = bfd_section_alignment (segment);
return ((size + (1 << align) - 1) & -(1 << align));
}
|| S_IS_WEAK (fragP->fr_symbol)
#ifdef MEP_IVC2_SUPPORTED
|| (mep_cop == EF_MEP_COP_IVC2
- && bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW)
+ && bfd_section_flags (segment) & SEC_MEP_VLIW)
#endif /* MEP_IVC2_SUPPORTED */
)
{
}
if (MEP_VLIW && ! MEP_VLIW64
- && (bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW))
+ && (bfd_section_flags (segment) & SEC_MEP_VLIW))
{
/* Use 32 bit branches for vliw32 so the vliw word is not split. */
switch (fragP->fr_cgen.insn->base->num)
#ifdef MEP_IVC2_SUPPORTED
if (mep_cop == EF_MEP_COP_IVC2
- && bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW)
+ && bfd_section_flags (segment) & SEC_MEP_VLIW)
return 0;
#endif /* MEP_IVC2_SUPPORTED */
long rv = relax_frag (segment, fragP, stretch);
#ifdef MEP_IVC2_SUPPORTED
if (mep_cop == EF_MEP_COP_IVC2
- && bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW)
+ && bfd_section_flags (segment) & SEC_MEP_VLIW)
return 0;
#endif
return rv;
int core_mode;
#ifdef MEP_IVC2_SUPPORTED
- if (bfd_get_section_flags (stdoutput, seg) & SEC_MEP_VLIW
+ if (bfd_section_flags (seg) & SEC_MEP_VLIW
&& mep_cop == EF_MEP_COP_IVC2)
core_mode = 0;
else
switch (fixP->fx_cgen.opinfo)
{
case BFD_RELOC_MEP_LOW16:
- *valP = ((long)(*valP & 0xffff)) << 16 >> 16;
+ *valP = ((*valP & 0xffff) ^ 0x8000) - 0x8000;
break;
case BFD_RELOC_MEP_HI16U:
*valP >>= 16;
break;
}
- /* Now call cgen's md_aply_fix. */
+ /* Now call cgen's md_apply_fix. */
gas_cgen_md_apply_fix (fixP, valP, seg);
}
{
flagword applicable = bfd_applicable_section_flags (stdoutput);
vtext_section = subseg_new (VTEXT_SECTION_NAME, 0);
- bfd_set_section_flags (stdoutput, vtext_section,
+ bfd_set_section_flags (vtext_section,
applicable & (SEC_ALLOC | SEC_LOAD | SEC_RELOC
| SEC_CODE | SEC_READONLY
| SEC_MEP_VLIW));