OPTION_NO_LOONGSON_MMI,
OPTION_LOONGSON_CAM,
OPTION_NO_LOONGSON_CAM,
+ OPTION_LOONGSON_EXT,
+ OPTION_NO_LOONGSON_EXT,
OPTION_END_OF_ENUM
};
{"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI},
{"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM},
{"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM},
+ {"mloongson-ext", no_argument, NULL, OPTION_LOONGSON_EXT},
+ {"mno-loongson-ext", no_argument, NULL, OPTION_NO_LOONGSON_EXT},
/* Old-style architecture options. Don't add more of these. */
{"m4650", no_argument, NULL, OPTION_M4650},
OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM,
0, 0, -1, -1,
-1 },
+
+ { "loongson-ext", ASE_LOONGSON_EXT, 0,
+ OPTION_LOONGSON_EXT, OPTION_NO_LOONGSON_EXT,
+ 0, 0, -1, -1,
+ -1 },
};
/* The set of ASEs that require -mfp64. */
ext_ases |= AFL_ASE_LOONGSON_MMI;
if (ase & ASE_LOONGSON_CAM)
ext_ases |= AFL_ASE_LOONGSON_CAM;
+ if (ase & ASE_LOONGSON_EXT)
+ ext_ases |= AFL_ASE_LOONGSON_EXT;
return ext_ases;
}
/* MIPS 64 Release 2 */
/* Loongson CPU core */
- { "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM, ISA_MIPS64R2,
- CPU_LOONGSON_3A },
+ { "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
+ ISA_MIPS64R2, CPU_LOONGSON_3A },
/* Cavium Networks Octeon CPU core */
{ "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
-mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
-mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
fprintf (stream, _("\
+-mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
+-mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
+ fprintf (stream, _("\
-minsn32 only generate 32-bit microMIPS instructions\n\
-mno-insn32 generate all microMIPS instructions\n"));
fprintf (stream, _("\